Analog front-end circuit applied to ultra-high-speed serdes receiver

Abstract

The application relates to the technical field of integrated circuits, and discloses an analog front-end circuit applied to a super-high-speed SerDes receiver, a transimpedance amplifier of which comprises a pair of input transistors, the gates of which are connected and connected with a T coil composed of a first inductor and a second inductor, one end of the first inductor is connected with the gate and connected in parallel with a second capacitor, the other end receives a front-stage input and is connected in parallel with one end of the second inductor and a first capacitor, the drains of the input transistors are connected and connected with a T coil composed of a fifth inductor and a sixth inductor, one end of the sixth inductor is connected with the drain and connected in parallel with a third capacitor, the other end outputs an amplified signal and is connected in parallel with one end of the fifth inductor and a fourth capacitor, and the other end of the second inductor and the other end of the fifth inductor are directly connected in series with a first resistor and a third inductor. The application optimizes zero-pole compensation high-frequency loss and optimizes impedance matching to reduce reflection, and better guarantees the integrity of signals.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an analog front-end circuit for an ultra-high-speed SerDes receiver, and a SerDes receiver including the analog front-end circuit. Background Technology

[0002] With the continuous increase in transmission speeds driven by applications such as data centers, AI computing, and high-speed interconnects, SerDes (serializer / deserializer) technology has been widely applied in high-speed communication systems such as PCIe, Ethernet, InfiniBand, and optical interconnects. Currently, the transmission rates of commercial SerDes receivers are evolving from 56Gbps to 112Gbps, 224Gbps, and even 448Gbps.

[0003] At such high data rates, the frequency response characteristics of the channel will degrade significantly, high-frequency signal components will be severely attenuated, and accompanied by strong reflections and inter-symbol interference (ISI). Therefore, the performance of the analog front-end (AFE), as the first processing module in the signal receiving path, will directly affect the signal integrity of the entire link.

[0004] In existing technologies, mainstream AFEs typically employ a structure consisting of a continuous-time linear equalizer (CTLE) and a trans-impedance amplifier (TIA) connected in series. The CTLE is used for front-end optimization compensation in the analog domain, while the TIA is responsible for current-to-voltage conversion and gain control. However, with the increase in data rates, this architecture suffers from the following key problems:

[0005] 1. Bandwidth limitation: Parasitic capacitances at the input (such as PADs, ESD protection devices, CTLE input transistors, etc.) and resistors form poles in the low-pass filter, which significantly limits the system bandwidth;

[0006] 2. Insufficient gain peaking: The feedback network of traditional TIA is usually a simple RC structure, which makes it difficult to achieve effective gain peaking at high frequencies (such as 56GHz and above);

[0007] 3. Severe noise and reflection problems: Poor input impedance matching leads to increased return loss, further degrading signal integrity; parasitic capacitance caused by ESD protection circuits cannot be effectively managed, becoming a performance bottleneck;

[0008] 4. Insufficient adjustability and robustness: The existing structure lacks the ability to flexibly adapt to different rates and channel loss conditions, making it difficult to meet the development needs of future high-speed interconnection protocols.

[0009] Therefore, there is an urgent need for an analog front-end circuit structure with high bandwidth, high gain peaking capability, excellent matching characteristics, and the ability to balance ESD protection and process feasibility, in order to meet the application requirements of 56Gbps to 448Gbps ultra-high-speed SerDes receivers. Summary of the Invention

[0010] The purpose of this application is to provide an analog front-end circuit for ultra-high-speed SerDes receivers. By optimizing zero-pole compensation for high-frequency losses and optimizing impedance matching to reduce reflections, it solves the problems of limited bandwidth, difficult matching, and insufficient high-frequency gain compensation in existing AFEs, and provides better system adjustability, anti-reflection capability, and signal integrity assurance.

[0011] In a first aspect, this application provides an analog front-end circuit for a SerDes receiver, comprising an input matching network, a continuous-time linear equalizer, and a transimpedance amplifier connected in sequence, wherein:

[0012] The transimpedance amplifier includes a pair of input transistors. The gates of the pair of input transistors are connected and connected to a T-coil composed of a first inductor and a second inductor. One end of the first inductor is connected to the gate and in parallel to a second parasitic capacitor at the input of the pair of input transistors. The other end of the first inductor receives the input from the previous stage and is in parallel to one end of the second inductor and the first parasitic capacitor at the previous stage. The drains of the pair of input transistors are connected and connected to a T-coil composed of a third inductor and a fourth inductor. One end of the third inductor is connected to the drain and in parallel to a third parasitic capacitor at the output of the pair of input transistors. The other end of the third inductor outputs an amplified signal and is in parallel to one end of the fourth inductor and a fourth capacitor. The other ends of the second inductor and the other ends of the fourth inductor are directly connected in series with a first resistor and a fifth inductor.

[0013] In a preferred embodiment, a second resistor and a sixth inductor are connected in parallel across the two ends of the third inductor.

[0014] In a preferred embodiment, the pair of input transistors includes a first transistor and a second transistor, the first transistor being a PMOS transistor and the second transistor being an NMOS transistor, with a parasitic fifth capacitance between the first transistor and the second transistor.

[0015] In a preferred embodiment, the input matching network includes a pair of differential input matching branches. Each input matching branch includes a seventh inductor, a first electrostatic discharge (ESD) protection unit, an eighth inductor, a second ESD protection unit, a ninth inductor, a tenth inductor, and an eighth capacitor connected in sequence. The seventh inductor is connected to an input pad, which has a parasitic sixth capacitor. The node between the ninth inductor and the eighth capacitor is connected to one end of a third resistor through the tenth inductor. The first and second ESD protection units each include a diode discharge path and a seventh capacitor parasitized by the diode connected in sequence. The diode discharge path includes a first diode and a second diode connected in series. The anode of the first diode is grounded, and the cathode of the first diode is connected to the anode of the second diode and one end of the seventh capacitor. The cathode of the second diode is connected to a power supply, and the other end of the seventh capacitor is grounded.

[0016] In this pair of differential input matching branches, the other end of the third resistor is connected to and connected to the reference voltage.

[0017] In a preferred embodiment, each input matching branch further includes a ninth and a tenth capacitor parasitized by the eighth capacitor, wherein one end of the ninth capacitor is connected to one end of the eighth capacitor and the other end of the ninth capacitor is grounded; one end of the tenth capacitor is connected to the other end of the eighth capacitor and the other end of the tenth capacitor is grounded.

[0018] In a preferred embodiment, the inductance value of the ninth inductor is less than the inductance value of the tenth inductor.

[0019] In a preferred embodiment, the output of each input matching branch is connected to the input of the continuous-time linear equalizer.

[0020] In a second aspect, this application also provides a SerDes receiver, including the aforementioned analog front-end circuitry.

[0021] The embodiments of this application have at least the following beneficial effects:

[0022] First, in this application's TIA, the first and second inductors isolate the parasitic capacitance of the preceding stage and reduce the bandwidth reduction caused by the pole formed by the parasitic capacitance of the preceding stage and the gate resistance of the pair of differential input transistors. The third and fourth inductors isolate the output parasitic capacitance and the load capacitance and reduce the bandwidth reduction caused by the pole formed by the output parasitic capacitance and the output resistance of the pair of differential input transistors. This results in controllable peaking at 56GHz and above, more uniform gain within the frequency band, and higher eye diagram quality.

[0023] Furthermore, the second resistor and the sixth inductor in the TIA constitute a De-Q circuit. By introducing the De-Q circuit into the TIA, the inductor plays a dominant role at low frequencies to complete peaking. At high frequencies, the second resistor reduces the Q value of the fifth inductor and decreases the inductance value to ensure the stability of the loop, thereby achieving a design that is compatible with high-frequency gain and system stability.

[0024] Secondly, by employing two small electrostatic discharge protection units in the input matching network, independent conduction paths are maintained under ESD events, while a relatively close pole is split into two very distant poles, effectively ensuring bandwidth and ESD resistance.

[0025] Furthermore, the selection of the values ​​of the ninth and tenth inductors allows for a trade-off between bandwidth and impedance matching. Larger inductance values ​​provide greater impedance assistance to the third resistor at high frequencies, resulting in better return loss; smaller inductance values ​​result in lower parasitic resistance and are further removed from the poles created by the capacitor, thus aiding in bandwidth expansion. Moreover, the ninth and tenth inductors form an asymmetrical T-coil, ensuring both bandwidth and better impedance matching.

[0026] It should be understood that, within the scope of this invention, the above-described technical features of this invention and the technical features specifically described below (such as in the embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, they will not be described in detail here. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. It should be understood that the accompanying drawings described below are merely some implementation examples of the present invention, and those skilled in the art can obtain other implementation examples based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the circuit structure of a transimpedance amplifier according to one embodiment of this application.

[0029] Figure 2 This is a schematic diagram of the circuit structure of an input matching network according to one embodiment of this application.

[0030] Figure 3 The results are simulation results of the input matching network based on one embodiment of this application, using 224Gbps as an example.

[0031] Figure 4 The results are simulation results of a transimpedance amplifier with a bandwidth of 224Gbps, based on one embodiment of this application. Detailed Implementation

[0032] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0034] One embodiment of this application relates to an analog front-end circuit for a SerDes receiver. The analog front-end (AFE) circuit includes an input matching network, a continuous-time linear equalizer (CTLE), a transconductance (Gm) buffer, and a transimpedance amplifier (TIA) connected in sequence. The input matching network adjusts the impedance at the receiver input to match the characteristic impedance of the signal source or transmission line. The CTLE is used to recover the high-frequency components of the signal in the analog domain, improving signal integrity and is a key frequency domain compensation unit. The Gm buffer converts the voltage input into a proportional current output, facilitating the response of subsequent current processing devices. The TIA converts the current signal output from the Gm buffer into a voltage signal output.

[0035] The structure of the transimpedance amplifier is as follows: Figure 1 As shown, the transimpedance amplifier includes a pair of input transistors, namely a first transistor M1 and a second transistor M2. The first transistor M1 is a PMOS transistor, and the second transistor M2 is an NMOS transistor. The gates of the first transistor M1 and the second transistor M2 are connected together and connected to a T-coil composed of a first inductor T1 and a second inductor T2. One end of the first inductor T1 is connected to the gate and connected in parallel to a second capacitor C2 (i.e., the input parasitic capacitance of the pair of input transistors). The other end of the first inductor T1 receives the input from the previous stage and is connected in parallel to one end of the second inductor C2 and the first capacitor C1 (i.e., the previous stage parasitic capacitance).

[0036] In this embodiment, the first inductor L1 in the TIA isolates the parasitic capacitance C1 from the preceding stage. The T-coil formed by the first inductor L1 and the second inductor L2 reduces the bandwidth reduction caused by the pole formed by the parasitic capacitance C1 and the gate resistance of the pair of differential input transistors. The drains of the first transistor M1 and the second transistor M2 are connected and connected to a T-coil formed by the third inductor L3 and the fourth inductor L4. One end of the third inductor L3 is connected to the drain and connected in parallel to the third capacitor C3 (i.e., the output parasitic capacitance of the pair of input transistors). The other end of the third inductor L3 outputs the amplified signal and is connected in parallel to one end of the fourth inductor L4 and the fourth capacitor C4 (i.e., the load capacitance). Furthermore, the third inductor L3 and the fourth inductor L4 isolate the output parasitic capacitance and the load capacitance. The T-coil formed by the third inductor L3 and the fourth inductor L4 reduces the bandwidth reduction caused by the pole formed by the output parasitic capacitance C3 and the output resistance of the pair of differential input transistors. By designing the inductor and capacitor in the TIA feedback path, controllable peaking is achieved at 56GHz and above, resulting in more uniform gain within the frequency band and higher eye diagram quality.

[0037] In one embodiment, a fifth capacitor C5 is provided between the first transistor M1 and the second transistor M2, which is a parasitic capacitance of the pair of input transistors.

[0038] Continue to refer to Figure 1 As shown, the other ends of the second inductor L2 and the fourth inductor L4 are directly connected in series with the first resistor R1 and the fifth inductor T5. In one embodiment, the two ends of the third inductor L3 are connected in parallel with the second resistor R2 and the sixth inductor L6. In the TIA, the second resistor R2 and the sixth inductor L6 constitute a De-Q circuit. Introducing the De-Q circuit into the TIA allows the inductor to play a dominant role at low frequencies, completing peaking. At high frequencies, the second resistor R2 reduces the Q value of the fifth inductor L5, thus reducing its inductance and ensuring loop stability. This achieves a design that balances high-frequency gain and system stability.

[0039] The input matching network structure is as follows: Figure 2As shown, the input matching network includes a pair of differential input matching branches, which are connected to pads PAD_N and PAD_P respectively, receiving a pair of differential input signals. Each input matching branch includes, in sequence, a seventh inductor L7, a first electrostatic discharge (ESD) protection unit 11, an eighth inductor L8, a second ESD protection unit 12, a ninth inductor L9, a tenth inductor L10, and an eighth capacitor C8 (i.e., a DC blocking capacitor). The seventh inductor L7 is connected to either input pad PAD_N or PAD_P, and the input pad has a parasitic sixth capacitor C6. The node between the ninth inductor L9 and the eighth capacitor C8 is connected to one end of the third resistor R3 through the tenth inductor L10. The other end of the third resistor R3 in the pair of differential input matching branches is connected to and linked to the reference voltage vref.

[0040] The first electrostatic discharge (ESD) protection unit 11 includes a diode discharge path and a seventh capacitor C7 (i.e., the parasitic capacitance of the diode) connected in sequence. The diode discharge path includes a first diode D1 and a second diode D2 connected in series. The anode of the first diode D1 is grounded, and the cathode of the first diode D1 is connected to the anode of the second diode D2 and one end of the seventh capacitor C7. The cathode of the second diode D2 is connected to the power supply Vdd, and the other end of the seventh capacitor C7 is grounded. The second ESD protection unit 12 includes a diode discharge path and a seventh capacitor C7' connected in sequence. The diode discharge path includes a first diode D1' and a second diode D2' connected in series. The anode of the first diode D1' is grounded, and the cathode of the first diode D1' is connected to the anode of the second diode D2' and one end of the seventh capacitor C7'. The cathode of the second diode D2' is connected to the power supply Vdd, and the other end of the seventh capacitor C7' is grounded. In this embodiment, by using two small ESD protection units 11 and 12 in the input matching network, independent conduction paths are maintained under ESD events, while a relatively close pole is split into two very far poles, effectively ensuring bandwidth and ESD resistance.

[0041] In one embodiment, the diodes in the first electrostatic discharge protection unit 11 and the second electrostatic discharge protection unit 12 are of the same size.

[0042] In one embodiment, each input matching branch further includes a ninth capacitor C9 and a tenth capacitor C10, which are parasitic capacitances of the eighth capacitor C8, respectively. One end of the ninth capacitor C9 is connected to one end of the eighth capacitor C8, and the other end is grounded. One end of the tenth capacitor C10 is connected to the other end of the eighth capacitor C8, and the other end is grounded. The output of each input matching branch is coupled to the input of the continuous-time linear equalizer CTLE. The selection of the values ​​of the ninth inductor L9 and the tenth inductor L10 allows for a trade-off between bandwidth and impedance matching. A larger inductance value provides greater impedance assistance to the third resistor R3 at high frequencies, resulting in better return loss; a smaller inductance value results in lower parasitic resistance and a greater distance from the poles generated by the capacitor, which helps extend the bandwidth. Furthermore, the inductance value of the ninth inductor L9 is smaller than that of the tenth inductor L10, and the ninth and tenth inductors form an asymmetrical T-coil, achieving better impedance matching while ensuring bandwidth.

[0043] This application discloses an analog front-end circuit for an ultra-high-speed SerDes receiver. The circuit employs a cascaded structure of an input matching network, a continuous-time linear equalizer (CTLE), and a transimpedance amplifier (TIA). Multiple T-Coil networks and De-Q circuits are introduced into the TIA to enhance bandwidth and achieve high-frequency gain peaking. Simultaneously, an asymmetric T-Coil input matching network optimizes impedance matching and reduces return loss. This analog front-end structure is suitable for ultra-high-speed receiving systems ranging from 56Gbps to 448Gbps, offering advantages such as wide bandwidth, strong anti-reflection capability, and high signal integrity.

[0044] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0045] In SerDes systems with speeds of 56 Gbps and above, high-frequency channel losses and reflections cause severe signal degradation. Traditional AFEs employ a cascaded CTLE and TIA structure, but suffer from bandwidth limitations, insufficient gain peaking, and noise superposition. In existing technologies, TIA feedback networks are mostly purely resistive or simple RC structures, which are insufficient to compensate for channel attenuation above 56 GHz. Furthermore, input stage parasitic capacitance and inductance mismatch lead to reflections, limiting overall performance. This invention proposes an improved AFE structure that combines T-Coil broadband matching, CTLE-TIA joint optimization, and a high-order feedback network, providing effective bandwidth and adjustable gain peaking within speeds from 56 to 448 Gbps.

[0046] The input network is matched using asymmetric T-coil and transmission line theory. To enhance ESD protection, the selected diode size cannot be too small, but a larger diode implies a larger parasitic capacitance, which would drastically degrade the bandwidth. Therefore, the ESD protection diode is divided into two equal parts, with a small inductor forming physical isolation between them. This ensures an independent conduction path under ESD events while splitting a relatively close pole into two very distant poles, effectively guaranteeing bandwidth and ESD resistance. The ESD protection diode meets the specifications of HBM greater than 2000V and CDM greater than 200V, and the inductor value is similar to the parasitic capacitance value of the ESD diode. Figure 2 As shown, C6 is the parasitic capacitance of the pad (Pad_P or Pad_N), C7 and C7' are the parasitic capacitances of the ESD-protected diode, C9 and C10 are the parasitic capacitances of the DC blocking capacitor C8, and C11 is the parasitic capacitance of the CTLE input pair. L7 is a single inductor that compensates for the parasitic capacitance C6 of the pad. L8 is a single inductor that compensates for the parasitic capacitances C7 and C7' of the diode, ensuring that the impedance seen from point L2 is close to the matching impedance. L9 and L10 form a T-Coil network. L9 ensures that the impedance seen from point L9 is close to the matching impedance, and L10 helps compensate for the parasitic capacitances C9 and C10 of the DC blocking capacitor and the parasitic capacitance C11 of the CTLE input pair. K is the coupling coefficient of L9 and L10, and the mutual inductance generated by L9 and L10 helps the impedance of resistor R3 at high frequencies. The choice of inductor sizes L9 and L10 represents a trade-off between bandwidth and impedance matching. Larger inductance values ​​provide greater impedance assistance to resistor R3 at high frequencies, resulting in better return loss. Conversely, smaller inductance values ​​result in lower parasitic resistance and a greater distance from the capacitor's pole, thus aiding in bandwidth expansion. A larger inductance ratio generally yields a larger maximum bandwidth. However, since it's difficult to fabricate inductors with large size variations and high coupling coefficients (>0.7) in a chip, a ratio between 0.3 and 0.5 and a coupling coefficient between 0.3 and 0.6 are typically considered. Using a larger L10 and a smaller L9 to form an asymmetrical T-coil ensures both bandwidth and better impedance matching. Figure 3 The simulation results are based on a 224Gbps frequency. The horizontal axis represents frequency, the vertical axis of the upper half represents gain, and the vertical axis of the lower half represents return loss, all in dB. It can be seen that after the matching network, the gain at the Nyquist frequency is only 0.5dB attenuation, and the return loss within the frequency band is below -18dB.

[0047] TIA's advanced zero-pole design, such as Figure 1 As shown. The CTLE source degradation resistor (Rs) and capacitor (Cs) generate the first pair of zeros and poles (2-20GHz) for mid-to-low frequency compensation. The TIA feedback network introduces an RLC structure to form a gain peak at 56GHz for high-frequency compensation, with a total peaking amount of over 18dB.

[0048] The inductance, resistance, and capacitance distribution of the TIA feedback path are as follows: Figure 1 As shown, C1 is the parasitic capacitance of the pre-stage, and C2 is the input parasitic capacitance of the TIA input pair transistors M1 and M2. These are separated by inductor L1 to reduce single-point parasitic capacitance. L1 and L2 form a T-coil, significantly reducing the bandwidth reduction caused by the pole formed by the pre-stage parasitic capacitance C1 and the gate resistances of the input pair transistors M1 and M2. K2 is the coupling coefficient between L1 and L2. Similarly, L3 and L4 form a T-coil, isolating the output parasitic capacitance C3 of the TIA input pair transistors M1 and M2 from the load capacitance C4 of the subsequent stage, while also significantly reducing the bandwidth reduction caused by the pole formed by the load capacitance C4 and the output resistances of the input pair transistors M1 and M2. K2 is the coupling coefficient between L3 and L4. R2 and L6 form a De-Q circuit design. At low frequencies, the inductor plays a dominant role, completing peaking. At high frequencies, resistor R2 reduces the Q value of inductor L5, decreasing its inductance to ensure loop stability. Figure 4 The simulation results are based on a 224Gbps output. The horizontal axis represents frequency, and the vertical axis represents gain, both in dB. The darker color represents the AC curve of the analog front-end circuit using multi-inductor high-order zero-pole compensation, while the lighter color represents the AC curve of the analog front-end circuit using single-inductor compensation. Both improve bandwidth and high-frequency peaking.

[0049] Based on the classic Gm-TIA circuit structure, this invention optimizes the zero-pole compensation for high-frequency loss and optimizes impedance matching to reduce reflection, thus better ensuring signal integrity.

[0050] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0051] The term “coupled to” and its derivatives may be used in this document. “Coupled” can mean two or more elements in direct physical or electrical contact. However, “coupled” can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements coupled or connected between elements referred to as being coupled to each other.

[0052] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

Claims

1. An analog front-end circuit for a SerDes receiver, characterized in that, It includes an input matching network, a continuous-time linear equalizer, and a transimpedance amplifier connected in sequence, wherein: The transimpedance amplifier includes a pair of input transistors (M1, M2). The gates of the pair of input transistors (M1, M2) are connected to and connected to a T-coil composed of a first inductor (L1) and a second inductor (L2). One end of the first inductor (L1) is connected to the gate and in parallel to a second parasitic capacitor (C2) at the input of the pair of input transistors. The other end of the first inductor (L1) receives the input from the previous stage and is connected in parallel to one end of the second inductor (L2) and the first parasitic capacitor (C1) at the previous stage. The drains of the pair of input transistors (M1, M2) are connected to and connected to a third inductor (L3). The T-coil is composed of the third inductor (L2) and the fourth inductor (L4). One end of the third inductor (L3) is connected to the drain and is connected in parallel to the third capacitor (C3) of the output of the pair of input transistors. The other end of the third inductor (L3) outputs an amplified signal and is connected in parallel to one end of the fourth inductor (L4) and the fourth capacitor (C4). The other ends of the second inductor (L2) and the other ends of the fourth inductor (L4) are directly connected in series with the first resistor (R1) and the fifth inductor (L5). The two ends of the fifth inductor (L5) are connected in parallel with a De-Q circuit composed of the second resistor (R2) and the sixth inductor (L6).

2. The analog front-end circuit as described in claim 1, characterized in that, The pair of input transistors (M1, M2) includes a first transistor (M1) and a second transistor (M2), wherein the first transistor (M1) is a PMOS transistor and the second transistor (M2) is an NMOS transistor, and there is a parasitic fifth capacitor (C5) between the first transistor (M1) and the second transistor (M2).

3. The analog front-end circuit as described in claim 1, characterized in that, The input matching network includes a pair of differential input matching branches. Each input matching branch includes a seventh inductor (L7), a first electrostatic discharge (ESD) unit, an eighth inductor (L8), a second ESD unit, a ninth inductor (L9), and an eighth capacitor (C8) connected in sequence. The seventh inductor (L7) is connected to the input pad, which has a parasitic sixth capacitor (C6). The node between the ninth inductor (L9) and the eighth capacitor (C8) is connected to one end of a third resistor (R3) through a tenth inductor (L10). The first ESD unit and the second ESD unit each include a diode discharge path and a diode parasitic seventh capacitor (C7) connected in sequence. The diode discharge path includes a first diode and a second diode connected in series. The anode of the first diode is grounded, and the cathode of the first diode is connected to the anode of the second diode and one end of the seventh capacitor (C7). The cathode of the second diode is connected to the power supply, and the other end of the seventh capacitor (C7) is grounded. In this pair of differential input matching branches, the other end of the third resistor (R3) is connected to and connected to the reference voltage.

4. The analog front-end circuit as described in claim 3, characterized in that, Each input matching branch also includes a ninth capacitor (C9) and a tenth capacitor (C10) parasitized by the eighth capacitor (C8), wherein one end of the ninth capacitor (C9) is connected to one end of the eighth capacitor (C8), and the other end of the ninth capacitor (C9) is grounded; one end of the tenth capacitor (C10) is connected to the other end of the eighth capacitor (C8), and the other end of the tenth capacitor (C10) is grounded.

5. The analog front-end circuit as described in claim 3, characterized in that, The inductance value of the ninth inductor (L9) is less than the inductance value of the tenth inductor (L10).

6. The analog front-end circuit as described in claim 2, characterized in that, The output of each input matching branch is connected to the input of the continuous-time linear equalizer.

7. A SerDes receiver, characterized in that, Includes the analog front-end circuit as described in any one of claims 1 to 6.

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