Synchronization method of multi-channel high-speed digital-to-analog conversion module

Abstract

The invention discloses a synchronization method of a multi-channel high-speed digital-to-analog conversion module. The synchronization method comprises the following steps: a reference clock source generates a reference clock; the trigger controller generates a trigger signal, and the trigger signal is used for notifying each DAC board to start digital quantity transmission of a new waveform; the main control chip PLL performs frequency multiplication on a reference clock to a preset working frequency, a feedback path of the main control chip PLL is moved to the DAC board, and the routing delays of the voltage-controlled oscillator for outputting the main control chip IO are consistent and are close to each other; the DAC PLL performs frequency multiplication on the reference clock to the sampling clock frequency of the DAC, and the output phase of the DAC PLL is adjustable to ensure the time sequence margin when the DAC reads the digital quantity; the main control chip sends a plurality of to-be-converted waveform digital quantities to the DACs through an isochronous transmission path at a preset moment under the triggering of a triggering signal, and the DACs convert the digital quantities into analog waveforms, so that all the DACs finish the conversion from the digital quantities to the analog quantities at the same moment, and the high-precision synchronous conversion of the DACs is realized.

Description

Technical Field

[0001] This invention belongs to the field of digital-to-analog conversion synchronization control technology, and in particular, a synchronization method for a multi-channel high-speed digital-to-analog conversion module. Background Technology

[0002] In high-precision measurement and control systems, thousands of high-speed digital-to-analog converters (DACs) often need to operate simultaneously to achieve parallel output of multi-channel analog signals. Such systems have extremely high requirements for the synchronization of the analog waveforms output by the DACs. This synchronization must meet two core requirements: first, DAC clock synchronization, meaning the digital-to-analog conversion times of different DACs must be strictly aligned; second, control logic data transmission synchronization, meaning the main control chip must simultaneously send the digital quantities to be converted to all DACs, ensuring that the deviation of the analog waveforms output by each DAC is better than one sampling period. However, in existing technologies, if the sampling clocks of different DACs originate from different references or have inconsistent transmission path lengths, it will lead to clock phase deviations, resulting in misaligned conversion times. Furthermore, significant differences in signal transmission delays at different locations within the chip or between different chips can cause the time difference between the arrival of the digital quantities at each DAC to exceed one sampling period. These problems can lead to significant deviations in the analog waveforms output by multi-channel DACs, severely reducing the overall accuracy and reliability of the measurement and control system. Therefore, a multi-channel DAC synchronization method that can solve these problems is urgently needed. Summary of the Invention

[0003] The purpose of this invention is to provide a synchronization method for a multi-channel high-speed digital-to-analog converter module to overcome the shortcomings of the prior art. By solving the synchronization problem of multi-channel high-speed DAC measurement and control systems, it achieves high-precision synchronous conversion of DACs. It can be widely used in fields such as radar, communication, and industrial measurement and control where the synchronization of analog signals is extremely important, and has significant practical value and prospects for promotion.

[0004] One embodiment of this application provides a synchronization method for a multi-channel high-speed digital-to-analog converter module, applied to a measurement and control system containing multiple digital-to-analog converters (DACs). The measurement and control system structure includes a reference clock source, a trigger controller, and at least two DAC boards with identical structures. Each DAC board integrates a main control chip, a DAC, a main control chip PLL, and a DAC PLL. The method includes: The reference clock source generates a reference clock, which is distributed to all DAC boards through reference clock cables of equal length to ensure that the reference clock received by each DAC board is in phase. The trigger controller generates a trigger signal, which is distributed to all DAC boards through trigger signal cables of equal and adjustable length. The trigger signal is used to notify each DAC board to start sending digital signals of a new waveform. The main control chip PLL multiplies the reference clock to a preset operating frequency, and the feedback path of the main control chip PLL is moved to the DAC board. At the same time, the layout and wiring of the main control chip meet the following requirements: the two traces from the chip IO to the phase detector have the same delay and are close in position; the traces of the voltage-controlled oscillator output to the main control chip IO have the same delay and are close in position. The DAC PLL multiplies the reference clock to the sampling clock frequency of the DAC, and the output phase of the DAC PLL is adjustable to ensure the timing margin when the DAC reads digital data. When triggered by a trigger signal, the main control chip sends several digital waveforms to be converted to the DAC at a preset time through an isochronous transmission path. The DAC converts the digital signals into analog waveforms, so that all the DACs can complete the conversion from digital to analog signals at the same time.

[0005] Optionally, the reference clock source provides a clock reference for the measurement and control system to ensure that the clock frequency of each module of the measurement and control system is without deviation; wherein, the frequency of the reference clock is set to 25MHz.

[0006] Optionally, the main control chip PLL multiplies the reference clock into two clocks. The first clock is set to 125MHz for the operation of the internal logic registers of the main control chip; the second clock is set to 1GHz for the main control chip to send data to the DAC, and the 1GHz clock uses single-edge triggered data transmission.

[0007] Optionally, the feedback path of the main control chip PLL is located outside the main control chip and is routed from the DAC board.

[0008] Optionally, the main control chip integrates at least one parallel-to-serial conversion shift register, which receives 8 bits of parallel digital data from an internal logic register at a rate of 125MHz, and then converts the parallel digital data into serial digital data at a rate of 1GHz and sends it to the DAC.

[0009] Optionally, the trigger controller has a built-in trigger controller PLL, which multiplies the reference clock to the operating frequency of the trigger controller to ensure that the trigger controller outputs a stable trigger signal.

[0010] Optionally, the parameters of the DAC include: sampling rate of 1 GSPS, resolution of 8 bits, and interface data width of 8 bits; the DAC is used to receive the serial digital quantity sent by the main control chip and convert it into the corresponding analog waveform.

[0011] Optionally, the two traces from the chip IO to the phase detector include: the trace from the first main control chip IO to the phase detector on the DAC board and the trace from the fourth main control chip IO to the phase detector; wherein the phases of the first main control chip IO and the fourth main control chip IO are consistent.

[0012] Optionally, the routing from the voltage-controlled oscillator output to the third main control chip IO and to the second main control chip IO includes: routing from the voltage-controlled oscillator output to the third main control chip IO via frequency division by 8 and frequency division by 5, and routing from the voltage-controlled oscillator output to the second main control chip IO via a parallel-to-serial conversion shift register; wherein the third main control chip IO and the second main control chip IO are in phase.

[0013] Optionally, the synchronization method ensures that the analog waveform deviation of all DAC outputs is better than one sampling period, and that the digital quantities planned to be converted at the same time are all converted into analog waveforms at the same time.

[0014] Compared with existing technologies, this invention is applied to a measurement and control system containing multiple digital-to-analog converters (DACs), including a reference clock source, a trigger controller, and at least two DAC boards with identical structures. Each DAC board integrates a main control chip, a DAC, a main control chip PLL, and a DAC PLL. The reference clock source generates a reference clock, which is distributed to all DAC boards through reference clock cables of equal length to ensure that the reference clock received by each DAC board is in phase. The trigger controller generates a trigger signal, which is distributed to all DAC boards through trigger signal cables of equal and adjustable length. The trigger signal is used to notify each DAC board to start the digital transmission of a new waveform. The main control chip PLL multiplies the reference clock to a preset operating frequency, and the feedback path of the main control chip PLL is moved to the DAC board. At the same time, the layout and wiring of the main control chip meet the following requirements: the two traces from the chip I / O to the phase detector have the same delay and are close in position; the traces of the voltage-controlled oscillator output to the main control chip I / O have the same delay and are close in position; the DAC PLL multiplies the reference clock to the sampling clock frequency of the DAC, and the DAC PLL multiplies the reference clock to the sampling clock frequency of the DAC. The output phase of the PLL is adjustable to ensure timing margin when the DAC reads digital signals. When triggered by a trigger signal, the main control chip sends several digital waveforms to be converted to the DAC via an isochronous transmission path at a preset time. The DAC converts the digital signals into analog waveforms, enabling all DACs to complete the digital-to-analog conversion simultaneously. This achieves high-precision synchronous conversion of the DAC by solving the synchronization problem of multi-channel high-speed DAC measurement and control systems. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a measurement and control system structure for a digital-to-analog converter (DAC) provided in an embodiment of the present invention; Figure 2A schematic diagram of a DAC board and a main control chip clock provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the internal layout and wiring of a main control chip provided in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the relationship between clock data in an embodiment of the present invention. Detailed Implementation

[0016] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0017] This invention provides a synchronization method for a multi-channel high-speed digital-to-analog converter module. This method can be applied to electronic devices, such as microwave source arrays, specifically phased array antennas, quantum computers, etc.

[0018] See Figure 1 , Figure 1 This is a schematic diagram of a measurement and control system structure for a digital-to-analog converter (DAC) according to an embodiment of the present invention. The measurement and control system structure for the DAC includes a reference clock source, a trigger controller, and at least two DAC boards with identical structures. Each DAC board integrates a main control chip, a DAC, a main control chip PLL, and a DAC PLL. The method includes: the reference clock source generates a reference clock and distributes it to all DAC boards through reference clock cables of equal length to ensure that the reference clock received by each DAC board is in phase; the trigger controller generates a trigger signal and distributes it to all DAC boards through trigger signal cables of equal length and adjustable length, the trigger signal being used to notify each DAC board to start transmitting a digital quantity of a new waveform; the main control chip PLL multiplies the reference clock to a preset operating frequency, and the feedback path of the main control chip PLL is moved to the DAC board, while the layout and wiring of the main control chip satisfies: the two traces from the chip IO to the phase detector have the same delay and are close in position; the traces of the voltage-controlled oscillator outputting the main control chip IO have the same delay and are close in position; the DAC PLL multiplies the reference clock to the sampling clock frequency of the DAC, and the DAC... The output phase of the PLL is adjustable to ensure timing margin when the DAC reads digital signals. When triggered by a trigger signal, the main control chip sends several digital waveforms to be converted to the DAC at a preset time through an isochronous transmission path. The DAC converts the digital signals into analog waveforms, so that all the DACs can complete the conversion from digital to analog signals at the same time.

[0019] The reference clock source provides a clock reference for the measurement and control system to ensure that the clock frequency of each module in the system is without deviation; the frequency of the reference clock can be set to 25MHz. The main control chip PLL multiplies the reference clock into two clocks: the first is set to a 125MHz clock for the operation of the internal logic registers of the main control chip; the second is set to a 1GHz clock for the main control chip to send data to the DAC, and the 1GHz clock uses single-edge triggered data transmission. The feedback path of the main control chip PLL is located outside the main control chip and is routed from the DAC board. The main control chip integrates at least one parallel-to-serial conversion shift register, which receives 8 bits of parallel digital data from the internal logic register at a rate of 125MHz and then converts the parallel digital data into serial digital data at a rate of 1GHz before sending it to the DAC. The trigger controller has a built-in trigger controller PLL, which multiplies the reference clock to the operating frequency of the trigger controller to ensure stable output of the trigger signal. The DAC parameters include: a sampling rate of 1 GSPS, a resolution of 8 bits, and an interface data width of 8 bits. The DAC receives serial digital signals from the main control chip and converts them into corresponding analog waveforms. The two traces from the chip I / O to the phase detector include: a trace from the first main control chip I / O to the phase detector on the DAC board, and a trace from the fourth main control chip I / O to the phase detector; wherein the first and fourth main control chip I / Os are in phase. The traces from the voltage-controlled oscillator (VCO) output to the third and second main control chip I / Os include: a trace from the VCO output to the third main control chip I / O via frequency division by 8 and frequency division by 5, and a trace from the VCO output to the second main control chip I / O via a parallel-to-serial conversion shift register; wherein the third and second main control chip I / Os are in phase. This synchronization method ensures that the analog waveform deviation of all DAC outputs is better than one sampling period, and that digital signals planned to be converted at the same time are converted into analog waveforms at the same time.

[0020] It should be noted that the initial data in this application refers to the digital quantities of several waveforms to be transmitted, and the target signal obtained is the analog waveform corresponding to the digital quantities of the aforementioned waveforms. The desired effect is to ensure that the digital quantities being converted at the same time are synchronously converted into analog waveforms. It is important to ensure that the sampling clock phases of all digital-to-analog converters (DACs) are the same, and that the digital quantities at the same time are sent to the DACs at the same time.

[0021] The reference clock source serves as the clock reference for the entire measurement and control system, ensuring consistent frequency across all components. The main control chip sends digital signals to the DAC at the correct time. Its internal main control PLL multiplies the reference clock source to a sufficiently high frequency for the main control chip's operation. The DAC (Digital-to-Analog Converter) chip converts digital signals into analog signals. The DAC PLL multiplies the reference clock source to a sufficiently high frequency to serve as the DAC's sampling clock. The DAC board provides the backbone for the main control chip, DAC, and DAC PLL, distributing the reference clock source to these components. The trigger controller sends trigger signals to each DAC board; these signals initiate the transmission of digital signals. Its built-in trigger controller PLL multiplies the reference clock source to a sufficiently high frequency for the trigger controller's operation.

[0022] It should be noted that the reference clock source generates a reference clock and distributes it to all DAC boards. The trigger controller generates a trigger signal to all DAC boards to notify them to start sending a new round of waveforms. All DAC boards have a consistent hardware design. For ease of explanation, assume a reference clock frequency of 25MHz, a main control chip clock of 125MHz, a single-edge clock of 1GHz for the main control chip to send data to the DAC, a DAC sampling rate of 1GSPS, a resolution of 8 bits, and an interface data width of 8 bits. See [link to documentation]. Figure 2 , Figure 2 This is a schematic diagram of a DAC board and a main control chip clock provided in an embodiment of the present invention. The main control chip receives a 25MHz reference clock and uses a built-in PLL to generate 125MHz and 1GHz clocks, which are used for internal logic operation and output data to the DAC, respectively. There are several parallel-to-serial conversion shift registers. Each parallel-to-serial conversion shift register receives 8 bits of parallel data from the internal logic at a rate of 125MHz and then sends it serially to the DAC at a rate of 1GHz.

[0023] To compensate for the variation in internal delay of the main control chip with process voltage and temperature, the following measures can be taken: First, the feedback path of the main control chip's PLL should be moved outside the chip and then routed from the DAC board; second, some requirements should be added to the internal layout and routing of the main control chip, see [link to relevant documentation] Figure 3 , Figure 3 This invention provides a schematic diagram of the internal layout and wiring of a main control chip. The layout and wiring requirements are as follows: the purpose of placing the components close together is to reduce the impact of temperature, process voltage differences at different locations on the chip: 1. The input traces from the chip's I / O to the phase detector, i.e. Figure 3 The two lines from P1 to the phase detector and from P4 to the phase detector have the same delay and are close to each other; 2. The two traces that divide the output of the voltage-controlled oscillator by 8 and 5 to P3 and the trace that divide the output of the voltage-controlled oscillator by parallel-to-serial conversion shift register to P2 have the same delay and are located close to each other; 3. There is no strict requirement for the delay of the voltage-controlled oscillator output to the clock terminal of the internal logic register after being divided by 8. It can be basically the same as the delay of the voltage-controlled oscillator output to the clock terminal of the register after being divided by 8 and by 5, and the setup time and hold time must be met.

[0024] The above requirements ensure that: 1. All DAC boards send data to their connected DACs via P2 at the same time. The reason is as follows: The phases at P1 and P4 are synchronized. The delay from P3 to P4 is external to the chip, so the phases of P1 and P3 are synchronized. Furthermore, although the delays from the VCO to P3 and from the VCO to P2 are unstable, their changes are consistent, meaning the phases of P3 and P2 are synchronized. Therefore, the phases of P1 and P2 are synchronized, meaning the moment P2 sends data to the DAC coincides with the edge of P1. Since P1 on different DAC boards comes from the same reference clock source and the cable lengths are identical, all P2s send data to their connected DACs at the same time.

[0025] Another factor that guarantees the phase alignment of P2 and P3 is that P3 passes through a series of frequency dividers, while P2 does not. In other words, the edge of P3 must be the edge of the 1GHz clock, while P2 data is sent at every edge of the 1GHz clock. This guarantees that the edge of P3 must be the moment when P2 data is sent.

[0026] 2. The 125MHz clock on all DAC boards has basically aligned edges, for the following reasons: All P3 pins on the DAC boards are aligned, and the edge of P3 is not significantly different from the edge of the 125MHz clock. 125MHz is not a very high frequency, and the timing requirements are not very strict. A slight deviation can be considered as basic alignment.

[0027] It should be noted that the requirements for the trigger controller are similar to those for the main control chip, but can be relaxed somewhat because the trigger signal is emitted by a 125MHz clock, providing a relatively large timing margin. During measurement and control system integration, only the length of the trigger cable needs to be adjusted to ensure that the DAC board meets the setup and hold time requirements when receiving the trigger signal.

[0028] The output clock phase of the DAC PLL can be adjusted with fine granularity to meet the data setup and hold times. Since all DAC PLLs have the same input reference clock phase (all from the same reference clock source and with the same cable length), all DAC PLLs can also have the same output phase. That is, all DACs sample data at the same time, process it internally for a fixed period, and then output analog waveforms at the same time.

[0029] For example, the reference clock source serves as the system clock reference, generating a 25MHz reference clock, which is distributed to all DAC boards via cables of equal length to ensure no clock frequency deviation across modules. The trigger controller has a built-in trigger controller PLL, used to multiply the reference clock to its own operating frequency, generating a trigger signal to initiate a new round of waveform transmission from the DAC boards. This trigger signal is distributed to all DAC boards via adjustable-length cables, meeting the setup and hold time requirements of the trigger signal. The DAC board is the core unit for multi-channel synchronization; each DAC board has an identical structure and can integrate the following sub-modules: The main control chip is responsible for sending the digital quantity to be converted, i.e., the digital quantity of several waveforms, to the DAC at a preset time when triggered by the trigger signal. The main control chip PLL is integrated inside the main control chip. It multiplies the reference clock into two clocks: a 125MHz clock for the internal logic registers of the main control chip and a 1GHz clock for the parallel-to-serial conversion shift register to send data. Its feedback path is moved to the DAC board to compensate for the chip's I / O delay. The parallel-to-serial conversion shift register receives 8-bit parallel digital data output from the internal logic register at a rate of 125MHz, converts it into serial digital data at a rate of 1GHz, and sends it to the DAC. The DAC (Digital-to-Analog Converter) chip is configured with a sampling rate of 1 GSPS, a resolution of 8 bits, and an interface data width of 8 bits. It is responsible for converting the digital signals sent by the main control chip into analog waveforms. The DAC PLL is used to multiply the reference clock to 1GHz, which is the sampling clock of the DAC, and the output phase can be adjusted in fine granularity to ensure the timing margin when the DAC reads digital values.

[0030] Based on the above system architecture, the synchronization method specifically includes the following steps: Step 1: Clock reference unification and transmission path optimization: The reference clock source distributes the 25MHz reference clock to all DAC boards through reference clock cables of equal length, ensuring that the phase of the reference clock received by each DAC board is completely consistent; the trigger controller distributes the trigger signal to all DAC boards through adjustable trigger signal cables of equal length, adjusting the cable length so that the timing of each DAC board receiving the trigger signal meets the setup time and hold time, ensuring that all DAC boards start data transmission synchronously.

[0031] Step 2: Optimize the clock and layout routing of the main control chip. Move the feedback path of the main control chip PLL from inside the chip to the DAC board to compensate for the transmission delay of the main control chip's I / O ports. The internal layout routing of the main control chip should meet the following requirements: the two traces from chip I / O (P1, P4) to the phase detector have the same delay and are physically close; the trace from the VCO output to chip I / O (P3) via frequency divider 8 and frequency divider 5 has the same delay as the trace from the VCO output to chip I / O (P2) via parallel-to-serial conversion shift register and is physically close; the trace from the VCO output to the clock terminal of the internal logic register via frequency divider 8 has a basically the same delay as the trace from the VCO output to the clock terminal of the frequency divider 5 register via frequency divider 8 and meets the setup and hold times.

[0032] Step 3: DAC sampling clock phase adjustment. Adjust the output phase of the DAC PLL on each DAC board, ensuring that the sampling clock phase of all DACs is consistent, assuming that the reference clock cables are of equal length, so as to provide a clock basis for synchronous digital conversion.

[0033] Step 4: Data Synchronization and Conversion. After the trigger signal is activated, the main control chip's internal logic register sends an 8-bit parallel digital quantity to the parallel-to-serial conversion shift register at a rate of 125MHz; the parallel-to-serial conversion shift register converts the parallel digital quantity into a serial digital quantity at a rate of 1GHz, and sends it to the DAC through an isochronous transmission path; all DACs, triggered by a 1GHz sampling clock with consistent phase, synchronously read the digital quantity and convert it into an analog waveform, realizing the conversion of digital quantities at the same time and completing the analog waveform conversion at the same time.

[0034] See Figure 4 , Figure 4 This is a schematic diagram of the relationship between clock data provided in an embodiment of the present invention. The diagram shows the relationship between the clock data. P2 of all DAC boards is aligned, and the DAC clocks of all DAC boards are also aligned. That is, all DACs acquire new data at the same time and output analog waveforms after internal processing for a fixed period.

[0035] The synchronization method of the multi-channel high-speed digital-to-analog converter module of the present invention has the following advantages compared with the prior art: 1. High synchronization accuracy. By ensuring equal lengths of reference clock cables and trigger signal cables, and fine-grained adjustment of the DAC PLL phase, the sampling clock phase of all DACs is kept consistent, and the digital signals arrive at the DACs synchronously, with analog waveform deviations better than one sampling period. 2. Strong anti-interference capability. The external shift of the main control chip PLL feedback path and the optimization of internal layout and wiring compensate for delay fluctuations caused by changes in process, temperature, and voltage, ensuring the stability of data transmission; 3. Excellent versatility. All DAC boards use a consistent hardware design, allowing for flexible expansion of the number of DACs. Clock frequency and DAC parameters can be adjusted according to requirements, making them widely applicable. 4. High reliability. Through timing margin optimization and adjustable trigger signal length, data reading timing errors are avoided, improving the long-term reliability of the system.

[0036] In one optional implementation, the synchronization method of the present invention will be described in detail below in conjunction with specific parameters and timing relationships, so that those skilled in the art can more clearly understand the implementation process of the present invention.

[0037] 1. System parameter settings In this embodiment, the core system parameters are set as follows: Reference clock source output frequency: 25MHz; The main control chip PLL output clock is 125MHz (internal logic clock) and 1GHz (data transmission clock, single-edge triggered). DAC parameters: sampling rate 1GSPS, resolution 8bit, interface data width 8bit; Parallel-to-serial conversion shift register: Each channel receives 8 bits of parallel data at 125MHz and transmits serial data at 1GHz; Number of DAC boards: N (N≥2, to meet the requirements of the measurement and control system).

[0038] 2. Specific Implementation Examples of the Synchronization Process After the reference clock source is started, a 25MHz reference clock is generated and distributed to N DAC boards through cables of the same specification with varying lengths. The phase difference of the reference clock received by each DAC board is as follows: After the trigger controller is started, its built-in PLL multiplies the 25MHz reference clock to 125MHz, generating a trigger signal. This trigger signal is distributed to N DAC boards through cables of the same specification with adjustable lengths. Adjusting the cable length ensures that the time difference between the trigger signals received by each DAC board meets the setup and hold time requirements of the trigger signal. After receiving a 25MHz reference clock, the main control chip on each DAC board multiplies the reference clock to 125MHz and 1GHz using its built-in PLL. The 125MHz clock drives the internal logic register to work, which generates an 8-bit parallel digital quantity (digital quantity of several waveforms) to be converted according to the measurement and control requirements. The 1GHz clock drives the parallel-to-serial conversion shift register to work, and the shift register waits for a trigger signal to start data reception. The internal layout and wiring of the main control chip strictly follows the principles of consistent delay and close proximity. Specifically, the delay difference between the traces from P1 to the phase detector and from P4 to the phase detector is constrained to be less than 0.1ns, and the physical spacing is the minimum process spacing. The delay difference between the traces from the voltage-controlled oscillator to P3 and to P2 is constrained to be less than 0.1ns, and the physical spacing is the minimum process spacing. The difference in trace length between the voltage-controlled oscillator to the internal logic register and to the 5 divider register meets the timing requirements.

[0039] When the DAC board receives the trigger signal, its internal logic register immediately sends an 8-bit parallel digital value to the parallel-to-serial conversion shift register at a rate of 125MHz. After receiving the parallel data, the parallel-to-serial conversion shift register converts it into serial data at a rate of 1GHz and sends it to the DAC's input interface through an impedance-matched transmission line. The DAC PLL on each DAC board multiplies the 25MHz reference clock to 1GHz and, through fine-grained phase adjustment, aligns the rising edge of the DAC sampling clock with the center of the stable window of the serial data, ensuring timing margin. Under the unified trigger of the 1GHz sampling clock, all DACs synchronously read the serial digital value, and after internal fixed-period processing, convert the digital value into an analog waveform, realizing that the analog waveforms output by N DACs are generated at the same time, and the waveform deviation is better than one sampling period.

[0040] It should be noted that the synchronization method of the above-mentioned multi-channel high-speed digital-to-analog converter module can also be applied to quantum chip measurement and control systems to perform quantum measurement and control operations.

[0041] In this application, all reference clock cables and trigger signal cables are of equal length. The main control chip PLL feedback path is compensated, meaning the feedback path is moved outside the chip to compensate for chip I / O delays. The timing measures for key internal traces of the main control chip are the same as the clock layout and routing requirements for the main control chip. Furthermore, the length of each trigger cable is adjustable, and the DAC PLL output phase can be adjusted with fine granularity to ensure sufficient timing margin when the DAC reads digital data. These layout and routing requirements compensate for delays in multiple locations, which is a crucial guarantee that all data arrives at the DAC simultaneously and is an important component of this application.

[0042] Compared with existing technologies, this invention is applied to a measurement and control system containing multiple digital-to-analog converters (DACs), including a reference clock source, a trigger controller, and at least two DAC boards with identical structures. Each DAC board integrates a main control chip, a DAC, a main control chip PLL, and a DAC PLL. The reference clock source generates a reference clock, which is distributed to all DAC boards through reference clock cables of equal length to ensure that the reference clock received by each DAC board is in phase. The trigger controller generates a trigger signal, which is distributed to all DAC boards through trigger signal cables of equal and adjustable length. The trigger signal is used to notify each DAC board to start the digital transmission of a new waveform. The main control chip PLL multiplies the reference clock to a preset operating frequency, and the feedback path of the main control chip PLL is moved to the DAC board. At the same time, the layout and wiring of the main control chip meet the following requirements: the two traces from the chip I / O to the phase detector have the same delay and are close in position; the traces of the voltage-controlled oscillator output to the main control chip I / O have the same delay and are close in position; the DAC PLL multiplies the reference clock to the sampling clock frequency of the DAC, and the DAC PLL multiplies the reference clock to the sampling clock frequency of the DAC. The output phase of the PLL is adjustable to ensure timing margin when the DAC reads digital signals. When triggered by a trigger signal, the main control chip sends several digital waveforms to be converted to the DAC via an isochronous transmission path at a preset time. The DAC converts the digital signals into analog waveforms, enabling all DACs to complete the digital-to-analog conversion simultaneously. This achieves high-precision synchronous conversion of the DAC by solving the synchronization problem of multi-channel high-speed DAC measurement and control systems.

[0043] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0044] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0045] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0046] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0047] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0048] If the aforementioned integrated units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0049] The embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A synchronization method for a multi-channel high-speed digital-to-analog converter module, characterized in that, A measurement and control system comprising multiple digital-to-analog converters (DACs) is provided. The system structure includes a reference clock source, a trigger controller, and at least two identical DAC boards. Each DAC board integrates a main control chip, a DAC, a main control chip PLL, and a DAC PLL. The method includes: The reference clock source generates a reference clock, which is distributed to all DAC boards through reference clock cables of equal length to ensure that the reference clock received by each DAC board is in phase. The trigger controller generates a trigger signal, which is distributed to all DAC boards through trigger signal cables of equal and adjustable length. The trigger signal is used to notify each DAC board to start sending digital signals of a new waveform. The main control chip PLL multiplies the reference clock to a preset operating frequency, and the feedback path of the main control chip PLL is moved to the DAC board. At the same time, the layout and wiring of the main control chip meet the following requirements: the two traces from the chip IO to the phase detector have the same delay and are close in position; the traces of the voltage-controlled oscillator output to the main control chip IO have the same delay and are close in position. The DAC PLL multiplies the reference clock to the sampling clock frequency of the DAC, and the output phase of the DAC PLL is adjustable to ensure the timing margin when the DAC reads digital data. When triggered by a trigger signal, the main control chip sends several digital waveforms to be converted to the DAC at a preset time through an isochronous transmission path. The DAC converts the digital signals into analog waveforms, so that all the DACs can complete the conversion from digital to analog signals at the same time.

2. The synchronization method according to claim 1, characterized in that, The reference clock source provides a clock reference for the measurement and control system to ensure that the clock frequency of each module of the measurement and control system is without deviation; wherein, the frequency of the reference clock is set to 25MHz.

3. The synchronization method according to claim 1, characterized in that, The main control chip PLL multiplies the reference clock into two clocks. The first clock is set to 125MHz for the operation of the internal logic registers of the main control chip. The second clock is set to 1GHz for the main control chip to send data to the DAC. The 1GHz clock uses single-edge triggered data transmission.

4. The synchronization method according to claim 3, characterized in that, The feedback path of the main control chip PLL is located outside the main control chip and is routed from the DAC board.

5. The synchronization method according to claim 4, characterized in that, The main control chip integrates at least one parallel-to-serial conversion shift register. The parallel-to-serial conversion shift register receives 8 bits of parallel digital data from an internal logic register at a rate of 125MHz, and then converts the parallel digital data into serial digital data at a rate of 1GHz and sends it to the DAC.

6. The synchronization method according to claim 1, characterized in that, The trigger controller has a built-in trigger controller PLL, which multiplies the reference clock to the operating frequency of the trigger controller to ensure that the trigger controller outputs a stable trigger signal.

7. The synchronization method according to claim 1, characterized in that, The parameters of the DAC include: sampling rate of 1 GSPS, resolution of 8 bits, and interface data width of 8 bits; the DAC is used to receive the serial digital quantity sent by the main control chip and convert it into the corresponding analog waveform.

8. The synchronization method according to claim 1, characterized in that, The two traces from the chip I / O to the phase detector include: the trace from the first main control chip I / O to the phase detector on the DAC board and the trace from the fourth main control chip I / O to the phase detector; wherein, the phases of the first main control chip I / O and the fourth main control chip I / O are consistent.

9. The synchronization method according to claim 1, characterized in that, The routing from the voltage-controlled oscillator output to the third main control chip IO and to the second main control chip IO includes: a routing from the voltage-controlled oscillator output to the third main control chip IO via frequency division by 8 and frequency division by 5, and a routing from the voltage-controlled oscillator output to the second main control chip IO via a parallel-to-serial conversion shift register; wherein the third main control chip IO and the second main control chip IO are in phase.

10. The synchronization method according to any one of claims 1-9, characterized in that, The synchronization method ensures that the analog waveform deviation of all DAC outputs is better than one sampling period, and that the digital quantities planned to be converted at the same time are all converted into analog waveforms at the same time.

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