Adaptive equalization circuit and method based on approximate calculation

Abstract

The invention provides a self-adaptive equalization circuit and method based on approximate calculation, and relates to the technical field of approximate circuits. The method comprises the following steps: constructing a three-level technical architecture: designing an approximate positive / negative compressor with a directional error characteristic, and enabling output to respectively generate positive and negative bias errors based on probability optimization logic; a compressor is integrated in a Wallace tree array to form an 8bit * 8bit layered approximate multiplier, a low weight bit is cut off, an approximate compressor is used for a middle bit, a high weight bit is fully accurately configured, and a mixed adder is combined for summation; the approximate equalizer adopts a 15-tap FFE architecture, taps are divided into a front tap, a main tap and a rear tap according to signal energy on the basis of an LMS algorithm, the main tap adopts a low-error approximate negative multiplier, and the front tap and the rear tap adopt an approximate positive / negative multiplier which are arranged in a crossed manner to realize error complementation. According to the design, hardware is simplified, through system-level error self-counteracting, the area, the power consumption and the delay are reduced, meanwhile, the balance performance is guaranteed, and a scheme is provided for breaking through a bottleneck for a high-speed optical interface.

Description

Technical Field

[0001] This invention relates to the field of approximation circuit technology, and in particular to an adaptive equalization circuit and method based on approximation calculation. Background Technology

[0002] With the rapid development of cloud computing, big data, and 5G communication technologies, data traffic in optical networks is growing exponentially, placing higher demands on the transmission rate of short-range optical interfaces. Pulse Amplitude Modulation 4 (PAM4) technology, capable of doubling the transmission bandwidth at the same symbol rate, has become the mainstream modulation scheme for next-generation short-range optical communication. However, compared to traditional Non-Return-to-Zero (NRZ) modulation, PAM4 signals, when transmitted through a channel, have an eye diagram containing three decision thresholds and four signal levels, with narrower eye diagram boundaries, significantly increasing sensitivity to inter-symbol interference (ISI). This makes high-performance adaptive equalization technology a core requirement for reliable transmission in PAM4 systems.

[0003] Among numerous schemes for suppressing ISI, feedforward equalizers (FFEs) based on the least mean square (LMS) algorithm are widely used in high-speed optical communication systems due to their simple structure and stable convergence. LMS-FFE compensates for the leading and trailing edge distortion of the input signal by dynamically adjusting the tap coefficients. Its core operations include the multiplication and accumulation of the tap coefficients and the input signal, as well as coefficient updates based on the error signal. However, with the increase in transmission rate, the hardware overhead of LMS-FFE has become a key bottleneck restricting system performance. To address the hardware overhead problem of LMS-FFE equalization circuits, existing research has attempted to introduce approximate calculation techniques to simplify the core computational units. Xie Wenzhuo et al. proposed an LMS adaptive filter design based on approximate multipliers and system-level compensation strategies in "A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing." However, the current design does not further explore the hardware efficiency improvement space by combining the multi-tap parallel structure characteristics of the FFE equalizer, making it difficult to adapt to the design requirements of optical modules for "extreme miniaturization" of the equalizer. Summary of the Invention

[0004] Purpose of the invention: To address the hardware resource constraints faced by adaptive equalizers in high-speed optical communication scenarios, this invention proposes an adaptive equalization circuit and method based on approximate calculation, which optimizes performance and saves hardware resources through system-level error compensation.

[0005] To achieve the aforementioned technical objectives, a first aspect of the present invention discloses an adaptive equalization circuit based on approximate calculation. This equalizer includes an input signal interface, an approximate directional compressor structure, an approximate directional multiplier structure, a K-tap approximate feedforward equalizer structure, and a specific hardware connection architecture. The input signal interface receives an 8-bit PAM4 modulated signal and is connected to the K-tap approximate feedforward equalizer structure. The approximate directional compressor structure includes two types: a positive approximate compressor and a negative approximate compressor, both employing a 4-input 2-output architecture. Orientation error generation is achieved through specific gate-level circuit connections. The approximate directional multiplier structure is based on a Wallace tree architecture, integrating the approximate directional compressor structure to form an 8-bit × 8-bit approximate positive multiplier and an approximate negative multiplier. The K-tap approximate feedforward equalizer structure includes a delay line unit, an approximate FIR filter module, and an approximate tap coefficient update module. Signal processing and adaptive coefficient updates under approximate calculation are achieved through specific hardware connection relationships. The specific hardware connection architecture includes the physical connection relationships and data flow paths between the components, ensuring that orientation errors are cooperatively canceled at the system level.

[0006] In a further embodiment of the first aspect, the input signal interface is used to receive an 8-bit PAM4 modulated signal and transmit it to a delay line unit; the delay line unit consists of K-1 cascaded 8-bit registers, which are connected in sequence to form a signal delay chain for storing historical data of the input signal; each tap output of the delay line unit is connected to the first input terminal of the approximate multiplier module corresponding to the K-tap approximate feedforward equalizer, providing the multiplicand signal (A0-A7) for the multiplication operation.

[0007] In a further embodiment of the first aspect, the forward approximation compressor includes four data input terminals, a local sum output terminal and a local carry output terminal. Its logic circuit consists of only two AND gates, wherein the first AND gate is connected to the input terminals X1 and X2, the second AND gate is connected to the output and input terminal X4 of the first AND gate, the output result is Sum, and the carry result Carry is always 1.

[0008] In a further embodiment of the first aspect, the negative approximation compressor includes four data input terminals, a local sum output terminal and a local carry output terminal. Its logic circuit consists of two AND gates and two OR gates, wherein the first AND gate is connected to input terminals X1 and X2, the second AND gate is connected to input terminals X3 and X4, the first OR gate is connected to input terminals X1 and X3 to obtain the output result Sum; the second OR gate is connected to the outputs of the first AND gate and the second AND gate, and the output result is Carry.

[0009] In a further embodiment of the first aspect, the approximate multiplier module includes two types: a positive approximate multiplier and a negative approximate multiplier, both of which adopt a Wallace tree structure. This structure includes three main hardware components: a partial product generation array, a hierarchical partial product compression array, and a final summation unit.

[0010] In a further embodiment of the first aspect, the partial product generation array is composed of a logic circuit consisting of 64 AND gates, with its 16 input terminals connected to an 8-bit multiplicand signal line and an 8-bit multiplier signal line, respectively, generating 16 columns of partial product signals (P0-P15). The partial product compression layer adopts a layered processing structure, and the bit weight is distinguished through physical layout: the low-weight bit processing unit directly truncates the partial product of bits 1-6 and grounds its output; the intermediate-weight bit processing unit adopts a 4-input 2-output approximation compressor array, wherein the positive approximation multiplier uses a positive approximation compressor, and the negative approximation multiplier uses a negative approximation compressor, and the two compressors adopt different gate-level circuit layouts; the high-weight bit processing unit adopts a precise 4-2 compressor, a full adder, and a half adder; the summation layer adopts a hybrid structure of carry-preserving adder and row-carry adder, which is used to finally sum the compressed partial products.

[0011] In a further embodiment of the first aspect, the K-tap approximate feedforward equalizer structure includes an approximate FIR filter module and an approximate tap coefficient update module, the two modules implementing signal processing functions through a specific hardware interconnect architecture; The approximate FIR filtering module adopts a shift register-based hardware pipeline structure, comprising K parallel-operating approximate multiplier units and a multi-bit adder tree. The first input of each approximate multiplier unit is directly connected to the corresponding tap output of the delay line unit via an 8-bit data bus, and the second input is connected to the output of the corresponding coefficient register in the approximate tap coefficient update module, receiving real-time data for approximate filtering. The multi-bit adder tree adopts a Wallace tree structure, consisting of multiple levels of full adders and half adders. Its inputs are respectively connected to the 16-bit product outputs of the K approximate multiplier units, and the parallel accumulation of partial products is achieved through a specific wiring network, finally outputting a 16-bit filtered result. The approximate tap coefficient update module adopts an error feedback architecture, comprising an error calculation unit and a coefficient update unit. The error calculation unit consists of an accurate subtractor, whose two inputs are connected to the desired signal interface and the output interface of the approximate FIR filter module, respectively. The coefficient update unit contains K parallel coefficient update channels, each containing a step multiplier, an approximate multiplier, an accumulator, and a coefficient register. The step multiplier is an accurate multiplier, with its first input connected to the output of the error calculation unit and its second input connected to the configuration register of the step factor μ. The first input of the approximate multiplier is connected to the error signal output by the error calculation unit, and its second input is connected to the corresponding tap output of the delay line unit via an 8-bit data bus. The input of the accumulator is connected to the 16-bit product output of the approximate multiplier, and its output is fed back to its own input to achieve the accumulation function. The coefficient register is connected to the second input of the corresponding approximate multiplier unit in the approximate FIR filter module via an 8-bit coefficient bus, forming a closed-loop control structure.

[0012] In a further embodiment of the first aspect, the tap arrangement of the K-tap approximate feedforward equalizer adopts a specific hardware connection method, wherein in the first M taps, the approximate multipliers in the approximate FIR filtering module and the approximate tap coefficient update module adopt a physical layout of alternating positive and negative directions; in the middle N taps, all adopt negative approximate multipliers; in the last P taps, adopt a physical layout of alternating negative and positive directions; the approximate multipliers of each tap adopt a symmetrical configuration in the approximate FIR filtering module and the approximate tap coefficient update module, and the same type of approximate multipliers in the two modules adopt the same layout and routing scheme.

[0013] A second aspect of the present invention discloses an adaptive equalization method based on approximate calculation, which is implemented using the adaptive equalization circuit based on approximate calculation disclosed in the first aspect, and includes the following steps: Step A: Detect the error characteristics of the approximate positive multiplier and the approximate negative multiplier. Based on the error probability distribution and output results analysis, the approximate positive multiplier has a higher probability of positive output error, while the approximate negative multiplier has a lower probability of negative output error. Step B: Design a tap configuration scheme to compensate for orientation errors based on the error characteristics of the approximate multiplier. Configure more approximate negative multipliers in the equalizer system to compensate for the larger errors of the approximate positive multipliers. Divide the equalizer taps into three parts: the first M front taps adopt an alternating layout of approximate positive and approximate negative multipliers; the middle N taps all adopt negative approximate multipliers; and the last P rear taps adopt an alternating layout of negative and positive multipliers. Step C: The approximate FIR filtering module filters the input signal x(n) under the error-compensated approximate multiplier tap configuration scheme to obtain the output signal y(n):

[0014] in, Let K be the coefficient of the k-th tap. The total number of taps K = M + N + P, where M is the number of preceding taps, N is the number of major taps, and P is the number of following taps. This represents the input signal after k delays; the approximate FIR filter module is actually divided into three approximate filter modules, which compensate for the error of the final accumulation result through an approximate tap configuration scheme; Step D: The approximate tap coefficient update module uses the LMS algorithm to achieve approximate coefficient updates by configuring an approximate multiplier; it obtains the ideal reference signal d(n) and calculates the error signal. Then, based on the error signal e(n) and the input signal x(n), the tap weight coefficients for the next time step are obtained through approximate multiplication using the LMS algorithm. :

[0015] Where μ is the step size factor; the taps of the approximate tap coefficient update module correspond one-to-one with the taps of the approximate FIR filter module, and the tap configuration adopts the same approximate multiplier error compensation scheme. Step E: Repeat steps C to D, and through continuous cyclical approximate filtering and approximate tap coefficient updates, achieve adaptive equalization adjustment of the input signal under approximate calculation.

[0016] In a further embodiment of the second aspect, in step A, the approximate positive multiplier is an 8-bit × 8-bit multiplier, whose partial product generation is achieved through an 8 × 8 AND gate array. During partial product compression, the low-weight bits from the 1st to the 6th bit are directly truncated, the intermediate weight bits of the 7th and 8th bits are processed using an approximate positive compressor, and the high-weight bits from the 9th to the 16th bits are processed using a precise 4-2 compressor, a full adder, and a half adder. The summation stage uses a hybrid structure of a carry-preserving adder and a row-carry adder. The approximate negative multiplier is an 8-bit × 8-bit multiplier, whose partial product generation and summation stages are the same as those of the approximate positive multiplier. During partial product compression, the intermediate weight bits of the 7th and 8th bits are processed using an approximate negative compressor.

[0017] In a further embodiment of the second aspect, the approximate positive compressor has a 4-input 2-output structure, where the probability of a positive output error is much greater than the probability of a negative error; the approximate negative compressor also has a 4-input 2-output structure, where the probability of a negative output error is greater than the probability of a positive error. The approximate positive multiplier has a higher probability of positive output error, while the approximate negative multiplier has a lower probability of negative output error. In a further embodiment of the second aspect, in step B, an approximate multiplier tap configuration scheme is designed, configuring more approximate negative multipliers to compensate for the larger error of the approximate positive multipliers; the first M taps use an alternating arrangement of approximate positive multipliers and approximate negative multipliers, the middle N main taps all use approximate negative multipliers, and the last P taps use an alternating arrangement of approximate positive multipliers and approximate negative multipliers.

[0018] To address the hardware resource constraints of adaptive equalizers (LMS-FFE) in high-speed optical communication, this invention proposes a solution. It replaces traditional high-precision multipliers with two approximate multipliers (positive bias and negative bias) with fixed error directions, thereby reducing the hardware overhead of the compensation circuit. In the specific implementation, the multipliers in the 15 taps are mixed and configured in a specific ratio, utilizing the systematic superposition of positive and negative errors to achieve overall error cancellation. Compared with existing technologies, this invention has the following advantages: (1) This invention innovatively reconstructs the compressor and multiplier architecture, designs a positive / negative error bias compressor based on the probability distribution characteristics of partial product, and performs hierarchical approximation in the 8×8 bit multiplier according to the weight of the partial product, which can effectively simplify the compressor and multiplier structure and generate the expected error bias, saving hardware resources.

[0019] (2) This invention creatively proposes a three-segment tap arrangement strategy to achieve system-level error self-cancellation. Through the inherent error compensation of complementary bias cancellation, the output deviation is eliminated without increasing additional overhead, thus solving the problem of balancing accuracy and efficiency of approximate calculation in the field of adaptive equilibrium. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the adaptive equalization circuit architecture based on approximate calculation in the embodiment.

[0021] Figure 2 This is a Karnaugh map for an approximate forward compressor.

[0022] Figure 3 This is a schematic diagram of the logic gate circuit for an approximate forward compressor.

[0023] Figure 4 Karnaugh map for an approximate negative compressor.

[0024] Figure 5 This is a schematic diagram of the logic gate circuit for an approximate negative compressor.

[0025] Figure 6 This is a schematic diagram of an array structure for an approximate multiplier.

[0026] Figure 7 This is a schematic diagram of the basic architecture of the LMS-FFE system. Detailed Implementation

[0027] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0028] Example 1 This embodiment discloses an adaptive equalization circuit based on approximate calculation. Through three innovative strategies—directional error control, hierarchical approximation optimization, and complementary error compensation—it significantly reduces hardware complexity while ensuring the stability of the system's equalization performance. The adaptive equalization circuit comprises a three-level technical architecture: an approximate positive compressor and an approximate negative compressor with directional error characteristics; these compressors are dynamically integrated into a Wallace tree partial product compression array to form an 8-bit × 8-bit approximate positive multiplier and an approximate negative multiplier; the approximate equalizer uses an FFE architecture for filtering, selects the LMS algorithm for weight updates, and introduces error-biased approximate multipliers into the approximate FIR filtering module and the approximate tap coefficient update module, implementing an error-compensating tap arrangement strategy.

[0029] The approximate compressor is the fundamental module for controlling the direction of error. Its design breaks through the limitation of unbiased error in traditional compressors, and achieves error orientation through probability-driven logic optimization. The truth table optimization of the forward compressor aims to maximize the probability of positive error: by calculating the error distance of different input combinations, the probability of the output error being positive is much greater than the probability of the error being negative, thereby generating a stable positive bias error. The approximate negative compressor adopts the same compressor error bias approach, making the probability of the output error distance being negative greater than the probability of being positive, thus generating a negative bias error. The approximate forward multiplier consists of three stages: partial product generation, partial product compression, and summation. Its innovation lies in the hierarchical approximation and key bit precision preservation strategies. The partial product is generated by an AND gate array; partial product compression employs a truncated approximation method, directly truncating low-weight bits, replacing the precise 4-2 compressor with an approximate forward compressor for intermediate bits, and processing high-weight bits using a precise 4-2 compressor, a full adder, and a half adder; the summation stage uses a hybrid structure, combining a carry-preserving adder and a row-carry adder to achieve precise summation. The approximate negative multiplier uses the same approximation method, replacing the exact 4-2 compressor with an approximate negative compressor for the middle two bits in the partial product compression part; The equalizer is the top-level design of the system architecture, employing a K-tap approximate feedforward equalizer structure. An adaptive adjustment mechanism based on the least mean square algorithm is designed for the 8-bit PAM4 input signal, and an innovative error-complementary tap arrangement strategy is proposed. The equalizer mainly consists of an approximate tap coefficient update module and an approximate FIR filtering module. The input signal is x(n), the output signal is y(n), the tap coefficients are w(n), and the system filter output can be expressed as: The approximate tap coefficient update module uses the LMS algorithm. The ideal reference signal is d(n), and the mathematical expression for the error signal e(n) is: By using the LMS algorithm to update the weights, the tap weight coefficients for the next time step can be obtained. .

[0030] To maximize the efficiency of approximate calculations, this invention introduces approximate multipliers into the equalizer, classifying and differentiating the K taps by function: the taps are divided into pre-tap, main tap, and post-tap, with the main tap, corresponding to the signal at the current moment, having the largest impact on the equalization effect and being key to error control; the pre-tap and post-tap are mainly used to compensate for the leading and trailing edge distortion of the signal, with relatively smaller impact on performance. Based on this classification, the replacement of the approximate multipliers for the taps follows the principle of error complementarity: the approximate FIR filtering module and the approximate tap coefficient update module of the main tap all use approximate negative multipliers, utilizing their smaller error probability to ensure the accuracy of the core path; the pre-tap and post-tap use a 1:1 cross arrangement of positive and negative multipliers, reducing the accumulation of local errors by canceling out the positive and negative errors of adjacent taps. This configuration achieves accuracy compensation without additional calibration circuitry through global error complementarity, ultimately ensuring system convergence stability and equalization effect while reducing hardware overhead.

[0031] To optimize the above technical solution, the specific measures also include: The approximate compressor consists of an approximate positive compressor and an approximate negative compressor. The compressor has four input data points and two output data points: the sum and carry. Compared to a traditional precise 4-2 compressor, it discards the carry from the previous stage (Cin) and the carry from the next stage (Cout). The core principle of this design is the probabilistic characteristics of the input partial product. Based on the probability distribution of the input signals, the compressor adjusts the output logic by optimizing the truth table. This makes the error of the output data in the approximate positive compressor biased towards the positive direction, and the error of the output data in the approximate negative compressor biased towards the negative direction. Furthermore, a simplified logic function is obtained by combining this with Karnaugh maps.

[0032] The multiplier is an 8-bit × 8-bit multiplier, generating a 16-column partial product array. The bits 1 through 6 are low-weight bits, truncated for partial product processing, arranged from low to high weight. Bits 7 and 8 are intermediate-weight bits, where the precise 4-2 compressor is replaced with the proposed approximate compressor. Specifically, the intermediate-weight bits of the approximate positive multiplier are replaced with the approximate positive compressor, and the intermediate-weight bits of the approximate negative multiplier are replaced with the approximate negative compressor. Bits 9 through 16 are high-weight bits, using precise devices for partial product compression. The summation stage is completed using a hybrid structure of carry-saving adders and row-carry adders, ensuring both accumulation speed and avoiding error accumulation during the summation process.

[0033] The approximate equalizer system adopts an FFE equalizer architecture and uses the LMS algorithm for tap coefficient updates. Based on the output probabilities of the approximate positive and negative compressors and the error distance of the output results of the corresponding multipliers, an error-compensated arrangement strategy for approximate taps is used. In the front taps, the multipliers in the FIR filtering and approximate tap coefficient update modules are replaced with an alternating arrangement of approximate positive and approximate negative multipliers. In the main taps, approximate negative multipliers with lower error probabilities are used. In the back taps, an alternating arrangement of approximate positive and approximate negative multipliers is also used, thus forming an approximate LMS-FFE system.

[0034] Example 2 The following uses an optical communication system approximating LMS-FFE as an example, with the system input signal being an 8-bit PAM4 signal. The technical solution of the present invention will be further described in detail with reference to the accompanying drawings: Table 1 shows the probability distribution of the partial products of the compressor inputs. The approximate compressor is a 4-input, 2-output structure. The input signals are partial products of a multiplier array, each generated by an AND gate. The probability of a product being 0 is 3 / 4, and the probability of a product being 1 is 1 / 4. Therefore, probabilities are calculated for the four inputs x1, x2, x3, and x4 of the compressor, and the 16 different input scenarios are grouped according to their probabilities, resulting in 5 different input groups. The output results in the compressor's truth table are then modified according to these different input probabilities.

[0035] Table 1: Probability distribution of compressor input partial product

[0036] Table 2 is the truth table for the approximate forward compressor. Based on the input probability and error distance, the probability that the error is positive can be calculated as follows: The probability that the error is negative is: This makes the output result more likely to be positive. Figure 2 It is a Karnaugh map of an approximate forward compressor, and the sum of the logic functions is... Carry-over , Figure 3 It is a logic gate circuit structure that approximates a forward compressor, consisting of only two AND gates, which efficiently saves hardware resources.

[0037] Table 2: Truth Table for Approximate Forward Compressor

[0038] Table 3 is the truth table for the approximate negative compressor. Following the same design approach, the probability of the error being negative is: The probability that the error is positive is: This makes the output more likely to be negative. Figure 4 It is a Karnaugh map of an approximate negative compressor, and the sum of the logic functions is... Carry-over . Figure 5 It is a logic gate circuit structure that approximates a negative compressor, consisting of two AND gates and two OR gates.

[0039] Table 3: Truth Table for Approximate Negative Compressors

[0040] Figure 6 This diagram illustrates the structure of an 8-bit × 8-bit approximate multiplier. The multiplier employs a hybrid architecture combining hierarchical approximation and precise key-bit calculation. The multiplier array consists of three parts: partial product generation, partial product compression, and partial product summation. Partial product generation is implemented using an 8×8 AND gate array, consistent with traditional structures. Partial product compression employs a hierarchical processing strategy: the lowest 6 bits are directly truncated, as this part has a relatively small impact on the system's signal-to-noise ratio, and truncating it directly saves on the number of compressors; the middle 2 bits are processed in parallel using the aforementioned approximation compressor, with the positive multiplier configured with a positive compressor and the negative multiplier configured with a negative compressor to obtain an error-biased multiplier; the highest 8 bits are processed using precise 4-2 compressors, full adders, and half adders to ensure the accuracy of signal amplitude calculation, which is crucial for system performance. In the partial product summation stage, a hybrid structure is used, combining a carry-saving adder (CSA) to achieve parallel accumulation of intermediate results, and finally, a row carry adder (RCA) completes the precise summation, balancing computational speed and accuracy.

[0041] Figure 7 The basic architecture of the LMS-FFE system is as follows: the input signal x(n) is filtered to obtain the output signal y(n), where the tap weights are updated using the LMS algorithm, and d(n) is the desired signal. Specifically, the process involves first calculating the error between the output signal and the desired signal. Then, based on the error and the input signal, the tap coefficients for the next time step are updated, i.e. (where μ is the step size factor), through continuous cyclic filtering This enables adaptive equalization and adjustment of the signal.

[0042] The adaptive equalization circuit based on approximation calculation designed in this invention uses a 15-tap system and proposes an innovative approximation multiplier configuration scheme. Figure 1 It is an adaptive equalization circuit architecture based on approximate calculation.

[0043] In this scheme, the approximate FIR filter module filters the input signal x(n) under the error-compensated approximate multiplier tap configuration to obtain the output signal y(n):

[0044] in, Let K be the coefficient of the k-th tap. The total number of taps K = M + N + P, where M is the number of preceding taps, N is the number of major taps, and P is the number of following taps. This represents the input signal after k delays.

[0045] For a 15-tap FFE architecture, the taps are divided into three parts: the first 6 taps are the pre-tap taps, the middle 3 taps are the main taps, and the last 6 taps are the post-tap taps. To optimize system performance, approximate multipliers are used to replace the exact multipliers in the FIR module and the approximate tap coefficient update module, utilizing the complementary positive and negative error characteristics of the two approximate multipliers. Since the total error probability of the approximate negative multiplier is... The total error probability of an approximate positive multiplier Since the negative error is smaller, more negative multipliers are needed to compensate for the positive error generated by the positive multipliers. Specifically, the configuration is as follows: in the first six taps, the approximate positive and negative multipliers are arranged in a 1:1 alternating ratio (3 positive, 3 negative) to cancel out local biases through alternating errors; the middle three main taps all use approximate negative multipliers, as the main taps contribute the most to the signal gain, and arranging more negative multipliers can effectively compensate for larger positive biases; the last six taps also use a 1:1 alternating arrangement (3 positive, 3 negative) to balance the overall error distribution. The entire LMS-FFE system achieves an approximate positive-to-negative multiplier ratio of 6:9. Error compensation is achieved through this complementary bias cancellation mechanism without the need for additional calibration circuitry, reducing hardware overhead while ensuring system performance.

[0046] As described in the above embodiments, to address the hardware resource constraints faced by adaptive equalizers in high-speed optical communication scenarios, this invention proposes a low-complexity LMS-FFE architecture employing approximate multipliers with different error directions, achieving performance optimization through system-level error compensation. Approximate positive and negative compressors with error biases are designed to construct corresponding error-biased approximate multipliers, reducing hardware complexity by eliminating compensation circuitry. At the system level, by strategically configuring the multiplier type in the 15-tap FFE, error cancellation can be achieved through coordinated positive / negative bias superposition. This collaborative approach allows LMS-FFE to achieve hardware resource savings within acceptable error tolerance by sacrificing some accuracy, providing a feasible path for overcoming hardware bottlenecks in next-generation high-speed optical interfaces.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An adaptive equalization circuit based on approximate calculation, characterized in that, include: Input signal interface, approximate directional compressor structure, approximate directional multiplier structure, K-tap approximate feedforward equalizer structure, and predetermined hardware connection architecture. The input signal interface is used to receive an 8-bit PAM4 modulated signal and is connected to the K-tap approximate feedforward equalizer structure. The approximate directional compressor structure includes a positive approximate compressor and a negative approximate compressor, both of which adopt a 4-input 2-output architecture and are connected through predetermined gate-level circuits to realize the directional error generation function. The approximate oriented multiplier structure is based on the Wallace tree architecture and integrates the approximate oriented compressor structure to form an 8-bit × 8-bit approximate positive multiplier and an approximate negative multiplier. The K-tap approximate feedforward equalizer structure includes a delay line unit, an approximate FIR filter module, and an approximate tap coefficient update module, which realizes signal processing and adaptive coefficient update through predetermined hardware connection relationships. The predetermined hardware connectivity architecture includes the physical connection relationships between the components and the data flow path, ensuring that orientation errors are collaboratively offset at the system level.

2. The adaptive equalization circuit based on approximate calculation according to claim 1, characterized in that, The input signal interface is used to receive an 8-bit PAM4 modulated signal and transmit it to the delay line unit; the delay line unit consists of K-1 cascaded 8-bit registers, which are connected in sequence to form a signal delay chain for storing historical data of the input signal; each tap output of the delay line unit is connected to the first input terminal of the approximate multiplier module corresponding to the K-tap approximate feedforward equalizer, providing multiplicand signals A0-A7 for the multiplication operation; The approximate multiplier module includes two types: positive approximate multipliers and negative approximate multipliers. Both adopt a Wallace tree structure and contain a partial product generation array, a hierarchical partial product compression array, and a final summation unit.

3. The adaptive equalization circuit based on approximate calculation according to claim 1, characterized in that, The forward approximation compressor includes four data input terminals, a local sum output terminal, and a local carry output terminal. Its logic circuit consists of only two AND gates, where the first AND gate is connected to the input terminals X1 and X2, and the second AND gate is connected to the output and input terminal X4 of the first AND gate. The output result is Sum, and the carry result Carry is always 1.

4. The adaptive equalization circuit based on approximate calculation according to claim 1, characterized in that, The negative approximation compressor includes four data input terminals, a local sum output terminal, and a local carry output terminal. Its logic circuit consists of two AND gates and two OR gates. The first AND gate is connected to input terminals X1 and X2, the second AND gate is connected to input terminals X3 and X4, and the first OR gate is connected to input terminals X1 and X3 to obtain the output result Sum. The second OR gate is connected to the outputs of the first AND gate and the second AND gate, and the output result is Carry.

5. The adaptive equalization circuit based on approximate calculation according to claim 2, characterized in that, The partial product generation array consists of 64 AND gates, with its 16 inputs connected to 8-bit multiplicand and 8-bit multiplier signal lines, generating 16 columns of partial product signals P0-P15. The partial product compression layer adopts a layered processing structure, with bit weight differentiation achieved through physical layout: low-weight bit processing units directly truncate the partial product of bits 1-6 and ground their outputs; intermediate-weight bit processing units use a 4-input, 2-output approximation compressor array, where the positive approximation multiplier uses a positive approximation compressor and the negative approximation multiplier uses a negative approximation compressor, with different gate-level circuit layouts for the two types of compressors; high-weight bit processing units use precise 4-2 compressors, full adders, and half adders; the summation layer adopts a hybrid structure of carry-preserving adders and row-carry adders, used to finally sum the compressed partial products.

6. The adaptive equalization circuit based on approximate calculation according to claim 1, characterized in that, The approximate FIR filtering module adopts a shift register-based hardware pipeline structure, comprising K parallel-operating approximate multiplier units and a multi-bit adder tree. The first input of each approximate multiplier unit is directly connected to the corresponding tap output of the delay line unit via an 8-bit data bus, and the second input is connected to the output of the corresponding coefficient register in the approximate tap coefficient update module to receive real-time data for filtering. The multi-bit adder tree adopts a Wallace tree structure, consisting of multiple levels of full adders and half adders. Its inputs are respectively connected to the 16-bit product outputs of the K approximate multiplier units, and the parallel accumulation of partial products is achieved through a wiring network, finally outputting a 16-bit filtered result.

7. The adaptive equalization circuit based on approximate calculation according to claim 6, characterized in that, The approximate tap coefficient update module adopts an error feedback architecture, comprising an error calculation unit and a coefficient update unit. The error calculation unit consists of an accurate subtractor, whose two inputs are connected to the desired signal interface and the output interface of the approximate FIR filter module, respectively. The coefficient update unit contains K parallel coefficient update channels, each containing a step multiplier, an approximate multiplier, an accumulator, and a coefficient register. The step multiplier is an accurate multiplier, with its first input connected to the output of the error calculation unit and its second input connected to the configuration register of the step factor μ. The first input of the approximate multiplier is connected to the error signal output by the error calculation unit, and its second input is connected to the corresponding tap output of the delay line unit via an 8-bit data bus. The input of the accumulator is connected to the 16-bit product output of the approximate multiplier, and its output is fed back to its own input to achieve the accumulation function. The coefficient register is connected to the second input of the corresponding approximate multiplier unit in the approximate FIR filter module via an 8-bit coefficient bus, forming a closed-loop control structure.

8. The adaptive equalization circuit based on approximate calculation according to claim 1, characterized in that, The tap arrangement of the K-tap approximate feedforward equalizer adopts the following hardware connection method: In the first M taps, the approximate multipliers in the approximate FIR filtering module and the approximate tap coefficient update module adopt a physical layout of alternating positive and negative directions; All of the N taps in the middle use negative approximation multipliers; In the last P taps, a physical layout method of alternating negative and positive directions is adopted; the approximate multipliers of each tap are symmetrically configured in the approximate FIR filtering module and the approximate tap coefficient update module, and the same type of approximate multipliers in the two modules adopt the same layout and routing scheme.

9. An adaptive equilibrium method based on approximate calculation, characterized in that, The adaptive equalization circuit based on approximate calculation as described in any one of claims 1 to 8 includes the following steps: Step A: Detect the error characteristics of the approximate positive multiplier and the approximate negative multiplier. The method is as follows: the approximate positive multiplier has a higher probability of positive output error, and the approximate negative multiplier has a lower probability of negative output error. Step B: Design a tap configuration scheme to compensate for orientation error based on the error characteristics: Divide the equalizer taps into three parts. The first M front taps adopt an alternating layout of approximately positive multipliers and approximately negative multipliers; the middle N taps all adopt negative approximate multipliers; and the last P rear taps adopt an alternating layout of negative and positive multipliers. Step C: The approximate FIR filtering module filters the input signal x(n) under the error-compensated approximate multiplier tap configuration scheme to obtain the output signal y(n): in, Let K be the coefficient of the k-th tap. The total number of taps K = M + N + P, where M is the number of preceding taps, N is the number of major taps, and P is the number of following taps. This represents the input signal after k delays; Step D: The approximate tap coefficient update module uses the LMS algorithm to achieve approximate updates of the tap coefficients by configuring an approximate multiplier; it obtains the ideal reference signal d(n) and calculates the error signal. Then, based on the error signal e(n) and the input signal x(n), the tap weight coefficients for the next time step are obtained through approximate multiplication using the LMS algorithm. : Where μ is the step size factor; the taps of the approximate tap coefficient update module correspond one-to-one with the taps of the approximate FIR filter module, and the tap configuration adopts the same approximate multiplier error compensation scheme. Step E: Repeat steps C to D, and through continuous cyclic filtering and approximate tap coefficient updates, achieve adaptive equalization adjustment of the input signal under approximate calculation.

10. The adaptive equilibrium method based on approximate calculation according to claim 9, characterized in that, In step A, the approximate positive multiplier is an 8-bit × 8-bit multiplier. Its partial product generation is achieved through an 8 × 8 AND gate array. During partial product compression, the low-weight bits from the 1st to the 6th bit are directly truncated, the intermediate weight bits of the 7th and 8th bits use an approximate positive compressor, and the high-weight bits from the 9th to the 16th bits use a precise 4-2 compressor, a full adder, and a half adder. The summation stage uses a hybrid structure of carry-preserving adder and row-carry adder. The approximate negative multiplier is also an 8-bit × 8-bit multiplier. Its partial product generation and summation stages are the same as those of the approximate positive multiplier. During partial product compression, the intermediate weight bits of the 7th and 8th bits use an approximate negative compressor. The approximate forward compressor has a 4-input 2-output structure, and the probability that the output error is positive is greater than the probability that the error is negative. The approximate negative compressor has a 4-input, 2-output structure, and the probability of the output error being negative is greater than the probability of the error being positive.

Images