High-throughput signal processing and switching device

Abstract

The invention discloses a signal processing and switching device with high throughput, which belongs to the field of signal processing and comprises a PSOC (programmable system on chip) chip FMQL45T900, an FPGA (field programmable gate array) chip SMQ7VX690TFFG1157, a photoelectric conversion chip HTG8515A, a digital signal processor FT-M6678N, an SRIO (serial rapid input / output) interaction chip NRS1800 and an Ethernet switching chip SM5396. The integration level of the signal processing system can be improved, the throughput capacity of the signal processing device is improved, and therefore the overall capacity of the system is improved.

Description

Technical Field

[0001] This invention relates to the field of signal processing, and more specifically, to a high-throughput signal processing and switching device. Background Technology

[0002] In traditional design schemes, due to the increasing system integration, a signal processing system typically contains multiple signal processing devices, and the number of signal processing devices largely determines the overall processing capability of the signal processing system. However, the collaborative operation between signal processing devices involves a large amount of information exchange. Traditional systems employ multiple high-speed data exchange devices, but these face significant challenges in terms of cost, power consumption, and exchange efficiency. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-throughput signal processing and switching device that can improve the integration of the signal processing system, enhance the throughput of the signal processing device, and thus improve the overall system capability.

[0004] The objective of this invention is achieved through the following solution: A high-throughput signal processing and switching device, comprising: PSOC chip FMQL45T900, FPGA chip SMQ7VX690TFFG1157, photoelectric conversion chip HTG8515A, digital signal processor FT-M6678N, SRIO interactive chip NRS1800, Ethernet switching chip SM5396; The on-board management function is implemented using the PSOC chip FMQL45T900. It is connected to the Ethernet switching chip SM5396 through the SGMII interface and to the digital signal processor FT-M6678N and FPGA chip SMQ7VX690TFFG1157 through the SPI interface. The digital signal processor FT-M6678N is connected to the FPGA chip SMQ7VX690TFFG1157; the digital signal processor FT-M6678N has external DDR chips and FLASH chips, and is connected to the Ethernet switching chip SM5396, the SRIO interaction chip NRS1800 and the PSOC chip FMQL45T900 respectively. The FPGA chip SMQ7VX690TFFG1157 is connected to the SRIO interaction chip NRS1800 and the photoelectric conversion chip HTG8515A respectively; The SRIO interactive chip NRS1800 is connected to the photoelectric conversion chip HTG8515A, and then connected to the backplane via optical fiber.

[0005] Furthermore, the PSOC chip FMQL45T900 is equipped with a temperature acquisition port and a voltage acquisition port, which are used to acquire temperature and voltage information within the board, respectively.

[0006] Furthermore, the PSOC chip FMQL45T900 includes 6 SPI interfaces, which are connected to 4 digital signal processors FT-M6678N and 2 FPGA chips SMQ7VX690TFFG1157 respectively.

[0007] Furthermore, the PSOC chip FMQL45T900 is equipped with two CAN interfaces, which are used to connect to the backplane as a maintenance channel and a discrete signal transmission channel.

[0008] Furthermore, the first digital signal processor FT-M6678N, the second digital signal processor FT-M6678N, and the first FPGA chip SMQ7VX690TFFG1157 are designed as mirror images of the third digital signal processor FT-M6678N, the fourth digital signal processor FT-M6678N, and the second FPGA chip SMQ7VX690TFFG1157.

[0009] Furthermore, the digital signal processor FT-M6678N is equipped with DDR chips and FLASH chips, and is connected to the Ethernet switching chip SM5396, the SRIO interaction chip NRS1800, and the PSOC chip FMQL45T900, respectively. Specifically, the digital signal processor FT-M6678N is equipped with four DDR3 chips and one BPI interface FLASH chip, which are connected to the Ethernet switching chip SM5396 through one SGMII and the SRIO interaction chip NRS1800 through two 4X SRIOs, respectively, and to the PSOC chip FMQL45T900 through one SPI interface.

[0010] Furthermore, the first digital signal processor FT-M6678N and the third digital signal processor FT-M6678N are respectively connected to one EMIF to the first FPGA chip SMQ7VX690TFFG1157 and the second FPGA chip SMQ7VX690TFFG1157.

[0011] Furthermore, the first FPGA chip SMQ7VX690TFFG1157 has two 4X SRIO connections on the board to the first SRIO interaction chip NRS1800, and one 4X SRIO connection to the photoelectric conversion chip HTG8515A; the second FPGA chip SMQ7VX690TFFG1157 has one 4X SRIO connection on the board to the second SRIO interaction chip NRS1800, and one 4X SRIO connection to the photoelectric conversion chip HTG8515A.

[0012] Furthermore, there is one 4X SRIO interface and 20 LVDS interfaces between the first FPGA chip SMQ7VX690TFFG1157 and the second FPGA chip SMQ7VX690TFFG1157.

[0013] Furthermore, the digital signal processor FT-M6678N has no direct interface to the backplane. The first FPGA chip SMQ7VX690TFFG1157 is connected to the backplane via one 4X SRIO interface and several LVDS and LVCMOS interfaces; the second FPGA chip SMQ7VX690TFFG1157 is connected to the backplane via two 4X SRIO interfaces and several LVDS and LVCMOS interfaces.

[0014] Furthermore, the SRIO interaction chip NRS1800 is connected to the photoelectric conversion chip HTG8515A, specifically including: the SRIO interaction chip NRS1800 is connected to the photoelectric conversion chip HTG8515A through 2 channels of 4X SRIO.

[0015] Furthermore, the second SRIO interaction chip NRS1800 has a 4X SRIO electrical interface on the backplane.

[0016] Furthermore, it also includes a PHY chip SM88E1111. The Ethernet switching chip SM5396 is also provided with one electrical Ethernet interface directly connected to the backplane, and one Ethernet interface is converted to a COPPER through the PHY chip SM88E1111 and then to the panel debugging port.

[0017] Furthermore, it also includes panel debugging ports, including JTAG and UART ports.

[0018] The beneficial effects of this invention include: The device of this invention proposes a new architecture, namely PSOC+DSP+FPGA+switching architecture. Based on this, the relevant connection relationships and working logic are improved, the signal processing device and the network switching device are integrated, the integration degree of the signal processing device is improved, the overall power consumption of the signal processing system is reduced, the system is easier to maintain, and high-reliability, high-throughput signal processing and switching are achieved. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of the device according to an embodiment of the present invention. Detailed Implementation

[0021] All features disclosed in all embodiments of this specification, or steps in all methods or processes implied in the disclosure, may be combined and / or extended or replaced in any way, except for mutually exclusive features and / or steps.

[0022] The specific implementation process of this invention is as follows: like Figure 1 As shown, this invention specifically provides a high-throughput signal processing and switching device that can achieve highly reliable signal processing and switching. It mainly employs one Fudan Microelectronics PSOC chip FMQL45T900, two Guowei Microelectronics FPGA chips SMQ7VX690TFFG1157, one AVIC Optoelectronics photoelectric conversion chip HTG8515A, four National University of Defense Technology digital signal processors FT-M6678N, two Tianjin Information Center SRIO interaction chips NRS1800, one Shenzhen Guowei Microelectronics Ethernet switching chip SM5396, one Shenzhen Guowei Microelectronics PHY chip SM88E1111, and interface connectors.

[0023] More specifically, the management unit mainly implements on-board management functions, which are specifically implemented by the PSOC chip. The PSOC chip's on-board connections are as follows: 1) It outputs one SGMII interface to the Ethernet switching chip; 2) It collects on-board temperature and voltage information; 3) It connects to DSP1~4 and FPGA1~2 respectively via six SPI interfaces. The PSOC chip's off-board connections are as follows: 1) It has two CAN interfaces (main and backup) connected to the backplane as maintenance channels; 2) Several discrete signals are transmitted to the backplane to transmit system clock and slot ID information.

[0024] In the device of this invention, four signal processing channels are provided. Each of the four signal processing channels contains four DSPs and two FPGAs; DSP1~2+FPGA1 and DSP3~4+FPGA2 are mirrored designs. Each DSP chip is externally connected to four DDR3 chips and one BPI interface FLASH, respectively connected to one SGMII to SM5396 and two 4X SRIOs to NRS1800, and then to one SPI interface to the management unit PSOC. DSP1 and DSP3 are each connected to one EMIF to FPGA1 and FPGA2, respectively. FPGA1 has two 4X SRIOs connected to the SRIOSW1 chip and one 4X SRIO to the photoelectric conversion chip HTG8515A. FPGA2 has one 4X SRIO to the SRIOSW2 chip and one 4X SRIO to the photoelectric conversion chip HTG8515A. Simultaneously, there is one 4X SRIO interface and 20 LVDS interfaces between FPGA1 and FPGA2. The DSP has no direct interface to the backplane. FPGA1 is connected to the backplane via one 4X SRIO interface and several LVDS and LVCMOS interfaces; FPGA2 is connected to the backplane via two 4X SRIO interfaces and several LVDS and LVCMOS interfaces.

[0025] In the device of this invention, the switching section includes an SRIO switching chip, an ETH switching chip, and a photoelectric conversion chip HTG8515A, with the following connection relationships: In addition to the above connection relationships, the two SRIO switching chips are each connected to two 4X SRIOs to the photoelectric conversion chip HTG8515A, and then connected to the backplane via optical fiber. SRIO SW2 also has one 4X SRIO electrical interface to the backplane; In addition to the above connection relationships, the ETH switching chip also has one electrical Ethernet interface directly connected to the backplane; One Ethernet interface is converted to a COPPER via PHY and then connected to the panel debugging port 1.

[0026] In the device of this invention, the debugging section includes the debugging JTAG port and debugging UART port through the panel debugging port, mainly including the JTAG and UART ports of 4 DSPs, the management and control chip PSOC, and the JTAG ports of 2 FPGAs.

[0027] In the device of this invention, the high-speed SRIO mainly transmits signal processing service data, while the relatively low-speed SGMII, LVDS and LVCMOS interfaces mainly transmit inter-module control and management data.

[0028] In the device of this invention, the sharing of internal signal processing resources is achieved specifically through two 4X SRIO interfaces between the DSP and FPGA of the four internal signal processing channels, each with an interaction throughput of 40Gbps.

[0029] In the device of this invention, the high-throughput functionality is achieved through external interaction via an optical port, with optical communication switching capacity reaching 120Gbps and electrical communication switching capacity reaching 80Gbps. The overall module's external SRIO switching capacity reaches 200Gbps.

[0030] In summary, the device of the present invention integrates a signal processing device and a network switching device, improves the integration of the signal processing device, reduces the overall power consumption of the signal processing system, facilitates system maintenance, and achieves highly reliable and high-throughput signal processing and switching.

[0031] It should be noted that, within the scope of protection defined in the claims of this invention, the following embodiments can be combined and / or extended or replaced in any logical manner from the above specific embodiments, such as the disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0032] Example 1 A high-throughput signal processing and switching device, characterized in that it comprises: PSOC chip FMQL45T900, FPGA chip SMQ7VX690TFFG1157, photoelectric conversion chip HTG8515A, digital signal processor FT-M6678N, SRIO interactive chip NRS1800, Ethernet switching chip SM5396; The on-board management function is implemented using the PSOC chip FMQL45T900. It is connected to the Ethernet switching chip SM5396 through the SGMII interface and to the digital signal processor FT-M6678N and FPGA chip SMQ7VX690TFFG1157 through the SPI interface. The digital signal processor FT-M6678N is connected to the FPGA chip SMQ7VX690TFFG1157; the digital signal processor FT-M6678N has external DDR chips and FLASH chips, and is connected to the Ethernet switching chip SM5396, the SRIO interaction chip NRS1800 and the PSOC chip FMQL45T900 respectively. The FPGA chip SMQ7VX690TFFG1157 is connected to the SRIO interaction chip NRS1800 and the photoelectric conversion chip HTG8515A respectively; The SRIO interactive chip NRS1800 is connected to the photoelectric conversion chip HTG8515A, and then connected to the backplane via optical fiber.

[0033] Example 2 Based on Example 1, the PSOC chip FMQL45T900 is equipped with a temperature acquisition port and a voltage acquisition port, which are used to acquire temperature and voltage information within the board, respectively.

[0034] Example 3 Based on Example 1, the PSOC chip FMQL45T900 includes 6 SPI interfaces, which are connected to 4 digital signal processors FT-M6678N and 2 FPGA chips SMQ7VX690TFFG1157 respectively.

[0035] Example 4 Based on Example 1, the PSOC chip FMQL45T900 is equipped with two CAN interfaces for connecting to the backplane as a maintenance channel and a discrete signal transmission channel.

[0036] Example 5 Based on Example 3, the first digital signal processor FT-M6678N, the second digital signal processor FT-M6678N, and the first FPGA chip SMQ7VX690TFFG1157 are designed as mirror images of the third digital signal processor FT-M6678N, the fourth digital signal processor FT-M6678N, and the second FPGA chip SMQ7VX690TFFG1157.

[0037] Example 6 Based on Embodiment 1, the digital signal processor FT-M6678N is equipped with external DDR chips and FLASH chips, and is respectively connected to Ethernet switching chip SM5396, SRIO interaction chip NRS1800 and PSOC chip FMQL45T900. Specifically, the digital signal processor FT-M6678N is equipped with four DDR3 chips and one BPI interface FLASH chip, which are respectively connected to one SGMII to Ethernet switching chip SM5396 and two 4X SRIO to SRIO interaction chip NRS1800, and one SPI interface to PSOC chip FMQL45T900.

[0038] Example 7 Based on Example 5, the first digital signal processor FT-M6678N and the third digital signal processor FT-M6678N are respectively connected to one EMIF to the first FPGA chip SMQ7VX690TFFG1157 and the second FPGA chip SMQ7VX690TFFG1157.

[0039] Example 8 Based on Example 7, the first FPGA chip SMQ7VX690TFFG1157 has two 4X SRIO connections on the board to the first SRIO interaction chip NRS1800, and one 4X SRIO connection to the photoelectric conversion chip HTG8515A; the second FPGA chip SMQ7VX690TFFG1157 has one 4X SRIO connection on the board to the second SRIO interaction chip NRS1800, and one 4X SRIO connection to the photoelectric conversion chip HTG8515A.

[0040] Example 9 Based on Example 7, there is one 4X SRIO interface and 20 LVDS interfaces between the first FPGA chip SMQ7VX690TFFG1157 and the second FPGA chip SMQ7VX690TFFG1157.

[0041] Example 10 Based on Embodiment 7, the digital signal processor FT-M6678N has no direct interface to the backplane. The first FPGA chip SMQ7VX690TFFG1157 is connected to the backplane via one 4X SRIO interface and several LVDS and LVCMOS interfaces; the second FPGA chip SMQ7VX690TFFG1157 is connected to the backplane via two 4X SRIO interfaces and several LVDS and LVCMOS interfaces.

[0042] Example 11 Based on Example 1, the SRIO interaction chip NRS1800 is connected to the photoelectric conversion chip HTG8515A, specifically including: the SRIO interaction chip NRS1800 is connected to the photoelectric conversion chip HTG8515A through 2 channels of 4X SRIO.

[0043] Example 12 Based on embodiment 8, the second SRIO interaction chip NRS1800 is provided with a 4X SRIO electrical interface on the backplane.

[0044] Example 13 Based on Embodiment 1, it also includes a PHY chip SM88E1111. The Ethernet switching chip SM5396 is further provided with one electrical Ethernet interface directly connected to the backplane, and one Ethernet interface is converted to a COPPER through the PHY chip SM88E1111 and then to the panel debugging port 1.

[0045] Example 14 Based on Embodiment 1, a panel debugging port is also included, which includes a JTAG port and a UART port.

[0046] The units described in the embodiments of the present invention can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0047] According to one aspect of the present invention, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and executes the computer instructions, causing the computer device to perform the methods provided in the various optional implementations described above.

[0048] In another aspect, embodiments of the present invention also provide a computer-readable medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device. The computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the methods described in the above embodiments.

Claims

1. A high-throughput signal processing and switching device, characterized in that, include: PSOC chip FMQL45T900, FPGA chip SMQ7VX690TFFG1157, photoelectric conversion chip HTG8515A, digital signal processor FT-M6678N, SRIO interactive chip NRS1800, Ethernet switching chip SM5396; The on-board management function is implemented using the PSOC chip FMQL45T900. It is connected to the Ethernet switching chip SM5396 through the SGMII interface and to the digital signal processor FT-M6678N and FPGA chip SMQ7VX690TFFG1157 through the SPI interface. The digital signal processor FT-M6678N is connected to the FPGA chip SMQ7VX690TFFG1157; the digital signal processor FT-M6678N has external DDR chips and FLASH chips, and is connected to the Ethernet switching chip SM5396, the SRIO interaction chip NRS1800 and the PSOC chip FMQL45T900 respectively. The FPGA chip SMQ7VX690TFFG1157 is connected to the SRIO interactive chip NRS1800 and the photoelectric conversion chip HTG8515A respectively, and there are discrete signal transmission channels to the backplane. The SRIO interactive chip NRS1800 is connected to the photoelectric conversion chip HTG8515A, and then connected to the backplane via optical fiber.

2. The high-throughput signal processing and switching apparatus according to claim 1, characterized in that, The PSOC chip FMQL45T900 is equipped with a temperature acquisition port and a voltage acquisition port, which are used to acquire temperature and voltage information within the board, respectively.

3. The high-throughput signal processing and switching apparatus according to claim 1, characterized in that, The PSOC chip FMQL45T900 includes 6 SPI interfaces, which are connected to 4 FT-M6678N digital signal processors and 2 SMQ7VX690TFFG1157 FPGA chips respectively.

4. The high-throughput signal processing and switching apparatus according to claim 1, characterized in that, The PSOC chip FMQL45T900 is equipped with two CAN interfaces, which are used to connect to the backplane as a maintenance channel and a discrete signal transmission channel.

5. The high-throughput signal processing and switching apparatus according to claim 3, characterized in that, The first digital signal processor FT-M6678N, the second digital signal processor FT-M6678N, and the first FPGA chip SMQ7VX690TFFG1157 are designed as mirror images of the third digital signal processor FT-M6678N, the fourth digital signal processor FT-M6678N, and the second FPGA chip SMQ7VX690TFFG1157.

6. The high-throughput signal processing and switching apparatus according to claim 1, characterized in that, The digital signal processor FT-M6678N is equipped with DDR chips and FLASH chips, and is connected to the Ethernet switching chip SM5396, the SRIO interaction chip NRS1800, and the PSOC chip FMQL45T900, respectively. Specifically, the digital signal processor FT-M6678N is equipped with four DDR3 chips and one BPI interface FLASH chip, which are connected to the Ethernet switching chip SM5396 through one SGMII and the SRIO interaction chip NRS1800 through two 4XSRIOs, and then connected to the PSOC chip FMQL45T900 through one SPI interface.

7. The high-throughput signal processing and switching apparatus according to claim 5, characterized in that, The first digital signal processor FT-M6678N and the third digital signal processor FT-M6678N are each connected to one EMIF channel to the first FPGA chip SMQ7VX690TFFG1157 and the second FPGA chip SMQ7VX690TFFG1157, respectively.

8. The high-throughput signal processing and switching apparatus according to claim 7, characterized in that, The first FPGA chip, SMQ7VX690TFFG1157, has two 4X SRIO connections on the board to the first SRIO interaction chip, NRS1800, and one 4X SRIO connection to the photoelectric conversion chip, HTG8515A. The second FPGA chip, SMQ7VX690TFFG1157, has one 4X SRIO connection on the board to the second SRIO interaction chip, NRS1800, and one 4X SRIO connection to the photoelectric conversion chip, HTG8515A.

9. The high-throughput signal processing and switching apparatus according to claim 7, characterized in that, There is one 4X SRIO interface and 20 LVDS interfaces between the first FPGA chip SMQ7VX690TFFG1157 and the second FPGA chip SMQ7VX690TFFG1157.

10. The high-throughput signal processing and switching apparatus according to claim 7, characterized in that, The digital signal processor FT-M6678N has no direct interface to the backplane. The first FPGA chip SMQ7VX690TFFG1157 is connected to the backplane via one 4X SRIO interface and several LVDS and LVCMOS interfaces. The second FPGA chip SMQ7VX690TFFG1157 is connected to the backplane via two 4X SRIO interfaces and several LVDS and LVCMOS interfaces.

11. The high-throughput signal processing and switching apparatus according to claim 1, characterized in that, The SRIO interaction chip NRS1800 is connected to the photoelectric conversion chip HTG8515A, specifically including: the SRIO interaction chip NRS1800 is connected to the photoelectric conversion chip HTG8515A through 2 channels of 4XSRIO.

12. The high-throughput signal processing and switching apparatus according to claim 8, characterized in that, The second SRIO interaction chip NRS1800 has a 4X SRIO electrical interface on the backplane.

13. The high-throughput signal processing and switching apparatus according to claim 1, characterized in that, It also includes the PHY chip SM88E1111. The Ethernet switching chip SM5396 is also equipped with one electrical Ethernet interface that is directly connected to the backplane, and one Ethernet interface that is converted to a COPPER through the PHY chip SM88E1111 and then to the panel debugging port.

14. The high-throughput signal processing and switching apparatus according to claim 1, characterized in that, It also includes panel debugging ports, including JTAG and UART ports.

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