Non-volatile memory cell with single polysilicon floating gate and contact control gate

Abstract

The invention relates to a non-volatile memory cell with a single polysilicon floating gate and a contact control gate. A cost effective technical solution for implementing a non-volatile memory cell based on a floating gate transistor including a floating gate covering an active region and a field region of a semiconductor substrate: a single polysilicon floating gate NVM bit cell. The control gate terminal is implemented with a contact plug (contact control gate) or metal field plate separated by a floating gate using a SIPROT stack (oxide and nitride) often present in the CMOS process.

Description

Technical Field

[0001] This disclosure relates to non-volatile memory, and more specifically, to a single polysilicon floating-gate electrically erasable programmable read-only memory (EEPROM). Background Technology

[0002] In smart power technology, a common approach to integrating low-cost memory is a single polysilicon floating-gate EEPROM. In one possible solution, the floating gate can be integrated with the same polysilicon used in CMOS and power MOS transistors. Tunnel oxide can also be used in the same way for CMOS and power MOS transistors. The control gate can be a well / diffusion within the substrate.

[0003] However, such a technical solution may have several drawbacks. For example, it may require applying a relatively high voltage between the control gate well and the body region of the sensing transistor for erase and / or programming operations. This, in turn, may require utilizing a significant area to maintain the voltage drop within the semiconductor to prevent junction breakdown. This can affect the overall bit cell size. Furthermore, another potentially high contribution to area consumption is the use of silicon protection masks in CMOS technology. This process step can isolate the floating gate from a boundaryless nitride layer, which can cause charge loss from the floating gate, thus affecting retention characteristics. Using such a mask layer increases the bit cell size because a dedicated distance is allocated from the floating gate to the drain / source contacts.

[0004] One possible solution to these problems is to use hot electron and hot hole injection to reduce the programming and / or erasing voltages. One possible solution could involve constructing non-volatile memory bit cells with special processing steps to reduce the bit cell area. However, using hot electrons with hot hole injection can increase power consumption because only a small fraction of the current is effectively injected into the floating gate. Even with lower voltages, some space is still wasted to maintain the voltage drop. Using hole injection also reduces the number of cycles before overprogramming windows narrow (e.g., charge trapping). Specialized methods are more expensive due to the introduction of additional masking and processing steps.

[0005] All topics discussed in the background section are not necessarily prior art and should not be assumed to be prior art simply because they are discussed in the background section. Following this line of thought, any awareness of problems in the prior art discussed in the background section or related to such topics should not be considered prior art unless explicitly stated otherwise. Instead, the discussion of any topic in the background section should be considered as part of the inventor's method for solving a particular problem, which in itself can be inventive. Summary of the Invention

[0006] Embodiments of this disclosure provide non-volatile memory cells that overcome at least some of the above-described disadvantages, and corresponding methods for manufacturing such non-volatile memory cells. Embodiments of this disclosure provide a non-volatile memory cell including a floating gate transistor and a select transistor. Embodiments of this disclosure advantageously utilize a silicide protective dielectric layer as the control gate of the floating gate transistor and the capacitive coupling dielectric of the floating gate. Embodiments of this disclosure utilize a control gate contact that at least partially covers a field dielectric region outside the active region of the substrate.

[0007] In one embodiment, the non-volatile memory cell utilizes different first and second control gate contacts covering a polysilicon floating gate. The first control gate contact is at least partially disposed on a first lateral side of the active region. The second control gate contact is at least partially disposed on a second lateral side of the active region opposite to the first lateral side. In one embodiment, the first and second control gate contacts do not overlap with the active region, or in other words, they are staggered relative to the active region.

[0008] In one embodiment, the non-volatile memory cell utilizes a field plate metal as a control gate contact. The field plate metal is disposed on a silicide protective dielectric layer and at least partially overlaps with a field oxide region outside the active region.

[0009] In one embodiment, a memory device includes a semiconductor substrate comprising an active region and a field region. The memory device includes a floating gate, a control gate above the floating gate, and a dielectric layer interposed between the control gate and the floating gate. The control gate is at least partially made of a metallic material.

[0010] In one embodiment, a memory device includes a semiconductor substrate comprising an active region and a field region. The memory device includes a floating gate, a control gate above the floating gate, and a dielectric layer interposed between the control gate and the floating gate. The control gate includes a plurality of discrete elements.

[0011] In one embodiment, a memory device includes a semiconductor substrate comprising an active region and a field region. The memory device includes a floating gate covering the active and field regions, a control gate disposed above the floating gate, and a dielectric layer interposed between the control gate and the floating gate. The control gate covers the field region but does not overlap with the active region.

[0012] In one embodiment, a method includes a floating gate forming an active region and a field region of a floating gate transistor covering a semiconductor substrate for a memory cell, and a gate terminal forming an active region and a field region of a select transistor covering a semiconductor substrate for a memory cell. The floating gate and the gate terminal have the same material. The method includes forming a dielectric layer over the floating gate and the gate terminal, and forming a window in the dielectric layer to expose the gate terminal. The method also includes forming a control gate of the floating gate transistor on the dielectric layer over the floating gate, and forming a gate contact in the opening to contact the gate terminal.

[0013] In one embodiment, a method includes reading data from a non-volatile memory cell including a floating gate transistor comprising a floating gate covering an active region and a field region of a semiconductor substrate. Reading data includes applying a read body voltage to the field region and applying a read control gate voltage to a control gate disposed on a dielectric layer. The dielectric layer is disposed on the floating gate, and the control gate covers the field region. The method includes sensing a current in response to the read control gate voltage. Attached Figure Description

[0014] Figure 1A This is a perspective view of an integrated circuit including non-volatile memory cells according to one embodiment.

[0015] Figure 1B This is a circuit diagram of a non-volatile memory cell according to one embodiment.

[0016] Figure 2 This is a cross-sectional perspective view of an integrated circuit including non-volatile memory cells according to one embodiment.

[0017] Figure 3 This is a cross-sectional perspective view of an integrated circuit including non-volatile memory cells according to one embodiment.

[0018] Figure 4 This is a perspective view of an integrated circuit including non-volatile memory cells according to one embodiment.

[0019] Figure 5 This is a cross-sectional view of an integrated circuit including non-volatile memory cells according to one embodiment.

[0020] Figure 6 This is a top view layout of a portion of a non-volatile memory cell according to one embodiment.

[0021] Figure 7A This is a top view layout of a non-volatile memory array according to one embodiment.

[0022] Figure 7B According to one embodiment Figure 7A An enlarged view of the layout of the memory cells in the memory array, including an overlay circuit diagram of the memory cells.

[0023] Figure 7C This is a top view layout of a non-volatile memory array including word lines, bit lines, and select lines according to one embodiment.

[0024] Figure 8 This is a top view layout of a non-volatile memory array according to one embodiment.

[0025] Figure 9 This is a cross-sectional view of a non-volatile memory cell according to one embodiment.

[0026] Figure 10 This is a flowchart of a method for manufacturing a non-volatile memory array according to one embodiment. Detailed Implementation

[0027] Figure 1A This is a perspective view of an integrated circuit 100 including a non-volatile memory cell 102 according to one embodiment. The non-volatile memory cell 102 is a floating-gate memory cell including a floating-gate transistor T1 and a CMOS select transistor T2. As will be described in more detail below, the non-volatile memory cell includes a control gate including a plurality of control gate contacts coupled to the floating-gate capacitance of the floating-gate transistor T1. The plurality of control gate contacts are formed at least partially outside the active region of the floating-gate transistor T1. The integrated circuit 100 may be referred to as a memory device.

[0028] In further description Figure 1A Before the integrated circuit 100, it is beneficial to describe the circuit layout of the non-volatile memory cell 102. Figure 1B According to one embodiment Figure 1A Circuit diagram of non-volatile memory cell 102.

[0029] refer to Figure 1B The non-volatile memory cell 102 includes a floating gate transistor T1, a select transistor T2, and a capacitor C. The first terminal of capacitor C is the control gate CG of memory cell 102. The second terminal of capacitor C is the floating gate 112 of floating gate transistor T1. The drain terminal of floating gate transistor T1 is coupled to bit line BL. The source terminal of floating gate transistor T1 is coupled to the drain terminal of select transistor T2. The gate terminal of select transistor T2 receives the select signal SEL. The source terminal of transistor T2 is coupled to source line SL. The body terminals of transistors T1 and T2 receive body voltage B. Bit line BL can be referred to as drain bit line BLD. Source line SL can also be referred to as source bit line BLS.

[0030] Typically, nonvolatile memory cell 102 can be programmed, erased, and read by applying a selected voltage to the control gate CG, bit line BL, gate terminal of transistor T2, and body terminal. The floating gate 112 of transistor T1 corresponds to the data storage element of nonvolatile memory cell 102. Depending on the specific configuration of memory cell 102, data can be stored in the floating gate 112 when a tunneling current causes charge to be stored in or removed from the floating gate 112. Depending on the configuration of nonvolatile memory cell 102, nonvolatile memory cell 102 can be erased in a similar manner by a tunneling current that stores or removes charge from the floating gate 112. Nonvolatile memory cell 102 can be read by applying a read voltage to the control gate CG, bit line BL, and gate of transistor T2, and then sensing the current flowing through transistors T1 and T2 (or the absence of current). Further details regarding the read, program, and erase operations of nonvolatile memory cell 102 will be described below.

[0031] return Figure 1A The integrated circuit 100 includes a substrate 104. The substrate 104 may include a semiconductor material. In one embodiment, the semiconductor material of the substrate 104 includes silicon. Alternatively, other semiconductor materials may be used, including but not limited to: germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof. Other substrates such as single-layer, multi-layer, or gradient substrates may be used.

[0032] In one embodiment, the substrate 104 beneath transistors T1 and T2 includes a doped region 105. In one embodiment, the doped region is a P-well. The P-well may correspond to a semiconductor material doped with a P-type dopant (such as boron or another suitable dopant). The dopant concentration of the P-well may be between 1E14 / cm^3 and 1E18 / cm^3, but other values ​​may be used without departing from the scope of this disclosure.

[0033] In one embodiment, the P-well extends from the top surface of substrate 104 to the bottom surface of substrate 104. Alternatively, the P-well may extend from the top surface of substrate 104 to a selected depth within substrate 104.

[0034] In one embodiment, the P-well corresponds to the body region of transistors T1 and T2. Although in Figure 1ANot shown, but integrated circuit 104 includes one or more body contacts as part of read, program, and erase operations of the non-volatile memory cell 102, through which a selected body voltage can be applied to the P-well of the body region 105. While this description may focus primarily on an embodiment where the body region of the transistor of the non-volatile memory cell 102 is a P-well, in other embodiments, the body region of the non-volatile memory cell 102 may include an N-well.

[0035] Substrate 104 includes an active region 106. The active region 106 corresponds to a portion of the source, drain, and channel regions of transistors T1 and T2 in substrate 104. The active region may correspond to an active diffusion region commonly referred to as "OD".

[0036] In one embodiment, the active region 106 corresponds to an N-well embedded within a P-well in the body region 105. The N-well extends from the top surface of the substrate 106 to a selected distance within the P-well. The N-well may correspond to a semiconductor material doped with an N-type dopant (such as phosphorus, arsenic, or other suitable N-type dopant). The N-well of the active region 106 may extend continuously beneath transistors T1 and T2.

[0037] In one embodiment, the integrated circuit 100 includes a field dielectric region 108 (e.g., a field oxide region) extending into a substrate 104. A portion of the field dielectric region 108 may be above the substrate 104, and a portion of the field dielectric region 108 may be below the substrate 104. In one embodiment, the field dielectric region 108 may correspond to a shallow trench isolation (STI) region. The field dielectric region 108 includes a dielectric material. In an exemplary embodiment, the dielectric material includes silicon oxide, such as SiO2. However, without departing from the scope of this disclosure, the dielectric material may include SiN, SiCN, SiOC, SiOCN, or other dielectric materials.

[0038] In one embodiment, a portion of the body region 105 outside the active region 106 corresponds to a field region of the substrate 104. The field region may include a portion of the body region 105 below the field dielectric region 108.

[0039] Integrated circuit 100 includes a gate dielectric layer 110. The gate dielectric layer 110 corresponds to a thin layer of dielectric material directly above the channel regions of transistors T1 and T2. In an exemplary embodiment, the gate dielectric layer 110 includes silicon oxide. However, the gate dielectric layer 110 may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, or other suitable dielectric materials.

[0040] Despite Figure 1ANot clearly shown in the view, but the gate dielectric 110 may include a first portion directly above the channel region of the floating gate transistor T1 and a second portion directly above the channel region of the select transistor T2. The first and second portions are separate from each other. The channel region of transistor T1 corresponds to the upper portion of the active region 106 directly below the floating gate 112 of the floating gate transistor T1. The channel region of transistor T2 corresponds to the upper portion of the active region 106 directly below the gate terminal 113 of the select transistor T2. The gate dielectric 110 may be made of the same material as the field dielectric 108. The gate dielectric 110 may be adjacent to the field dielectric 108.

[0041] Integrated circuit 100 includes a polysilicon layer for a floating gate 112 for a floating gate transistor T1 and a gate terminal 113 for a select transistor T2. Therefore, the floating gate terminal 112 of the floating gate transistor T1 and the gate terminal 113 of the select transistor T2 correspond to the same polysilicon layer. While this description primarily describes an embodiment where the floating gate 112 and gate terminal 113 are polysilicon, other gate materials may be used without departing from the scope of this disclosure.

[0042] A floating gate 112 is disposed on the field dielectric 108 and the gate dielectric 110. The floating gate 112 extends in the Y direction on the field dielectric 108, extends across the active region 106 on the gate dielectric 110, and extends on the field dielectric 108 on the other side of the active region 106. In one embodiment, the floating gate 112 extends sufficiently in the Y direction on each side of the active region 106 that individual control gate contacts can be disposed directly above the floating gate on each side of the active region 106, as will be described in further detail below.

[0043] In one embodiment, the floating gate transistor T1 includes a silicide protection (SIPROT) dielectric layer 114. The silicide protection dielectric layer 114 serves for the capacitive coupling of the floating gate 112. In other words, the silicide protection layer 114 is the dielectric material between the first terminal (CG) of the capacitor C and the second terminal (floating gate 112) of the capacitor C. Before providing a further description of the silicide protection dielectric layer 114, it is beneficial to describe aspects of the selection transistor T2.

[0044] The select transistor T2 includes a polysilicon gate terminal 113. A gate contact 118 is directly coupled to the gate terminal 113 of the select transistor T2. The gate contact 118 corresponds to a metallic structure such as a conductive plug or conductive path through which a voltage can be applied to the gate terminal 113. In other words, the select signal SEL is provided to the gate terminal 113 via the gate contact 118. The gate contact 118 may include one or more of tungsten, titanium, aluminum, titanium nitride, tantalum nitride, or other suitable conductive materials.

[0045] To provide a strong electrical connection between the gate contact 118 and the gate terminal 113, a silicide (not shown) is formed on the top surface of the gate terminal 113 of the select transistor T2. This silicide can be formed by depositing a conductive metal (such as titanium, nickel, or other suitable metal). A thermal annealing process can then be performed to form a silicide from the polysilicon and metal at the polysilicon-metal interface. The gate contact 118 can then be subsequently formed.

[0046] A silicon protective dielectric layer 114 is used to help ensure that no silicide is formed on the polysilicon of the floating gate 112 of transistor T1. Therefore, after depositing and patterning polysilicon to form the floating gate 112 and gate terminal 113, a silicon protective dielectric layer 114 is formed over the surface of integrated circuit 100.

[0047] Initially, a silicon protective dielectric layer 114 covers both the floating gate 112 and the gate terminal 113. The silicon protective dielectric layer 114 is then patterned to expose the polysilicon of the gate terminal 113 of transistor T2, while simultaneously covering the polysilicon of the floating gate 112. A metal for the previously described silicide can then be deposited on the gate terminal 113, and a silicide can be formed. Due to the presence of the silicide protective dielectric layer 114, no silicide is formed at the floating gate 112. The silicide protective dielectric layer 114 may be referred to as a silicide protective mask.

[0048] In one embodiment, the silicide-protected dielectric layer 114 comprises a stack of dielectric layers. In one example, the silicide-protected dielectric layer 114 comprises a first silicon oxide layer directly on the floating gate 112. The silicide-protected dielectric layer 114 comprises a second tetraethyl orthosilicate (TEOS) layer on the first silicon oxide layer. The silicide-protected dielectric layer 114 comprises a third silicon nitride layer on the second TEOS layer. Other layers and combinations thereof may be used for the silicide-protected dielectric layer 114 without departing from the scope of this disclosure.

[0049] In one embodiment, the floating gate transistor T1 includes a first control gate contact 116a and a second control gate contact 116b. In other words, the control gate of the memory device includes a plurality of discrete elements (i.e., control gate contacts 116a / b).

[0050] The first and second control gate contacts 116a / b are formed on a silicon protective dielectric layer 114 directly above the floating gate 112. The control gate contacts 116a / b can be formed using the same deposition process and from the same material as the gate contact 118. Alternatively, the control gate contacts 116a / b can be formed from a different material than the gate contact 118.

[0051] In one embodiment, control gate contacts 116a / b are formed on opposite sides of the active region 106 without overlapping with it. Control gate contact 116a is formed on the side of the active region 106 opposite to the gate contact 118 of transistor T2. Control gate contact 116b is formed on the same side of the active region 106 as the gate contact 118 of transistor T2.

[0052] In one embodiment, one or both of the control gate contacts 116a / b overlap with the active region 106. In other words, one or both of the control gate contacts 116a / b may be partially formed over the active region 106 and partially formed over the field dielectric region 108.

[0053] The control gate contacts 116a / b correspond to the first terminal of the capacitor C in the non-volatile memory cell 102. The floating gate 112 corresponds to the second terminal of the capacitor C in the non-volatile memory cell 102. The silicide protective dielectric layer 114 corresponds to the dielectric of the capacitor C.

[0054] In one embodiment, control gate contact 116a has a much larger occupied area than control gate contact 116b. In one embodiment, control gate contact 116a has an occupied area greater than or equal to 10 times the occupied area of ​​control gate contact 116b. In one embodiment, control gate contact 116a has an occupied area greater than or equal to 100 times the occupied area of ​​control gate contact 116b.

[0055] As used herein, the term "active region" refers to the location defining the transistor channel, source, and drain, and may include the region forming a well-ohmic contact. As used herein, the term "field region" refers to the region outside the active region, where a thick oxide or other dielectric is used for isolation between adjacent active regions.

[0056] Figure 2According to one embodiment Figure 1A A cross-sectional perspective view of integrated circuit 100. This section is taken through the floating gate transistor T1. Figure 2 The cross-sectional view more clearly illustrates the thin gate dielectric layer 110 directly between the active region 106 and the floating gate 112.

[0057] Figure 3 The view also illustrates that the polysilicon of the control gate 113 extends further in the Y direction on one side of the active region 106 compared to the other side of the active region 106. Figure 3 The illustration shows that, compared to the polysilicon of the gate terminal 113 of transistor T2, the polysilicon of the floating gate 112 extends further in the Y direction on both sides of the active region 106. Furthermore, the polysilicon of the gate terminal of transistor T2 is narrower in the X direction compared to the polysilicon of the floating gate 112 of floating gate transistor T1.

[0058] Figure 4 This is a perspective view of an integrated circuit 100 including a non-volatile memory cell 102 according to one embodiment. Figure 4 Non-volatile memory cell 102 and Figure 1A The non-volatile memory cell 102 is basically similar. However, in Figure 4 In the non-volatile memory cell 102, the silicide protective dielectric layer 114 is patterned so that it does not cover the active region 106.

[0059] Figure 5 This is a cross-sectional view of the floating gate transistor T1 of a non-volatile memory cell 102 according to one embodiment. Figure 5 floating gate transistor T1 and Figure 1A The floating gate transistor T1 is essentially similar. This cross-sectional view illustrates the active region 106 embedded in the substrate 104 / body region 105. A thick field dielectric region 108 lies on each side of the active region 106. A thin gate dielectric layer 110 is disposed directly above the active region 106. A floating gate 112 is disposed above the field dielectric region 108 and the gate dielectric 110. A silicide protective dielectric layer 114 is disposed above the floating gate 112. Figure 5 In this configuration, the silicide protective dielectric layer 114 has a flat top surface. Control gate contacts 116a / b are disposed directly on the silicide protective dielectric layer 114 above the floating gate 112 on each side of the active region 106 (not above the active region). The field region of the substrate 104 corresponds to a portion of the substrate 104 below the field dielectric region 108, or in other words, to the side surface of the active region 106.

[0060] Figure 6This is a top view of the layout of a portion of the floating gate transistor T1 of a non-volatile memory cell 102 according to one embodiment. The top view illustrates an active region extending in the X direction within a substrate 104 / body region 105. A floating gate 112 covers a portion of the active region 106 and the substrate 104 / body region 105 on each side of the active region 106. Control gate contacts 116a / b are formed on each side of the active region 106 without overlapping with it; that is, the control gate contacts 116a / b are staggered relative to the active region 106, and more specifically, the control gate contacts 116a / b are perpendicularly staggered relative to the active region 106 (where the perpendicular direction is along or parallel to the Z direction). However, as previously described, in one embodiment, one or both of the control gate contacts 116 may at least partially overlap with the active region 106.

[0061] return Figure 1B According to one embodiment, a description of read, program, and erase operations on non-volatile memory cell 102 will now be described. When memory cell 102 is to be read, the select signal SEL rises to the read voltage and the NMOS select transistor T2 is activated. The body voltage (e.g., P-well voltage) is set to ground. A bit line read voltage is applied to bit line BL. A control gate read voltage is applied to the control gate (e.g., control gate contacts 116a / b). If the floating gate 112 is in an erase state, the floating gate transistor T1 is turned on, and current flows through transistors T1 and T2 between bit line BL and source line SL. A sense amplifier is connected to the bit line via a multiplexer (not shown). The sense amplifier senses the current and determines that the non-volatile memory cell 102 is in an erase state (e.g., data value 0).

[0062] If the floating gate is in a programmed state (e.g., data value 1), then the floating gate transistor T1 will not conduct when various read voltages are applied. As a result, no current will flow through transistors T1 and T2. The lack of current will be sensed by the sense amplifier, and memory cell 102 will be determined to be in a programmed state.

[0063] In one embodiment, if memory cell 102 is in a memory sector selected for a read operation but not coupled to a word line selected for a read operation in that sector, the control gate signal will be at the read voltage of the select signal SEL, which will be low (e.g., ground), and transistor T2 will not be turned on. As a result, no current will flow through transistors T1 and T2 regardless of whether memory cell 102 is in an erase or programmable state.

[0064] In one embodiment, if memory cell 102 is not coupled to a word line selected for a read operation in a memory sector that is not selected for a read operation, the control gate signal will be grounded and the value of the select signal SEL will be grounded, and transistor T2 will not be turned on. As a result, no current will flow through transistors T1 and T2 regardless of whether memory cell 102 is in erase or program mode.

[0065] In one embodiment, floating-gate programming of volatile memory cells is achieved via Fowler-Nordheim (FN) tunneling. If memory cell 102 is in a selected sector and is selected for programming, a high programming voltage is applied to the control gate, grounding the bit line BL, grounding the body terminal, and grounding the source line. The bit line BL is grounded through the programming path. As a result, tunneling current flows out from the floating gate 112 of the floating-gate transistor T1. The tunneling current tunnels across the gate dielectric 110, thereby changing the net charge in the polysilicon floating gate 112. This corresponds to the programming of the memory cell.

[0066] In one embodiment, erasing the memory cell 102 includes hot hole injection using the floating gate 112. In one embodiment, programming the memory cell 102 includes hot electron injection using the floating gate 112.

[0067] If non-volatile memory cell 102 is in a selected sector but is not selected for programming, the control gate is set to the programming voltage, the body terminal to ground, and the source line to ground. The bit line is set to a high voltage. In other words, the bit line is connected to the programming disable voltage via the programming path. The high voltage on the bit line BL prevents tunneling current from flowing across the gate dielectric 110. As a result, non-volatile memory cell 102 is not programmed.

[0068] If the non-volatile memory cell 102 is an unselected word line and is in a sector not selected for programming operations, then the control gate, source line, and body region B are all grounded. If the memory cell 102 is connected to a selected bit line, then the bit line is also grounded. The tunneling current of the cell is not programmed. If the memory cell 102 is coupled to an unselected bit line, then the unselected bit line is set to a programming-inhibited voltage and no tunneling current flows.

[0069] In one embodiment, memory cell erasure occurs at the sector level. In other words, an entire sector of the memory cell can be erased simultaneously. If memory cell 102 is part of a selected sector for the erase operation, the gate terminal of the select transistor is set to a high erase voltage. The control gate is grounded. The body terminal B is set to a high erase voltage. The bit line BL and the source line SL are floating. As a result, tunneling current tunnels across the gate dielectric 110 from the body region B to the polysilicon floating gate 112. This causes memory cell 102 to be erased.

[0070] In one embodiment, if memory cell 102 is part of a sector that was not selected during the erase operation, the control gate is set to an erase-inhibit voltage. The other terminals are at the same voltages described for the selected sector. As a result, no tunneling current flows in memory cell 102 that are not erased.

[0071] Figure 7A This is a layout top view of an integrated circuit 100 including a non-volatile memory array 101 according to one embodiment. The memory array 101 includes a plurality of non-volatile memory cells, such as those for... Figures 1A to 6 The non-volatile memory cell 102 is shown. For the sake of simplicity in understanding this layout, in Figure 7A Word lines, bit lines, and select lines are not shown. Instead, in... Figure 7C The text shows word lines, bit lines, and select lines.

[0072] Figure 7A The view illustrates multiple memory cells 102. However, only a single memory cell 102 and its corresponding contact are detailed using reference numerals. The memory cell 102 provided in detail is surrounded by a dashed box, which indicates the area corresponding to the memory cell 102.

[0073] This memory cell is formed in conjunction with an active region 106 extending in the X direction. Because... Figure 7A The diagram shows three active regions 106, which are formed in conjunction with a central active region 106 and memory cells 102, as detailed. A polysilicon floating gate 112 has a relatively large first portion on a first side of the active region 106. This first portion is covered by a large first control gate contact 116a. This large portion of the floating gate 112 and the control gate contact 116a provides a large capacitive coupling between the floating gate 112 and the control gate contact 116a.

[0074] The polysilicon floating gate 112 has a second portion on the opposite side of the active region 106. The second portion has a much smaller area than the first portion. A control gate contact 116b is formed above the second portion of the floating gate 112.

[0075] The polysilicon control gate 113 of the select transistor T2 is also formed to cover the active region 106. Two gate contacts 118 are formed on the same side of the active region 106 above the control gate 113. The source contact of the select transistor T2 contacts the active region 106 to the left of the control gate 113. The drain contact of the floating gate transistor 112 contacts the active region 106 to the right of the floating gate 112.

[0076] Figure 7A The view also illustrates window 126, marked by a dashed box. Window 126 corresponds to the region where the silicide protective dielectric layer 114 is absent. Therefore, the gate contact 118 directly contacts the polysilicon gate 113 in window 126. Because the silicide protective dielectric layer 114 is absent, the previously described silicide is formed at this location.

[0077] Figure 7B According to one embodiment Figure 7A A magnified view of a portion of the layout. Or specifically, Figure 7B It's about the layout being appropriate and targeted. Figure 7A An enlarged view of a portion corresponding to the detailed non-volatile memory cell 102. Figure 7B It also includes a circuit diagram representation of the memory cell 102 superimposed on the layout diagram.

[0078] Figure 7B The view helps to illustrate the capacitor C more clearly, which mainly corresponds to the large area of ​​the floating gate 112 on which the control gate contact 116a is formed. Figure 7B The view also helps to illustrate the layout portions corresponding to the source, drain, and gate contacts of memory cell 102.

[0079] Figure 7C Corresponding to one embodiment Figure 7A The view shows bit lines BL, select lines SEL, and word lines WL. Each word line WL connects to the control gate contact 116a of eight memory cells. Word line WL0 connects to the control gate contact 116a of memory cell 102, details of which are shown in [the original text]. Figure 7A and Figure 7B Provided in [the document / framework]. Each control gate identifies the word line WL and sector. [In the document / framework] Figure 7C The text shows two word lines, WL.

[0080] In one embodiment, memory array 101 corresponds to a virtual NOR architecture, where consecutive memory cells share the same bit line BL, which is the drain line of one cell and the source line of another cell. Bit line BL3 is coupled to the drain contact 124 of memory cell 102, details of which are described in... Figure 7A and Figure 7BProvided in [the document]. Bit line BL1 is coupled to source contact 122 of select transistor T2, which corresponds to the source line of select transistor T2, details of which are provided in [the document]. Figure 7A and Figure 7B Provided by China.

[0081] Each select line SEL is connected to the gate contact 118 of multiple memory cells 102. Memory cells sharing the same select line SEL have different bit lines BL. This allows for current contribution from a single cell during read operations, even in the event of cell depletion. Select line SEL1 is connected to the gate contact 118 of the select transistor T2 of memory cell 102, details of which are provided below. Figure 7A and Figure 7B Provided by China.

[0082] In one embodiment, non-volatile memory bit cells according to the principles of this disclosure can be implemented without selecting transistors. In this case, the configuration of memory array 101 can be changed from a virtual NOR arrangement to a NOR arrangement.

[0083] Other layouts and configurations of the memory array 101 and memory cells 102 may be utilized in conjunction with the principles of this disclosure without departing from the scope of this disclosure.

[0084] Figure 8 This is a top view layout of a memory array 101 including a plurality of memory cells 102 according to one embodiment. Figure 8 The layout of the memory array 101 and Figure 7A The layout of the memory array 101 is basically similar, the difference is that Figure 8 The control gate contact 116b is not present. Other variations may be used without departing from the scope of this disclosure.

[0085] Figure 9 This is a cross-sectional view of an integrated circuit 100 including a floating gate transistor T1 with a non-volatile memory cell 102, according to one embodiment. Figure 9 Only the floating gate transistor T1 is shown in the diagram. However, the memory cell 102 may include a selection transistor T2 and, for example, a selection transistor T2 for... Figures 1A to 7C Other links described.

[0086] Integrated circuit 100 includes a substrate 104. Substrate 104 corresponds to a semiconductor substrate and may include a semiconductor material, such as... Figure 1A The semiconductor material described in substrate 104.

[0087] The substrate 104 includes a body region 105. In one embodiment, the body region 105 is a P-well region. In other words, the body region 105 may be a well region doped with a P-type dopant.

[0088] In one embodiment, substrate 104 includes a deep well region 107. In one embodiment, the deep well region 107 is an N-well region below the body region 105. The N-well region may be doped with N-type dopant.

[0089] In one embodiment, substrate 104 includes an active region 106. Active region 106 corresponds to the region in which the source, drain, and channel regions of transistors T1 and T2 are formed. Active region 106 extends in the X-direction. In one embodiment, active region 106 is an upward extension of body region 105. In one embodiment, active region 106 is doped with a P-type dopant.

[0090] In one embodiment, the integrated circuit 100 includes a field dielectric region 108 on each side of the active region 106. The field dielectric region 108 may include regions for... Figure 1A The field dielectric region 108 describes the material and properties. The field dielectric region 108 may correspond to a shallow trench isolation region.

[0091] In one embodiment, the floating gate transistor T1 includes a silicon dielectric layer 110. The gate dielectric region 110 includes a very thin dielectric layer directly above the active region 106. The gate dielectric layer 110 may include components for... Figure 1A The materials and properties of the gate dielectric layer 110 are described. The gate dielectric layer 110 may be adjacent to the field dielectric region 108. The gate dielectric layer 110 may correspond to the same gate dielectric layer used in CMOS transistors and power MOS transistors of integrated circuit 100.

[0092] In one embodiment, the floating gate transistor T1 includes a polysilicon floating gate 112. The polysilicon floating gate 112 may include features for... Figure 1A The polysilicon floating gate 112 describes the material and properties.

[0093] In one embodiment, transistor T1 includes a dielectric sidewall spacer 154 formed on the sidewall of a polysilicon floating gate 112. The dielectric sidewall spacer 154 may include one or more of SiN, SiCN, SiOC, SiOCN, or other dielectric materials. The dielectric sidewall spacer 154 may include multiple dielectric material layers.

[0094] In one embodiment, transistor T1 includes a dielectric layer 150 on the top surface of a polysilicon floating gate 112. The dielectric layer 150 may include one or more of SiO2, SiN, SiCN, SiOC, SiOCN, or other dielectric materials. In one embodiment, the dielectric layer 150 is a silicide protective layer and may have a dielectric material similar to... Figure 1A The composition of the silicide protective layer 114 is substantially similar. In one embodiment, the thickness of the dielectric layer 150 is approximately 80 nm. The composition of the dielectric layer 150 thickness can be selected so that it can also be used in conjunction with power MOS transistors that can be implemented within the integrated circuit 100.

[0095] In one embodiment, transistor T1 includes a metal field plate 152. The metal field plate 152 serves as a control gate contact for a non-volatile memory cell 102. The metal field plate 152 corresponds to a first terminal of a capacitor C in the memory cell 102. A dielectric layer 150 serves as the dielectric of the capacitor C in the memory cell 102. A polysilicon floating gate 112 serves as a second terminal of the capacitor C in the memory cell 102.

[0096] In one embodiment, a metal field plate 152 covers the field oxide region 108 on each side of the active region 106. The metal field plate 152 also covers the active region 106. The metal field plate 152 may completely cover the polysilicon floating gate 112. Alternatively, the metal field plate 152 may partially cover the polysilicon floating gate 112. In other words, the control gate of the memory device comprises a single element (i.e., the metal field plate 152).

[0097] In one embodiment, the metal field plate 152 comprises titanium nitride. Alternatively, the metal field plate 152 may comprise aluminum, titanium, tantalum, tungsten, tantalum nitride, or other suitable conductive materials. The metal field plate 152 may comprise multiple metal layers or conductive material layers.

[0098] In one embodiment, the combination of the metal field plate 152, the floating gate 112, and the dielectric layer 150 provides a relatively high breakdown voltage. This breakdown voltage can be higher than 20V. In one embodiment, in an example where the dielectric layer 150 comprises silicon oxide with a thickness of about 80 nm, the breakdown voltage is about 100V.

[0099] In one embodiment, the metal field plate 152 enables both positive and negative polarities to be provided to the control gate of the capacitor C. This provides flexibility in designing the memory array layout and the read, program, and erase schemes for the non-volatile memory cell 102. Furthermore, the memory cell 102 allows the capacitive coupling between the floating gate and the control gate to be independent of the thickness of the dielectric layer 150. This can be adjusted by utilizing the overlap of the floating gate and the control gate on the field oxide region 108.

[0100] Figure 10 This is a flowchart of a method 1000 for forming a non-volatile memory cell according to one embodiment. Method 1000 can utilize [a specific method / approach]... Figures 1A to 9 The materials, components, structures, and processes are described. At 1002, method 1000 includes forming a field oxide on a substrate. An example of a field oxide is... Figure 1A The field dielectric 108. An example of a substrate is... Figure 1A Substrate 104.

[0101] At 1004, method 1000 includes forming a gate oxide for a select transistor and a floating gate transistor. An example of a floating gate transistor is... Figure 1A The floating gate transistor T1. An example of a selected transistor is... Figure 1A Transistor T2. An example of gate oxide is... Figure 1A The gate dielectric layer 110.

[0102] At 1006, method 1000 includes depositing a polysilicon layer and patterning it to form a select gate and a floating gate. An example of polysilicon is... Figure 1A The polysilicon 113 at the gate terminal of transistor T2 and Figure 1A The floating gate transistor T1 has a polysilicon floating gate 112.

[0103] At 1008, method 1000 includes depositing silicide protective dielectric layers on the floating gate and the selected gate. An example of a silicide protective dielectric layer is... Figure 1A The silicide protective dielectric layer 114.

[0104] At 1010, method 1000 includes removing the silicide protective dielectric layer from the select gate. This includes patterning the silicide protective dielectric layer to form a window exposing the polysilicon gate of the select transistor. An example of the window is... Figure 7A Window 126.

[0105] At 1012, method 1000 includes depositing a metal layer on the silicide protective dielectric layer and on the exposed portion of the polysilicon select gate.

[0106] At 1014, method 1000 includes forming a first control gate contact and a second control gate contact on a silicide protective dielectric layer by patterning a metal layer, and forming a gate contact on a select gate. An example of the first and second control gate contacts is... Figure 1A The control gate contacts 116a and 116b. An example of a gate contact is... Figure 1A Gate contact 118.

[0107] These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the entire scope of equivalents to which such claims are granted. Accordingly, the claims are not limited by this disclosure.

[0108] This disclosure can also be exemplified by memory devices according to the following non-limiting examples 1 to 5.

[0109] Example 1. A memory device comprising: a semiconductor substrate including an active region and a field region; a floating gate; a control gate above the floating gate; and a dielectric layer disposed between the control gate and the floating gate, wherein the control gate includes a plurality of discrete elements.

[0110] Example 2. The memory according to Example 1, wherein the plurality of discrete elements include a first control gate contact and a second control gate contact, both of which are in direct contact with the dielectric layer.

[0111] Example 3. The memory according to Example 2, wherein the first contact area of ​​the first control gate contact and the first contact area of ​​the dielectric layer at least partially covers the field area of ​​the first side of the active region; and the second contact area of ​​the second control gate contact and the second contact area of ​​the dielectric layer at least partially covers the field area of ​​the second side of the active region opposite to the first side.

[0112] Example 4. The memory according to Example 3, wherein the first contact region is laterally completely outside the active region on the first side, and wherein the second contact region is laterally completely outside the active region on the second first side.

[0113] Example 5. The memory according to Example 1, wherein the dielectric layer is a silicide protective layer comprising multiple sublayers.

[0114] This disclosure can also be exemplified by memory devices according to the following non-limiting examples 6 to 8.

[0115] Example 6. A memory device comprising: a semiconductor substrate including an active region and a field region; a floating gate covering the active region and the field region; a control gate disposed above the floating gate; and a dielectric layer interposed between the control gate and the floating gate, wherein the control gate covers the field region without overlapping the active region.

[0116] Example 7. The memory device according to Example 6 includes a non-volatile memory cell comprising: a floating gate transistor including a floating gate; and a selection transistor including a gate terminal made of the same material as the floating gate and disposed above an active region and a field region, and including a gate contact that directly contacts the gate terminal and covers the field region without overlapping the active region.

[0117] Example 8. The memory device according to Example 7, wherein the gate contact contacts the gate terminal through an opening in the dielectric layer.

[0118] This disclosure can also be illustrated by a method of manufacturing a memory device according to the following non-limiting examples 9 to 12.

[0119] Example 9. A method of manufacturing a memory device, comprising: a floating gate of an active region and a field region of a covering semiconductor substrate forming a floating gate transistor of a memory cell; a gate terminal of an active region and a field region of a covering semiconductor substrate forming a select transistor of the memory cell, the floating gate and the gate terminal having the same material; forming a dielectric layer above the floating gate and the gate terminal; forming a window in the dielectric layer exposing the gate terminal; forming a control gate of the floating gate transistor on the dielectric layer above the floating gate; and forming a gate contact in the opening that contacts the gate terminal.

[0120] Example 10. The method according to Example 9 includes: depositing metal on a gate terminal and a dielectric layer; and forming a gate contact and a control gate by patterning the metal.

[0121] Example 11. The method according to Example 9, wherein the dielectric layer comprises a plurality of dielectric sublayers.

[0122] Example 12. The method according to Example 9 includes forming a silicide on a gate contact.

[0123] This disclosure can also be illustrated by the reading methods of the memory device according to the following non-limiting examples 13 to 15.

[0124] Example 13. A method of reading data from a non-volatile memory cell, the non-volatile memory cell including a floating gate transistor including a floating gate covering an active region and a field region of a semiconductor substrate, the data reading including: applying a read body voltage to the field region; applying a read control gate voltage to a control gate disposed on a dielectric layer disposed on the floating gate, the control gate covering the field region; and sensing a current in response to the read control gate voltage.

[0125] Example 14. The method according to Example 13, wherein reading data includes applying a selection voltage to the gate terminal of the selection transistor of the memory cell, the gate terminal covering the active region.

[0126] Example 15. The method according to Example 14 includes applying a selection voltage via a gate contact extending through an opening in the dielectric layer to contact a gate terminal.

Claims

1. A memory device (100), comprising: The semiconductor substrate (104) includes an active region (106) and field regions (105, 108); A floating gate (112) is located above the semiconductor substrate (104); Control gates (116a, 116b; 152) are located above the floating gate (112); and A dielectric layer (114; 150) is inserted between the control gate (116a, 116b; 152) and the floating gate (112), wherein the control gate (116a, 116b; 152) is at least partially made of a metallic material.

2. The memory device according to claim 1, comprising a non-volatile memory cell (102), the non-volatile memory cell comprising a floating gate transistor (T1) and a select transistor (T2), the floating gate transistor and the select transistor being disposed above the active region (106).

3. The memory device according to claim 2, wherein: The floating gate transistor (T1) includes the floating gate (112); The selection transistor (T2) includes a gate terminal made of the same material as the floating gate (112); and The dielectric layer (114; 150) includes an opening above the gate terminal.

4. The memory device according to claim 3, wherein, The dielectric layer (114; 150) is a silicide protective dielectric layer comprising multiple sublayers.

5. The memory device according to claim 4, wherein, The sublayer comprises a first sublayer of silicon oxide, a second sublayer of tetraethyl orthosilicate on the first sublayer, and a third sublayer of silicon nitride on the second sublayer.

6. The memory device according to claim 2, wherein, The control gate includes: A first control gate contact (116a) contacts the dielectric layer (114) above the floating gate (112) and overlaps the field regions (105; 108) on the first side of the active region (106); and The second control gate contact (116b) contacts the dielectric layer (114) above the floating gate (112) and overlaps the field region (105; 108) on the second side of the active region (106).

7. The memory device according to claim 6, wherein, The first control gate contact (116a) and the second control gate contact (116b) do not overlap with the active region.

8. The memory device according to claim 6, wherein, The first control gate contact (116a) and the floating gate (112) form a first capacitor region, wherein the second control gate contact (116b) and the floating gate (112) form a second capacitor region, wherein the first capacitor region is at least 10 times larger than the second capacitor region.

9. The memory device according to claim 2, comprising a field dielectric (108) disposed on a first side of the active region (106) and a second side of the active region (106) opposite to the first side, wherein, The control gate includes a metal field plate (152) that continuously covers the active region (106), the field dielectric (108) on the first side of the active region (106), and the field dielectric (108) on the second side of the active region (106).

10. The memory device of claim 9, comprising a dielectric sidewall spacer (154) on the sidewall of the floating gate (112), wherein, The dielectric layer (150) is in direct contact with the dielectric sidewall spacer (154).

11. The memory device according to claim 2, wherein, The floating gate transistor and the selection transistor both have corresponding gate dielectrics of the same thickness and the same material.

12. The memory device according to claim 1, wherein, The field region includes a P-well, wherein the active region includes an N-well.

13. The memory device according to claim 1, wherein, The control gate includes a plurality of discrete elements (116a, 116b) in direct contact with the dielectric layer (114), wherein a first discrete element (116a) at least partially covers the field region (105; 108) on a first side of the active region (106); and a second discrete element (116b) at least partially covers the field region (105; 108) on a second side of the active region (106) opposite to the first side, and wherein the plurality of discrete elements (116a, 116b) are formed entirely outside the active region (106).

14. The memory device according to claim 1, wherein, The control gate includes a single element (152) in contact with the dielectric layer (150), the single element (152) being formed continuously over both the active region (106) and the field region (105; 108).

15. The memory device according to claim 14, wherein, The single element (152) completely covers the floating gate (112).

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