Self-aligned stacked gate NORD flash memory structure and manufacturing method thereof
By combining a self-aligned stacked gate structure with a metal silicide layer, the problem of high resistivity of the polysilicon interconnects for the control gate in NORD flash memory is solved, thereby improving read speed and meeting the requirements of high-performance applications.
Patent Information
- Application Number
- CN202511049709.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-29
- Publication Date
- 2025-11-11
AI Technical Summary
The high resistivity of the polysilicon control gate interconnects in existing NORD flash memory leads to severe RC delay effects, which limits the read speed of the flash memory.
A self-aligned stacked gate structure is adopted, using the polysilicon sidewall of the control gate as a mask for etching, and forming a low-resistivity metal silicide layer on its top surface, which simplifies the manufacturing process and improves alignment accuracy and integration.
It significantly reduces the resistance of the control gate interconnects, reduces the RC delay effect on the signal transmission path, improves the read speed of NORD flash memory, and meets high performance requirements.
Smart Images
Figure CN120936031A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a self-aligned stacked gate NORD flash memory structure and its manufacturing method. Background Technology
[0002] Non-volatile memory, especially flash memory, is widely used in various electronic devices. NORD flash memory is a common flash memory structure that achieves data writing and erasure by storing charge between a floating gate and a control gate.
[0003] In the operation of NORD flash memory, read operations are one of the key performance indicators. During a read operation, a boost circuit charges the control gate to form a conductive path in the channel region. This charging process is transmitted via a voltage pulse along the polysilicon interconnect connecting the control gate to the memory cell array.
[0004] However, as device size continues to shrink and integration density increases, the length and density of the control gate polysilicon interconnects also increase. Due to the inherently high resistivity of polysilicon, the total resistance (R) of the control gate polysilicon interconnects is significant. In high-speed read operations on the nanosecond (ns) scale, this resistance, along with the device's inherent parasitic capacitance (C), constitutes a significant RC delay effect. This RC delay slows down the transmission speed of voltage pulses on the control gate interconnects and decelerates the signal rise time, severely limiting the overall read speed of NORD flash memory and failing to meet the ever-increasing demands for high performance.
[0005] Therefore, how to effectively reduce the line resistance of the control gate to reduce the RC delay effect and significantly improve the read speed of NORD flash memory is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0006] The purpose of this application is to provide a self-aligned stacked gate NORD flash memory structure with high read speed and its manufacturing method, so as to solve the technical problem in the prior art that the high resistivity of the control gate polysilicon interconnect leads to severe RC delay, thereby limiting the flash memory read speed.
[0007] To achieve the above and other related objectives, the present invention provides a self-aligned stacked gate NORD flash memory structure, comprising:
[0008] Substrate;
[0009] A floating gate, wherein the floating gate is disposed on the substrate and is made of floating gate polysilicon;
[0010] A control gate polysilicon sidewall, which serves as the control gate of the structure and is located above the floating gate, wherein the inner sidewall of the control gate polysilicon sidewall defines one sidewall of the floating gate, thereby forming a self-aligned structure;
[0011] Word lines, said word lines being made of word line polysilicon; and
[0012] A metal silicide layer is disposed on the top surface of the polysilicon sidewall of the control gate.
[0013] Preferably, the top surface of the control gate polysilicon sidewall has a predetermined height, and the top surface of the word line has another predetermined height, wherein the height of the top surface of the control gate polysilicon sidewall is higher than the height of the top surface of the word line.
[0014] Preferably, it further includes a metal silicide layer disposed on the top surface of the word line.
[0015] Preferably, it further includes: a coupling oxide layer disposed between the substrate and the floating gate; a polysilicon isolation dielectric layer disposed on the floating gate; and a tunneling oxide layer disposed between the sidewall of the floating gate and the channel region.
[0016] Preferably, the polycrystalline silicon isolation dielectric layer has an oxide-nitride-oxide structure.
[0017] Preferably, it further includes a final sidewall, which is disposed on the sidewall of the memory cell formed by the floating gate, the control gate polysilicon sidewall, and the word line.
[0018] Preferably, a first sidewall dielectric layer and a second sidewall dielectric layer are further formed between the tunneling oxide layer and the inner sidewall of the control gate polysilicon sidewall.
[0019] Preferably, the first sidewall dielectric layer is a first sidewall silicon oxide layer.
[0020] Preferably, the second sidewall dielectric layer is a sidewall silicon nitride layer.
[0021] This invention also provides a method for manufacturing a self-aligned stacked gate NORD flash memory structure, comprising:
[0022] Step 1: Sequentially form a floating gate polysilicon layer and a polysilicon isolation dielectric layer on the substrate; form a hard mask layer on the polysilicon isolation dielectric layer, and etch the hard mask layer to form trenches in the hard mask layer;
[0023] Step 2: Form a control gate polysilicon sidewall on the sidewall of the trench;
[0024] Step 3: Sequentially form a first sidewall dielectric layer and a second sidewall dielectric layer on the control gate polysilicon sidewall, and perform anisotropic etching on the second sidewall dielectric layer to form the second dielectric sidewall.
[0025] Step 4: Using the second dielectric sidewall and the hard mask layer as a mask, etch the exposed portion of the first sidewall dielectric layer and a portion of the control gate polysilicon sidewall;
[0026] Step 5: Using the second dielectric sidewall and the etched control gate polysilicon sidewall as a mask, perform self-aligned etching on the floating gate polysilicon layer;
[0027] Step 6: Formation of a tunneling oxide layer;
[0028] Step 7: Deposit a polysilicon layer for word lines, etch the polysilicon layer for word lines to form word lines, and thermally oxidize the word lines;
[0029] Step 8: Remove the hard mask layer and the underlying stack to define the memory cell, and form the final sidewalls on the memory cell; and
[0030] Step 9: Remove the oxide from the top surface of the polysilicon sidewall of the control gate and form a metal silicide layer on the exposed top surface of the polysilicon sidewall of the control gate.
[0031] Preferably, in step three, the first sidewall dielectric layer is a first sidewall silicon oxide layer.
[0032] Preferably, in step three, the second sidewall dielectric layer is a sidewall silicon nitride layer.
[0033] Preferably, in step one, the step of sequentially forming a floating gate polysilicon layer on the substrate includes: forming a coupling oxide layer on the substrate, and forming the floating gate polysilicon layer on the coupling oxide layer.
[0034] Preferably, after step four and before step five, the method further includes the step of forming a second sidewall silicon oxide layer on the etched surface of the control gate polysilicon sidewall to protect the control gate polysilicon sidewall.
[0035] Preferably, in step three, the step of forming the first sidewall dielectric layer is achieved by rapid thermal oxidation; and / or, in the step of forming the second sidewall silicon oxide layer, it is achieved by rapid thermal oxidation.
[0036] Preferably, after step five and before step six, a step of pulling back the second dielectric sidewall is included to form a wiped-off sharp corner.
[0037] Preferably, in step seven, after etching the polysilicon layer of the word lines, the step further includes etching back the word lines.
[0038] Preferably, the polycrystalline silicon isolation dielectric layer has an oxide-nitride-oxide structure.
[0039] Preferably, in step two, the step of forming the control gate polysilicon sidewall includes etching back the deposited control gate polysilicon layer, wherein the etching back stops at the nitride layer in the oxide-nitride-oxide structure.
[0040] Preferably, step nine further includes removing the oxide on the top surface of the word line by dry etching or wet etching, and forming a metal silicide layer on the exposed top surface of the word line.
[0041] As described above, the self-aligned stacked gate NORD flash memory structure and its manufacturing method of the present invention have the following beneficial effects:
[0042] This application uses the control gate polysilicon itself as a sidewall mask to perform self-aligned etching of the floating gate. This self-aligned process avoids the additional photolithography steps introduced to define the floating gate, which not only simplifies the overall manufacturing process and reduces production costs, but also fundamentally eliminates photolithography overlay errors, significantly improving the alignment accuracy and integration of the device.
[0043] This application effectively reduces the overall resistance of the control gate interconnect by forming a low-resistivity metal silicide layer above the top surface of the polysilicon sidewall of the control gate, which serves as the control gate. This directly reduces the RC delay effect on the signal transmission path, thereby significantly improving the read speed of NORD flash memory and meeting the requirements of high-performance applications. Attached Figure Description
[0044] Figure 1 The diagram shown is a schematic flow chart of a manufacturing method according to an embodiment of this application.
[0045] Figure 2 The diagram shown is a structural schematic of an embodiment of this application after the formation of a floating gate polysilicon layer and a polysilicon isolation dielectric layer;
[0046] Figure 3 The diagram shown is a structural schematic of an embodiment of this application after a hard mask layer has been formed and etched to form a trench.
[0047] Figure 4 The diagram shown is a structural schematic of a control gate polysilicon sidewall after it has been formed, according to an embodiment of this application.
[0048] Figure 5 The diagram shown is a structural schematic of an embodiment of this application after the first and second sidewall dielectric layers are sequentially formed.
[0049] Figure 6 The diagram shown is a structural schematic of an embodiment of this application after the formation of the second dielectric sidewall;
[0050] Figure 7 This is a schematic diagram of the structure behind the first sidewall dielectric layer and the control gate polysilicon sidewall in an etched portion, according to an embodiment of this application.
[0051] Figure 8 The diagram shown is a schematic representation of the structure of the control gate polysilicon sidewall after protective oxidation, according to an embodiment of this application.
[0052] Figure 9 This is a schematic diagram of the structure after self-aligned etching of the floating gate polysilicon layer according to an embodiment of this application;
[0053] Figure 10 The diagram shown is a schematic representation of the structure after the sharp corners have been erased, according to an embodiment of this application.
[0054] Figure 11 The diagram shown is a structural schematic of the polysilicon layer behind the deposited word lines, according to an embodiment of this application.
[0055] Figure 12 The diagram shown is a structural schematic of an embodiment of this application after the word lines have been formed and thermally oxidized.
[0056] Figure 13 The diagram shown is a schematic representation of the final self-aligned stacked gate NORD flash memory structure according to an embodiment of this application. Detailed Implementation
[0057] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0058] Please see Figure 13 This application provides a self-aligned stacked gate NORD flash memory structure, comprising:
[0059] Please see Figure 13 This application provides a self-aligned stacked gate NORD flash memory structure, comprising:
[0060] Substrate 101;
[0061] A floating gate 103 is disposed on a substrate 101 and is made of floating gate polysilicon;
[0062] A control gate polysilicon sidewall 106, which serves as the control gate of the structure, is located above the floating gate 103, wherein the inner sidewall of the control gate polysilicon sidewall 106 defines one sidewall of the floating gate 103, thereby forming a self-aligned structure.
[0063] The device comprises word lines 111, which are made of word line polysilicon; and a metal silicide layer 114, which is disposed on the top surface of the control gate polysilicon sidewall 106. By designing the control gate as a self-aligned sidewall structure and ultimately forming a low-resistance metal silicide layer 114 on top of it, the core objective of this application is to significantly reduce the line resistance of the control gate, thereby reducing the RC delay effect in read operations and ultimately achieving a significant improvement in the read speed of NORD flash memory.
[0064] In some embodiments, the top surface of the control gate polysilicon sidewall 106 has a predetermined height, and the top surface of the word line 111 has another predetermined height, wherein the height of the top surface of the control gate polysilicon sidewall 106 is higher than the height of the top surface of the word line 111. This height difference, formed through a specific process, provides a critical process window for the subsequent selective removal of the oxide on top of the control gate and metallization, effectively avoiding unnecessary etching damage or bridging short circuits to the word line 111 during silaneization, thereby improving process stability and device reliability.
[0065] In some embodiments, a metal silicide layer 114 is also included on the top surface of the word line 111. By synchronously metallizing the top of the word line 111, the line resistance of the word line 111 can be reduced, further improving the overall access speed and signal transmission efficiency of the memory array, and providing support for high-performance applications.
[0066] In some embodiments, the system further includes: a coupling oxide layer 102 disposed between the substrate 101 and the floating gate 103; a polysilicon isolation dielectric layer 104 disposed on the floating gate 103; and a tunneling oxide layer 110 disposed between the sidewall of the floating gate 103 and the channel region.
[0067] In some embodiments, the polysilicon isolation dielectric layer 104 is an oxide-nitride-oxide (ONO) structure. Using a classic ONO stacked structure as the polysilicon isolation dielectric layer 104 provides excellent charge retention characteristics and high reliability, ensuring stable operation of the flash memory cells after multiple read / write cycles.
[0068] In some embodiments, a final sidewall 113 is also included, which is disposed on the sidewall of the memory cell formed by the floating gate 103, the control gate polysilicon sidewall 106, and the word line 111. The formation of the final sidewall 113 provides effective electrical isolation between memory cells, prevents crosstalk between cells, and ensures the normal function of the device and stable operation under high integration.
[0069] In some embodiments, a first sidewall dielectric layer 107 and a second sidewall dielectric layer 108 are also formed between the tunneling oxide layer 110 and the inner sidewall of the control gate polysilicon sidewall 106. These two dielectric layers are key functional layers used for pattern transfer and structural protection during the manufacturing process, and their final residual morphology further ensures the insulation performance between the functional regions.
[0070] In some embodiments, the first sidewall dielectric layer 107 is a first sidewall silicon oxide layer.
[0071] In some embodiments, the second sidewall dielectric layer 108 is a sidewall silicon nitride layer.
[0072] Please see Figure 1 This application also provides a method for manufacturing a self-aligned stacked gate NORD flash memory structure, comprising:
[0073] Step 1: Sequentially form a floating gate polysilicon layer 103 and a polysilicon isolation dielectric layer 104 on the substrate 101 to form... Figure 2 The structure shown; a hard mask layer 105 is formed on the polysilicon isolation dielectric layer 104, and the hard mask layer 105 is etched to form trenches in the hard mask layer 105, forming a structure as shown. Figure 3 The structure shown.
[0074] In some embodiments, the step of sequentially forming a floating gate polysilicon layer 103 on the substrate 101 in step one includes: forming a coupling oxide layer 102 on the substrate 101, and forming a floating gate polysilicon layer 103 on the coupling oxide layer 102.
[0075] In some embodiments, the polysilicon isolation dielectric layer 104 has an oxide-nitride-oxide structure. This structure is a preferred option for achieving high-reliability charge storage.
[0076] Step 2: Form a control gate polysilicon sidewall 106 on the sidewall of the trench, forming a structure as shown in the image. Figure 4 The structure shown is shown. This step is one of the core aspects of this invention, innovatively using polysilicon with conductive control gates as sidewall masks for subsequent processes, rather than traditional insulating dielectric sidewalls, thus laying the structural foundation for subsequent self-alignment and top-side silicide formation.
[0077] In some embodiments, the step of forming the control gate polysilicon sidewall 106 in step two includes etching back the deposited control gate polysilicon layer, stopping at the nitride layer in the oxide-nitride-oxide structure that serves as the polysilicon isolation dielectric layer 104. Using the nitride layer as a precise etch stop layer can greatly improve the controllability and uniformity of the process, effectively preventing damage to the underlying functional layers, thereby ensuring the electrical performance and yield of the device.
[0078] Step 3: Sequentially form a first sidewall dielectric layer 107 and a second sidewall dielectric layer 108 on the polysilicon sidewall 106 of the control gate, forming as shown in the figure. Figure 5 The structure shown is used, and the second sidewall dielectric layer 108 is anisotropically etched to form the second dielectric sidewall, forming as shown. Figure 6 The structure shown.
[0079] In some embodiments, the first sidewall dielectric layer 107 in step three is a first sidewall silicon oxide layer.
[0080] In some embodiments, the second sidewall dielectric layer 108 in step three is a sidewall silicon nitride layer. Silicon nitride is chosen as the second dielectric sidewall material because of its high etch selectivity with the silicon oxide dielectric layer to be etched subsequently. This is crucial in the etching process of step four, ensuring accurate pattern transfer and protection of the underlying structure.
[0081] Step 4: Using the second dielectric sidewall and hard mask layer 105 as a mask, etch the exposed portion of the first sidewall dielectric layer 107 and a portion of the control gate polysilicon sidewall 106 to form a shape as shown in the image. Figure 7 The structure shown. This step precisely reduces the size of the control gate polysilicon sidewall 106 and shapes the basic profile required for subsequent formation of the word line 111.
[0082] In some embodiments, after step four and before step five, a step of forming a second sidewall silicon oxide layer 109 on the etched surface of the control gate polysilicon sidewall 106 is further included to protect the control gate polysilicon sidewall 106 and form a layer as shown in the figure. Figure 8 The structure shown is an example of this process. This oxidation step coats the exposed polysilicon sidewalls of the control gate, preventing them from being damaged or contaminated during subsequent complex etching and cleaning processes. This is crucial for ensuring the electrical characteristics of the final device.
[0083] In some embodiments, the step of forming the first sidewall dielectric layer 107 in step three is achieved by rapid thermal oxidation; and / or, the step of forming the second sidewall silicon oxide layer 109 is achieved by rapid thermal oxidation. The rapid thermal oxidation (RTO) process can form a dense and high-quality thin oxide layer while controlling the thermal budget, avoiding adverse effects on existing device structures.
[0084] Step 5: Using the second dielectric sidewall and the etched control gate polysilicon sidewall 106 as a mask, perform self-aligned etching on the floating gate polysilicon layer 103 to form a layer as shown in the image. Figure 9 The structure shown is a key step in realizing a self-aligned structure. By using the control gate sidewalls formed in situ as a mask, no additional photolithography process is required, which greatly simplifies the process flow, reduces manufacturing costs, and improves the integration and alignment accuracy of the device.
[0085] In some embodiments, after step five and before step six, a step of pulling back the second dielectric sidewall is included to form an erased sharp corner, forming as shown in the figure. Figure 10 The structure shown is an example of how the pull-back process can precisely form erase sharps to enhance the tunneling effect, thereby improving the erase efficiency and speed of flash memory cells.
[0086] Step 6: Form the tunnel oxide layer 110.
[0087] Step 7: Deposit the polycrystalline silicon layer 111 for the word lines, forming a shape like... Figure 11 The structure shown involves etching the polysilicon layer 111 of the word lines to form the word lines 111, and then thermally oxidizing the word lines 111. The thermal oxidation step forms a protective oxide layer 112 on the surface of the word lines 111, creating a structure as shown. Figure 12 The structure shown is used for isolation in subsequent processes.
[0088] In some embodiments, after etching the word line polysilicon layer 111 in step seven, a step of etching back the word line 111 is also included. The etch-back process can further optimize the contour of the word line 111 and ensure that the aforementioned height difference is formed between it and the control gate polysilicon sidewall 106, creating favorable conditions for final self-aligned siliconization.
[0089] Step 8: Remove the hard mask layer 105 and the stack below it to define the memory cell, and form the final sidewall 113 on the memory cell.
[0090] In some embodiments, the final sidewall 113 is an oxide-nitride-oxide (ONO) sidewall.
[0091] Step 9: Remove the oxide on the top surface of the control gate polysilicon sidewall 106 by dry etching or wet etching, and form a metal silicide layer 114 on the exposed top surface of the control gate polysilicon sidewall 106, forming a layer such as... Figure 13The structure shown illustrates how a precise oxide removal process exposes the pristine polysilicon top surface of the control gate, allowing it to undergo a uniform and thorough chemical reaction with subsequently deposited metals (such as tungsten, cobalt, or titanium) to form a low-sheet-resistance metal silicide. This metal silicide layer 114 significantly reduces the RC delay of the control gate, thereby substantially improving the read speed of the NORD flash memory and meeting the demands of high-performance applications.
[0092] In some embodiments, step nine further includes removing the oxide on the top surface of the word line 111 by dry etching or wet etching, and forming a metal silicide layer 114 on the exposed top surface of the word line 111.
[0093] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0094] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A self-aligned stacked gate NORD flash memory structure, characterized in that, include: Substrate; A floating gate, wherein the floating gate is disposed on the substrate and is made of floating gate polysilicon; A control gate polysilicon sidewall, which serves as the control gate of the structure and is located above the floating gate, wherein the inner sidewall of the control gate polysilicon sidewall defines one sidewall of the floating gate, thereby forming a self-aligned structure; Word lines, said word lines being made of word line polysilicon; and A metal silicide layer is disposed on the top surface of the polysilicon sidewall of the control gate.
2. The self-aligned stacked gate NORD flash memory structure according to claim 1, characterized in that: The top surface of the control gate polysilicon sidewall has a predetermined height, and the top surface of the word line has another predetermined height, wherein the height of the top surface of the control gate polysilicon sidewall is higher than the height of the top surface of the word line.
3. The self-aligned stacked gate NORD flash memory structure according to claim 1 or 2, characterized in that: It also includes a metal silicide layer disposed on the top surface of the word line.
4. The self-aligned stacked gate NORD flash memory structure according to claim 1, characterized in that: Also includes: A coupling oxide layer is disposed between the substrate and the floating gate; A polycrystalline silicon isolation dielectric layer is disposed above the floating gate; And a tunneling oxide layer, disposed between the sidewall of the floating grid and the channel area.
5. The self-aligned stacked gate NORD flash memory structure according to claim 1, characterized in that: The polycrystalline silicon isolation dielectric layer has an oxide-nitride-oxide structure.
6. The self-aligned stacked gate NORD flash memory structure according to claim 1, characterized in that: It also includes a final sidewall, which is disposed on the sidewall of the memory cell formed by the floating gate, the control gate polysilicon sidewall and the word line.
7. The self-aligned stacked gate NORD flash memory structure according to claim 4, characterized in that: A first sidewall dielectric layer and a second sidewall dielectric layer are also formed between the tunneling oxide layer and the inner sidewall of the control gate polysilicon sidewall.
8. The self-aligned stacked gate NORD flash memory structure according to claim 7, characterized in that: The first sidewall dielectric layer is a first sidewall silicon oxide layer.
9. The self-aligned stacked gate NORD flash memory structure according to claim 7, characterized in that: The second sidewall dielectric layer is a sidewall silicon nitride layer.
10. A method for manufacturing a self-aligned stacked gate NORD flash memory structure, characterized in that, include: Step 1: Sequentially form a floating gate polysilicon layer and a polysilicon isolation dielectric layer on the substrate; A hard mask layer is formed on the polysilicon isolation dielectric layer, and the hard mask layer is etched to form trenches in the hard mask layer; Step 2: Form a control gate polysilicon sidewall on the sidewall of the trench; Step 3: Sequentially form a first sidewall dielectric layer and a second sidewall dielectric layer on the control gate polysilicon sidewall, and perform anisotropic etching on the second sidewall dielectric layer to form the second dielectric sidewall. Step 4: Using the second dielectric sidewall and the hard mask layer as a mask, etch the exposed portion of the first sidewall dielectric layer and a portion of the control gate polysilicon sidewall; Step 5: Using the second dielectric sidewall and the etched control gate polysilicon sidewall as a mask, perform self-aligned etching on the floating gate polysilicon layer; Step 6: Formation of a tunneling oxide layer; Step 7: Deposit a polysilicon layer for word lines, etch the polysilicon layer for word lines to form word lines, and thermally oxidize the word lines; Step 8: Remove the hard mask layer and the stack below it to define the memory cell, and form the final sidewall on the memory cell; as well as Step 9: Remove the oxide from the top surface of the polysilicon sidewall of the control gate and form a metal silicide layer on the exposed top surface of the polysilicon sidewall of the control gate.
11. The method for manufacturing a self-aligned stacked gate NORD flash memory structure according to claim 10, characterized in that: In step three, the first sidewall dielectric layer is a first sidewall silicon oxide layer.
12. The method for manufacturing a self-aligned stacked gate NORD flash memory structure according to claim 10, characterized in that: In step three, the second sidewall dielectric layer is a sidewall silicon nitride layer.
13. The method for manufacturing a self-aligned stacked gate NORD flash memory structure according to claim 10, characterized in that: In step one, the step of sequentially forming a floating gate polysilicon layer on the substrate includes: forming a coupling oxide layer on the substrate, and forming the floating gate polysilicon layer on the coupling oxide layer.
14. The method for manufacturing a self-aligned stacked gate NORD flash memory structure according to claim 10, characterized in that: After step four and before step five, the process also includes forming a second sidewall silicon oxide layer on the etched surface of the control gate polysilicon sidewall to protect the control gate polysilicon sidewall.
15. The method for manufacturing a self-aligned stacked gate NORD flash memory structure according to claim 14, characterized in that: In step three, the step of forming the first sidewall dielectric layer is achieved by rapid thermal oxidation; and / or, in the step of forming the second sidewall silicon oxide layer, it is achieved by rapid thermal oxidation.
16. The method for manufacturing a self-aligned stacked gate NORD flash memory structure according to claim 1, characterized in that: After step five and before step six, there is also a step of pulling back the second dielectric sidewall to form a wiped-off corner.
17. The method for manufacturing a self-aligned stacked gate NORD flash memory structure according to claim 1, characterized in that: In step seven, after etching the polysilicon layer of the word lines, the step of re-etching the word lines is also included.
18. The method for manufacturing a self-aligned stacked gate NORD flash memory structure according to claim 1, characterized in that: The polycrystalline silicon isolation dielectric layer has an oxide-nitride-oxide structure.
19. The method for manufacturing a self-aligned stacked gate NORD flash memory structure according to claim 1, characterized in that: In step two, the step of forming the control gate polysilicon sidewall includes etching back the deposited control gate polysilicon layer, wherein the etching back stops at the nitride layer in the oxide-nitride-oxide structure.
20. The method for manufacturing a self-aligned stacked gate NORD flash memory structure according to claim 1, characterized in that: Step nine further includes removing the oxide on the top surface of the word line by dry etching or wet etching, and forming a metal silicide layer on the exposed top surface of the word line.