Preparation method of IGBT (Insulated Gate Bipolar Translator) device

Abstract

The invention discloses a preparation method of an IGBT device. The IGBT device comprises a substrate, an interlayer dielectric layer, a metal barrier layer, a metal layer, a first passivation layer, a second passivation layer, an alloy processing substrate and a semiconductor device area. The stress in the semiconductor device is released through alloying treatment after photoetching, the problem that the stress of a boron-free phosphorosilicate glass IGBT device is too large in the related technology is solved, due to the fact that the stress is reduced, the channel opening of the IGBT device is more sufficient under the low opening voltage, the problem that the saturation voltage drop of a collector and an emitter is discrete is effectively solved, and the reliability of the IGBT device is improved. The stability and the consistency of the IGBT device are improved, and the performance and the reliability of the whole circuit can be improved; the passivation layer is changed from a single silicon-rich silicon nitride layer to the combined film layer of the silicon nitride layer and the silicon-rich silicon nitride layer, so that the problem of small black spots in the subsequent newly-added alloying treatment process is avoided, the structure of the combined film layer is more stable, and the durability and reliability of the device are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a method for fabricating an IGBT device. Background Technology

[0002] An insulated gate bipolar transistor (IGBT) is a power semiconductor device that combines the high input impedance of a metal-oxide-semiconductor field-effect transistor with the high conduction capability of a bipolar transistor, and is widely used in power electronic systems.

[0003] like Figure 1 As shown, compared to 8-inch products, current 12-inch IGBT products generally share production lines with power devices and IC products in wafer fabrication plants. IGBT devices manufactured on 12-inch wafers cannot use silicon phosphide glass (PSG) or borophosphosilicate glass (BPSG). Since borophosphosilicate glass is unavailable, a thinner layer of silicon nitride (SIN) is grown at the bottom of the interlayer dielectric (ILD) layer to improve the reliability of various product parameters.

[0004] However, due to the inherent characteristics of SIN, it is easy to cause an increase in internal stress in the wafer. After aluminum deposition, the stress problem is further aggravated, which ultimately leads to insufficient channel opening of the IGBT at low turn-on voltage and dispersion of the collector-emitter saturation voltage drop Vcesat parameter. This dispersion will affect key parameters such as the switching characteristics, power consumption and efficiency of the IGBT. Summary of the Invention

[0005] This application provides a method for fabricating an IGBT device, which can solve the problem of excessive stress caused by omitting the BPSG in related technologies.

[0006] On one hand, embodiments of this application provide a method for fabricating an IGBT device, including: A substrate is provided, wherein an interlayer dielectric layer, a metal barrier layer and a metal layer are sequentially coated on the substrate; A first passivation layer is formed, which covers the metal layer; A second passivation layer is formed, which covers the first passivation layer; Photoresist is coated on the surface of the second passivation layer, and a preset pattern is formed on the photoresist; Using patterned photoresist as a mask, etching is stopped at the surface of the metal layer to remove part of the first passivation layer and the second passivation layer; Remove the patterned photoresist; The first passivation layer, the second passivation layer, the metal layer, the metal barrier layer, the interlayer dielectric layer, and the substrate after alloying treatment and etching.

[0007] In some embodiments, the first passivation layer includes a silicon nitride layer.

[0008] In some embodiments, the thickness of the first passivation layer is 500 angstroms to 2000 angstroms.

[0009] In some embodiments, the second passivation layer comprises a silicon-rich silicon nitride layer.

[0010] In some embodiments, the thickness of the second passivation layer is 8,000 to 15,000 angstroms.

[0011] In some embodiments, the processing temperature in the step of alloying the etched first passivation layer, second passivation layer, metal layer, metal barrier layer, interlayer dielectric layer and substrate is 350 degrees Celsius to 450 degrees Celsius.

[0012] In some embodiments, the alloying treatment time in the step of alloying the etched first passivation layer, second passivation layer, metal layer, metal barrier layer, interlayer dielectric layer and substrate is 15 minutes to 60 minutes.

[0013] In some embodiments, the gas used in the step of alloying the etched first passivation layer, second passivation layer, metal layer, metal barrier layer, interlayer dielectric layer, and substrate includes hydrogen and / or nitrogen.

[0014] In some embodiments, the interlayer dielectric layer includes a silicon dioxide layer and a silicon nitride layer; the silicon nitride layer is disposed between the silicon dioxide layer and the substrate.

[0015] The technical solution of this application has at least the following advantages: By releasing the internal stress of semiconductor devices through alloying after photolithography and etching, the problem of excessive stress in boron-free silicon phosphosilicate glass (BPSG) IGBT devices in related technologies is solved. Due to the reduction in stress, the IGBT device can turn on the channel more fully at low turn-on voltage, effectively solving the problem of collector-emitter saturation voltage drop dispersion, improving the stability and consistency of the IGBT device, and contributing to the improvement of the overall circuit performance and reliability. The passivation layer is changed from a single silicon-rich silicon nitride layer to a combination film of silicon nitride layer + silicon-rich silicon nitride layer, avoiding the small black spot problem in the subsequent alloying process. At the same time, the combined film structure is more stable, improving the durability and reliability of the device. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a comparison of scanning electron microscope images of 8-inch and 12-inch IGBT devices in related technologies; Figure 2 This is a flowchart of an exemplary embodiment of the improved method provided in this application; Figure 3 This is a cross-sectional view of an IGBT device substrate and its semiconductor device structure provided in an exemplary embodiment of this application; Figure 4 This is a cross-sectional view of the structure after the formation of the first passivation layer, provided in an exemplary embodiment of this application; Figure 5 This is a cross-sectional view of the structure after the formation of the second passivation layer, provided in an exemplary embodiment of this application; Figure 6 This is a cross-sectional view of the structure after a preset pattern has been formed by coating with photoresist, provided in an exemplary embodiment of this application; Figure 7 This is a cross-sectional view of the structure etched using a preset pattern as a mask, provided in an exemplary embodiment of this application. Figure 8 This is a cross-sectional view of the etched first passivation layer and second passivation layer provided in an exemplary embodiment of this application; Figure 9 This is a scanned image from an automatic visual inspection instrument that produces small black dots by alloying a silicon-rich silicon nitride layer that directly contacts the metal in the barrier layer of a related technology. Figure 10 This is a scanned image of an automatic visual inspection instrument that has undergone alloying treatment after combining a first passivation layer and a second passivation layer, as provided in an exemplary embodiment of this application. Figure 11 It is a wafer testing pattern for wafers in related technologies; Figure 12 This is a wafer test pattern of a wafer provided in an exemplary embodiment of this application. Detailed Implementation

[0018] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0020] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0021] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0022] refer to Figure 2 It presents a flowchart of an improved method provided by an exemplary embodiment of this application, such as... Figure 2 As shown, it includes: Step S101: Provide a substrate, on which an interlayer dielectric layer, a metal barrier layer and a metal layer are sequentially coated.

[0023] Optionally, the interlayer dielectric layer includes a silicon dioxide layer and a silicon nitride layer; the silicon nitride layer is disposed between the silicon dioxide layer and the substrate. Furthermore, it is worth noting that the interlayer dielectric layer does not include borosilicate glass (BPSG).

[0024] refer to Figure 3 It presents a cross-sectional view of an IGBT device substrate and its semiconductor device structure provided in an exemplary embodiment of this application, such as... Figure 3 As shown, it includes: For example, a substrate 201 is provided, on which a semiconductor structure (not shown) fabricated using conventional front-end and mid-end processes for IGBT devices is formed. An interlayer dielectric (ILD) 202 is covered on the substrate 201 near the semiconductor structure. The interlayer dielectric 202 is filled with a combination of a silicon dioxide layer and a silicon nitride layer, with the silicon nitride layer serving as the bottom layer of the interlayer dielectric 202 between the silicon dioxide layer and the substrate. Figure 3 (Not shown in the image) The silicon nitride layer, as the bottom layer, can improve the overall stability and reliability. There is no BPSG layer in the entire interlayer dielectric layer 202. A groove is formed in the middle of the interlayer dielectric layer 202, which extends into the well region of the substrate. A metal barrier layer 203 is covered on the surface of the interlayer dielectric layer 202 and the surface of the groove. The filling material of the metal barrier layer 203 is titanium (Ti) or titanium nitride (TiN) to prevent metal diffusion from the metal layer 204 on the surface of the metal barrier layer 203 and contamination of the substrate, while reducing the resistance. The surface of the metal barrier layer 203 is covered with a metal layer 204, and the metal filled in the metal layer 204 can be aluminum (Al).

[0025] Step S102: Form a first passivation layer, which covers the metal layer.

[0026] Optionally, the first passivation layer includes a silicon nitride layer.

[0027] The thickness of the first passivation layer is 500 to 2000 angstroms.

[0028] refer to Figure 4 It presents a cross-sectional view of the structure after the formation of the first passivation layer provided in an exemplary embodiment of this application, such as... Figure 4 As shown, it includes: For example, a 1200 angstrom silicon nitride layer is formed and covered on the surface of metal layer 204 as a first passivation layer 205.

[0029] Step S103: Form a second passivation layer, which covers the first passivation layer.

[0030] Optionally, the second passivation layer includes a silicon-rich silicon nitride layer.

[0031] The thickness of the second passivation layer is 8,000 to 15,000 angstroms.

[0032] refer to Figure 5 It presents a cross-sectional view of the structure after the formation of the second passivation layer provided in an exemplary embodiment of this application, such as... Figure 5 As shown, it includes: For example, a second passivation layer 206 is covered on the surface of the first passivation layer 205. The second passivation layer 206 includes a silicon-rich silicon nitride layer with a thickness of 10,000 angstroms.

[0033] Step S104: Coat the surface of the second passivation layer with photoresist to form a preset pattern on the photoresist.

[0034] refer to Figure 6 It presents a cross-sectional view of the structure after a preset pattern is formed by coating photoresist according to an exemplary embodiment of this application, such as... Figure 6 As shown, it includes: For example, photoresist 207 is coated on the surface of the second passivation layer 206, and after exposure and development, part of the photoresist 207 is removed to form a preset pattern.

[0035] Step S105: Using patterned photoresist as a mask, etch until the surface of the metal layer stops, removing part of the first passivation layer and the second passivation layer.

[0036] refer to Figure 7 It presents a cross-sectional view of the structure etched using a preset pattern as a mask, as provided in an exemplary embodiment of this application, such as... Figure 7 As shown, it includes: For example, using patterned photoresist 207 as a mask, the second passivation layer 206 and the first passivation layer 205 are etched downwards to the surface of the metal layer 204, and the areas of the second passivation layer 206 and the first passivation layer 205 not covered by the photoresist 207 are removed.

[0037] Step S106: Remove the patterned photoresist.

[0038] refer to Figure 8 It presents a cross-sectional view of the etched first passivation layer and second passivation layer provided in an exemplary embodiment of this application, as shown below. Figure 8 As shown, it includes: For example, a groove is formed by etching, retaining the first passivation layer 205 and the second passivation layer 206 on both sides, and the photoresist 207 is removed after etching is completed.

[0039] Step S107: Alloying treatment of the etched first passivation layer, second passivation layer, metal layer, metal barrier layer, interlayer dielectric layer and substrate.

[0040] Optionally, the processing temperature in the alloying process for the etched first passivation layer, second passivation layer, metal layer, metal barrier layer, interlayer dielectric layer, and substrate is 350 degrees Celsius to 450 degrees Celsius.

[0041] Optionally, the alloying process in the steps of alloying the first passivation layer, the second passivation layer, the metal layer, the metal barrier layer, the interlayer dielectric layer and the substrate after etching is 15 minutes to 60 minutes.

[0042] Optionally, the gas used in the alloying process for the etched first passivation layer, second passivation layer, metal layer, metal barrier layer, interlayer dielectric layer, and substrate may include hydrogen and / or nitrogen.

[0043] For example, after etching, the substrate and the first passivation layer, second passivation layer, metal layer, metal barrier layer and interlayer dielectric layer on the substrate surface are alloyed to release the stress accumulated between the interlayer dielectric layers. The alloying process uses a mixture of hydrogen and nitrogen gas, maintains a high temperature of 450 degrees Celsius, and continues for 45 minutes until the stress is completely released. After the stress is completely released, the channel is fully opened under low voltage, and no discrete phenomenon of collector-emitter saturation voltage drop (Vcesat) parameter is generated.

[0044] refer to Figure 9 They presented scanned images from an Automated Visual Inspection (AVI) instrument showing small black dots generated by alloying a silicon-rich silicon nitride layer directly contacting the metal as the barrier layer in the relevant technology. (Example:) Figure 9 As shown, the small black dots generated in the boxed area are due to the relatively high silicon content in the silicon-rich silicon nitride layer. At high temperatures, it is easy to mix with the Al metal in the metal layer. After the Al metal penetrates into the silicon-rich silicon nitride layer, it forms aluminum nitride with nitrogen, resulting in the appearance of small black dots.

[0045] refer to Figure 10 The document presents a scanned image of an automated visual inspection instrument employing an alloying treatment combining a first passivation layer and a second passivation layer, as provided in an exemplary embodiment of this application. Figure 10 As shown, in this application, the first passivation layer silicon nitride layer is combined with the silicon-rich silicon nitride layer, so that the metal layer 204 is in direct contact with the silicon nitride layer. The silicon nitride layer is relatively stable and will not produce black spots.

[0046] refer to Figure 11 and Figure 12 By comparing the chip probe (CP) spectra of wafers in related technologies with the chip probe spectra of wafers manufactured by the method provided in this application, it can be seen that in related technologies, due to the absence of borosilicate glass, the collector-emitter saturation voltage drop (Vcesat) parameter is relatively discrete. However, after the internal stress of the wafer is completely released by the method of this application, this phenomenon is greatly improved, and the discreteness of the collector-emitter saturation voltage drop (Vcesat) parameter no longer occurs.

[0047] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating an IGBT device, characterized in that, include: A substrate is provided, wherein an interlayer dielectric layer, a metal barrier layer and a metal layer are sequentially coated on the substrate; A first passivation layer is formed, which covers the metal layer; A second passivation layer is formed, which covers the first passivation layer; Photoresist is coated on the surface of the second passivation layer, and a preset pattern is formed on the photoresist by photolithography. Using patterned photoresist as a mask, etching is stopped at the surface of the metal layer to remove part of the first passivation layer and the second passivation layer; Remove the patterned photoresist; The first passivation layer, the second passivation layer, the metal layer, the metal barrier layer, the interlayer dielectric layer, and the substrate after alloying treatment and etching.

2. The method as described in claim 1, characterized in that, The first passivation layer includes a silicon nitride layer.

3. The method as described in claim 2, characterized in that, The thickness of the first passivation layer is 500 to 2000 angstroms.

4. The method as described in claim 1, characterized in that, The second passivation layer includes a silicon-rich silicon nitride layer.

5. The method as described in claim 4, characterized in that, The thickness of the second passivation layer is 8,000 to 15,000 angstroms.

6. The method as described in claim 1, characterized in that, The processing temperature in the steps of alloying the etched first passivation layer, second passivation layer, metal layer, metal barrier layer, interlayer dielectric layer and substrate is 350 degrees Celsius to 450 degrees Celsius.

7. The method as described in claim 1, characterized in that, The alloying process for the first passivation layer, second passivation layer, metal layer, metal barrier layer, interlayer dielectric layer and substrate after alloying treatment takes 15 to 60 minutes.

8. The method as described in claim 1, characterized in that, The gas used in the alloying process for etching the first passivation layer, the second passivation layer, the metal layer, the metal barrier layer, the interlayer dielectric layer, and the substrate includes hydrogen and / or nitrogen.

9. The method as described in claim 1, characterized in that, The interlayer dielectric layer includes a silicon dioxide layer and a silicon nitride layer; the silicon nitride layer is disposed between the silicon dioxide layer and the substrate.

Images