Formation method of semiconductor structure
By performing ion implantation and wet etching on the corner region of the FinFET, the problem of residual pseudo-gate material was solved, the gate morphology was improved, and the performance and reliability of the device were enhanced.
Patent Information
- Application Number
- CN202410566223.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-08
- Publication Date
- 2025-11-11
AI Technical Summary
In existing FinFET technology, the formation method of FinFET field-effect transistors leads to the residue of dummy gate material, which affects the control capability and performance of the device, especially at the nanoscale.
The morphology of the pseudo gate sidewall is improved by ion implantation to form a modified layer in the corner region and wet etching to remove the modified layer. At the same time, the ion implantation energy and direction are controlled to reduce the impact on the host region, and an appropriate etching selectivity is selected to reduce substrate damage.
This improved the gate morphology and device performance, reduced etching damage, optimized the morphology of the dummy gate, and enhanced the overall device performance.
Smart Images
Figure CN120936054A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology
[0002] In the existing semiconductor field, the FinFET is an emerging multi-gate device. Compared with the planar metal-oxide-semiconductor field-effect transistor (MOSFET), the FinFET has stronger short-channel rejection capability and higher operating current, and is now widely used in various semiconductor devices.
[0003] With the continuous development of semiconductor technology, integrated circuits are constantly being "scaled down." When the size of semiconductor devices shrinks to the nanometer level, especially for FinFETs, their gate control capability is closely related to their physical size. The small geometric size and three-dimensional structure of FinFETs make the impact of process changes on the device increasingly severe, urgently requiring new methods for optimization. Existing methods for forming FinFET structures need improvement. Summary of the Invention
[0004] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.
[0005] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a base and a fin located on a portion of the base; forming a dummy gate spanning the fin, the dummy gate being located on a portion of the sidewall and top surface of the fin, the dummy gate including a main region and a corner region, the sidewall surface of the main region being perpendicular to the sidewall surface of the fin, and the corner region being located at a corner surface formed by the sidewall of the main region and the sidewall of the fin; modifying the corner region by an ion implantation process to form a modified layer; and removing the modified layer by a wet etching process.
[0006] Optionally, the process parameters of the ion implantation process include: implanted ions include N-type ions or P-type ions; implantation energy is less than or equal to 10 keV; and the angle between the implantation direction and the normal direction of the substrate is less than or equal to 5 degrees.
[0007] Optionally, the substrate further includes an isolation structure located on the substrate, the isolation structure being located on a portion of the fin sidewall, and the top of the isolation structure being lower than the top of the fin, and the dummy gate being located on a portion of the surface of the isolation structure.
[0008] Optionally, in the ion implantation process, ions are also implanted onto the fin surface and the isolation structure surface exposed by the dummy gate; the fin has a well region; and the conductivity type of the implanted ions is different from that of the well region.
[0009] Optionally, after removing the modified layer, the method further includes: forming a source region and a drain region in the fins on both sides of the dummy gate, respectively; after forming the source region and the drain region, forming an interlayer dielectric layer on the substrate, the source region and the drain region, the interlayer dielectric layer also being located on the sidewall of the dummy gate and exposing the top surface of the dummy gate; and replacing the dummy gate to form a gate.
[0010] Optionally, the gate material may include metal.
[0011] Optionally, the dummy gate is made of polycrystalline silicon; the modified layer is made of amorphous silicon.
[0012] Optionally, the process parameters of the wet etching process include: the etching solution includes a hydrofluoric acid solution, the volume ratio of hydrofluoric acid to water in the hydrofluoric acid solution is in the range of 100:1 to 1000:1, and the reaction temperature is in the range of 100℃ to 200℃.
[0013] Optionally, the method for modifying the corner region further includes: during the ion implantation process, the substrate is rotated around its central axis.
[0014] Optionally, the method for forming the modified layer further includes: performing a thermal annealing treatment on the modified layer after the modification treatment.
[0015] Optionally, the wet etching process has an etching selectivity ratio of 50:1 to 100:1 for the modified layer and the dummy gate.
[0016] Optionally, the wet etching process has an etching selectivity ratio of 50:1 to 100:1 for the modified layer and the fin.
[0017] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0018] In the semiconductor structure formation method provided by the present invention, the corner region is modified to form a modified layer, and the modified layer is removed by a wet etching process. This improves the morphology of the pseudo-gate sidewall, thereby improving the morphology of the gate and thus enhancing the device performance. In addition, in the wet etching process, the corner region is more likely to retain etching solution than other surfaces, which is more conducive to the removal of the corner region. Furthermore, wet etching, which has a large etching selectivity for the modified layer, causes less etching damage to the substrate compared to dry etching, further enhancing the device performance.
[0019] Furthermore, the process parameters of the ion implantation process include: implanted ions include N-type ions or P-type ions; implantation energy is less than or equal to 10 keV; the angle between the implantation direction and the normal direction of the substrate is less than or equal to 5 degrees. Controlling the implantation energy range can reduce damage to the substrate and make the angle between the implantation direction and the normal direction of the substrate smaller, which is beneficial to improve the etching of the corner area and reduce the impact on the sidewalls of the main area.
[0020] Furthermore, in the ion implantation process, ions are also implanted onto the fin surface and the isolation structure surface exposed by the dummy gate; the fin has a well region; the conductivity type of the implanted ions is different from that of the well region. The ions implanted at the interface between the isolation structure and the fin, due to their different conductivity type from the dopant ions in the well region, can prevent the diffusion of dopant ions from the well region into the device channel, thereby optimizing the dummy gate morphology while reducing the impact on channel performance. Attached Figure Description
[0021] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure.
[0022] Figures 3 to 8 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation
[0023] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.
[0024] As mentioned in the background section, the performance of semiconductor structures formed using existing FinFET technology urgently needs improvement. This section will now explain and analyze a method for forming a semiconductor structure.
[0025] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure.
[0026] Please refer to Figure 1 and Figure 2 , Figure 2 yes Figure 1A cross-sectional structural schematic diagram obtained along the dashed line shows a substrate, which includes a base 100, a fin 101 located on a portion of the base 100, an isolation structure 102 located on the base 100, the isolation structure 102 also located on a portion of the sidewall of the fin 101, and the top surface of the isolation structure 102 being lower than the top surface of the fin 101; a dummy gate oxide layer 103 located on the surface of the fin 101; and a dummy gate 104 spanning the fin 101, the dummy gate 104 located on a portion of the top surface and a portion of the sidewall surface of the fin 101, and located on a portion of the top surface of the isolation structure 102.
[0027] In the above structure, the dummy gate 104 occupies space for the gate and is subsequently replaced by the gate. The method for forming the dummy gate 104 includes: forming a dummy gate material layer (not shown in the figure) on the substrate, and patterning the dummy gate material layer until the substrate is exposed. Due to the influence of photolithography and the three-dimensional structure of the FinFET, dummy gate material residue is easily present near the corner formed by the interface of the dummy gate 104, the isolation structure 102, and the fin 101, forming a small dummy gate foot A. The presence of the dummy gate foot A reduces the gate's control over the device and may even cause device short circuits or other abnormalities, severely affecting device performance.
[0028] To address the aforementioned issues, this invention provides a method for forming a semiconductor structure in which the corner region is modified to form a modified layer. This modified layer is then removed using a wet etching process, improving the morphology of the dummy gate sidewalls and consequently enhancing the gate morphology, thus improving device performance. Furthermore, in the wet etching process, the corner region is more prone to retaining etching solution compared to other surfaces, facilitating the removal of the corner region. Moreover, selecting wet etching, which has a higher selectivity for the modified layer, results in less etching damage to the substrate compared to dry etching, further contributing to improved device performance.
[0029] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0030] Figures 3 to 8 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.
[0031] Please refer to Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the three-dimensional structure. Figure 4 for Figure 3 A cross-sectional structural schematic diagram along the DD1 direction is provided, the substrate including a base 200 and a fin 201 located on a portion of the base 200.
[0032] In this embodiment, the substrate further includes an isolation structure 202 located on the substrate 200. The isolation structure 202 is also located on a portion of the sidewall of the fin 201, and the top surface of the isolation structure 202 is lower than the top surface of the fin 201.
[0033] In this embodiment, the fin 201 has a trap region (not shown in the figure).
[0034] In this embodiment, the well region has a P-type conductivity and is used to form an NMOS. In another embodiment, the well region has an N-type conductivity and is used to form a PMOS.
[0035] In this embodiment, the material of the isolation structure 202 includes silicon oxide. The isolation structure 202 is used for electrical insulation between different devices.
[0036] The substrate 200 is made of materials including silicon carbide, silicon-germanium, multi-element semiconductor materials composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor materials composed of group III-V elements include InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP. In this embodiment, the substrate 200 is made of silicon.
[0037] In this embodiment, the fin 201 is made of silicon. In other embodiments, the fin may also be made of germanium-silicon, germanium, or other similar materials.
[0038] Please continue to refer to this. Figure 3 and Figure 4 A dummy gate 203 is formed across the fin 201. The dummy gate 203 is located on a portion of the sidewall and top surface of the fin 201. The dummy gate 203 includes a main region I and a corner region II. The sidewall surface of the main region I is perpendicular to the sidewall surface of the fin 201. The corner region II is located on the corner surface formed by the sidewall of the main region I and the sidewall of the fin 201.
[0039] In this embodiment, the dummy gate 203 is also located on the top surface of a portion of the isolation structure 202. The dummy gate 203 is used to occupy space for forming a gate.
[0040] In this embodiment, the dummy gate 203 is also located on a portion of the surface of the isolation structure 202.
[0041] In this embodiment, a pseudo gate oxide layer 204 is formed on the surface of the fin 201 before the pseudo gate 203 is formed.
[0042] In this embodiment, the material of the pseudo gate oxide layer 204 includes silicon oxide.
[0043] In this embodiment, the material of the dummy gate 203 includes polycrystalline silicon.
[0044] Please refer to Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the three-dimensional structure. Figure 6 for Figure 5 A cross-sectional structural diagram along the DD1 direction is shown. The corner region II is modified by ion implantation to form a modified layer 205.
[0045] In this embodiment, during the ion implantation process, ions are implanted onto the surface of the dummy gate 203, meaning the modified layer 205 is also formed on the sidewalls and top surface of the main region I. Since the corner region II is thinner than the main region I, the modification is more thorough. Furthermore, the ion implantation angle during the ion implantation process can be adjusted to maximize the modification of the corner region II while minimizing its impact on the main region I.
[0046] In this embodiment, the process parameters of the ion implantation process include: implanted ions include N-type ions or P-type ions; implantation energy is less than or equal to 10 keV; and the angle between the implantation direction and the normal direction of the substrate is less than or equal to 5 degrees.
[0047] The purpose of selecting N-type or P-type ions is to reduce the introduction of impurity ions into the channel due to the ion implantation process. The purpose of selecting the implantation energy range is to control the thickness of the modified material, ensuring that the corner region II is fully modified while reducing the thickness of other regions. The purpose of selecting a small-angle ion implantation is to allow most ions to be implanted into the corner region II, ensuring that the corner region II is fully modified while reducing the impact on other regions.
[0048] It should be noted that the channel refers to the fin 201 located between the source region and the drain region and wrapped by the gate.
[0049] In this embodiment, the method for modifying the corner region II further includes: during the ion implantation process, the substrate is rotated around its central axis. Rotational implantation during ion implantation helps improve the uniformity of ion implantation and ensures the uniformity of the modified layer 205 thickness.
[0050] In this embodiment, the method for forming the modified layer 205 further includes: performing a thermal annealing treatment on the modified layer after the modification treatment. The thermal annealing treatment is used to reduce the etching damage to the substrate and the dummy gate 203 caused by the ion implantation process.
[0051] In this embodiment, the material of the modified layer 205 includes amorphous silicon.
[0052] In this embodiment, during the ion implantation process, ions are also implanted onto the surface of the fin 201 exposed by the dummy gate 203 and the surface of the isolation structure 202.
[0053] The implanted ions have a different conductivity type than the well region. Since the ions implanted at the interface between the isolation structure 202 and the fin 201 have a different conductivity type than the dopant ions in the well region, they can prevent the diffusion of dopant ions from the well region into the device channel. This optimizes the pseudo-gate morphology while reducing the impact on channel performance.
[0054] In this embodiment, the implanted ions are of N-type conductivity. In another embodiment, the implanted ions are of P-type conductivity.
[0055] Please refer to Figure 7 and Figure 8 , Figure 7 This is a schematic diagram of the three-dimensional structure. Figure 8 for Figure 7 A cross-sectional view of the structure along the DD1 direction is shown, in which the modified layer 205 is removed using a wet etching process.
[0056] Thus, the modified layer 205 was removed using a wet etching process, which improved the morphology of the sidewalls of the dummy gate 203, thereby improving the gate morphology and enhancing device performance. In addition, in the wet etching process, the corner region II is more likely to retain etching solution than other surfaces, making it easier to remove the corner region II. Furthermore, wet etching, which has a higher etching selectivity for the modified layer 205, causes less etching damage to the substrate compared to dry etching, further improving device performance.
[0057] In this embodiment, the process parameters of the wet etching process include: the etching solution includes a hydrofluoric acid solution, the volume ratio of hydrofluoric acid to water in the hydrofluoric acid solution is in the range of 100:1 to 1000:1, and the reaction temperature is in the range of 100°C to 200°C.
[0058] The wet etching process has an etching selectivity ratio for the modified layer 205 and the dummy gate 203 ranging from 50:1 to 100:1. The purpose of selecting this etching selectivity ratio is to reduce the etching damage to the dummy gate 203 caused by the wet etching, which is beneficial to optimizing the morphology of the final gate.
[0059] The wet etching process has an etching selectivity ratio for the modified layer 205 and the fin 201 ranging from 50:1 to 100:1. The purpose of selecting this etching selectivity ratio is to reduce the etching damage to the fin 201 caused by the wet etching, thereby improving the performance of the final device.
[0060] Subsequently, after removing the modified layer 205, the process further includes: forming a source region and a drain region (not shown in the figure) in the fins 201 on both sides of the dummy gate 203; after forming the source region and the drain region, forming an interlayer dielectric layer (not shown in the figure) on the substrate, the source region and the drain region, the interlayer dielectric layer also being located on the sidewall of the dummy gate 203 and exposing the top surface of the dummy gate 203; and replacing the dummy gate 203 to form a gate.
[0061] In this embodiment, the method for replacing the dummy gate 203 to form the gate includes: removing the dummy gate 203; forming a gate trench (not shown in the figure) in the interlayer dielectric layer, wherein a portion of the fin 201 is exposed at the bottom of the gate trench; and forming a gate (not shown in the figure) in the gate trench.
[0062] In this embodiment, the material of the gate includes metal.
[0063] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a base and fins located on a portion of the base; A dummy gate is formed across the fin, the dummy gate being located on a portion of the sidewall and top surface of the fin, the dummy gate including a main region and a corner region, the sidewall surface of the main region being perpendicular to the sidewall surface of the fin, and the corner region being located on the corner surface formed by the sidewall of the main region and the sidewall of the fin; The corner region is modified by ion implantation to form a modified layer; The modified layer was removed using a wet etching process.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters of the ion implantation process include: implanted ions include N-type ions or P-type ions; implantation energy is less than or equal to 10 keV; and the angle between the implantation direction and the normal direction of the substrate is less than or equal to 5 degrees.
3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The substrate further includes an isolation structure located on the substrate, the isolation structure being located on a portion of the fin sidewall, and the top of the isolation structure being lower than the top of the fin, and the dummy gate being located on a portion of the surface of the isolation structure.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, In the ion implantation process, ions are also implanted onto the fin surface and the isolation structure surface exposed by the dummy gate; the fin has a well region; the conductivity type of the implanted ions is different from the conductivity type of the well region.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, After removing the modified layer, the method further includes: forming a source region and a drain region in the fins on both sides of the dummy gate, respectively; after forming the source region and the drain region, forming an interlayer dielectric layer on the substrate, the source region and the drain region, the interlayer dielectric layer also being located on the sidewall of the dummy gate and exposing the top surface of the dummy gate; and replacing the dummy gate to form a gate.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The gate is made of metal.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The dummy gate is made of polycrystalline silicon; the modified layer is made of amorphous silicon.
8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The process parameters of the wet etching process include: the etching solution includes a hydrofluoric acid solution, the volume ratio of hydrofluoric acid to water in the hydrofluoric acid solution is in the range of 100:1 to 1000:1, and the reaction temperature is in the range of 100℃ to 200℃.
9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for modifying the corner region further includes: during the ion implantation process, the substrate is rotated around its central axis.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the modified layer further includes: after the modification treatment, performing a thermal annealing treatment on the modified layer.
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The wet etching process has an etching selectivity ratio of 50:1 to 100:1 for the modified layer and the dummy gate.
12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The wet etching process has an etching selectivity ratio of 50:1 to 100:1 for the modified layer and the fin.