Semiconductor chip with stepped slots and preparation method thereof
By designing the hole walls of the HEMT chip as a first sidewall, a stepped wall, and a second sidewall structure connected in sequence, and optimizing the etching process, the problem of poor metal filling caused by the limited hole size was solved, achieving high coverage metal deposition, avoiding voids, and making it suitable for aerospace, communication technology, switching power supply and other fields.
Patent Information
- Application Number
- CN202510859050.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-25
- Publication Date
- 2025-11-11
AI Technical Summary
The limited size of vias in HEMT chips leads to poor deposition and filling of metal layers within the vias, resulting in low metal coverage and voids.
The design of the slot wall consists of a first sidewall, a stepped wall, and a second sidewall connected in sequence. The inner diameter of the second sidewall is larger than that of the first sidewall. Metal is deposited through the larger second sidewall, and the oxygen content of the etching gas is optimized by combining two etching processes to form a stepped structure to improve the metal filling coverage.
It effectively improves the filling coverage of the metal layer in the hole trench, avoids the occurrence of voids, and does not affect the miniaturization design of semiconductor chips.
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Figure CN120936066A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor chip with stepped vias and a method for fabricating the same. Background Technology
[0002] HEMT (High Electron Mobility Transistor) is a heterojunction field-effect transistor widely used in aerospace, communications, automotive electronics, and switching power supplies, and is receiving particular attention in high-power and high-frequency applications. HEMT chips are a crucial component of HEMTs.
[0003] In related technologies, HEMT chips mainly consist of a semiconductor layer and a film stack grown on the semiconductor layer. The film stack has holes and grooves, within which metal layers are deposited.
[0004] However, due to the size limitations of semiconductor chips, the size of the vias is small, which is not conducive to the deposition and filling of metal layers in the vias, resulting in low metal filling coverage and voids. Summary of the Invention
[0005] This disclosure provides a semiconductor chip with stepped vias and a method for fabricating the same, which can improve metal filling coverage. The technical solution is as follows:
[0006] On one hand, embodiments of this disclosure provide a semiconductor chip with high metal filling coverage, including a semiconductor layer and a film stack;
[0007] The film stack is located on one side of the semiconductor layer. The side of the film stack facing away from the semiconductor layer has a hole. The wall of the hole includes a first sidewall, a stepped wall and a second sidewall connected in sequence. The second sidewall is farther away from the semiconductor layer than the first sidewall. The inner diameter of the second sidewall is larger than the inner diameter of the first sidewall. The first sidewall and the second sidewall both have an angle with the stepped wall. The stepped wall is parallel to the semiconductor layer.
[0008] In one implementation of this disclosure, the included angle between the first sidewall and the step wall is 82° to 92°.
[0009] The included angle between the second sidewall and the stepped wall is 70° to 80°.
[0010] In one implementation of this disclosure, the film stack includes a Ti layer, an AlSi layer, a TiN layer, and a dielectric layer;
[0011] The Ti layer, AlSi layer, TiN layer, and dielectric layer are sequentially stacked on one side of the semiconductor layer;
[0012] A portion of the first sidewall is located in the TiN layer, and another portion of the first sidewall is located in the dielectric layer;
[0013] The stepped wall is located in the medium layer;
[0014] The second sidewall is located in the dielectric layer.
[0015] On the other hand, this disclosure provides a method for fabricating a semiconductor chip, the method being used to fabricate the semiconductor chip as described in the preceding aspect, the method comprising:
[0016] Fabrication of semiconductor layers;
[0017] A film stack is prepared on one side of the semiconductor layer, the film stack comprising a Ti layer, an AlSi layer, a TiN layer and a dielectric layer stacked sequentially;
[0018] A photoresist layer is prepared on the side of the film stack opposite to the semiconductor layer;
[0019] The first etching is performed based on the photoresist layer;
[0020] A second etching is performed based on the photoresist layer to obtain a hole. The oxygen content of the etching gas in the second etching process is greater than the oxygen content of the etching gas in the first etching process.
[0021] In one implementation of this disclosure, the first etching based on the photoresist layer includes:
[0022] The dielectric layer is etched, retaining one-seventh to one-fifth of the total thickness of the dielectric layer.
[0023] In one implementation of this disclosure, the first etching based on the photoresist layer includes:
[0024] Set the etching pressure to 200–300 mTorr, the etching power to 500–700 W, the etching time to 250–350 s, and the etching gas to CHF3, AR, or CF4.
[0025] In one implementation of this disclosure, the first etching based on the photoresist layer further includes:
[0026] Set the flow rate of CHF3 to 40–60 sccm, the flow rate of AR to 130–170 sccm, and the flow rate of CF4 to 50–70 sccm.
[0027] In one implementation of this disclosure, a second etching is performed based on the photoresist layer, including:
[0028] Set the etching pressure to 5–11 mTorr, the source RF power to 200–400 W, the bias RF power to 50–150 W, the etching time to 350–450 s, and the etching gas to CF4 and O2.
[0029] In one implementation of this disclosure, the second etching based on the photoresist layer further includes:
[0030] Set the flow rate of CF4 to 70–90 sccm and the flow rate of O2 to 15–25 sccm.
[0031] In one implementation of this disclosure, the preparation method further includes:
[0032] During the first etching process based on the photoresist layer, the selectivity ratio of the dielectric layer to the photoresist layer is greater than 2;
[0033] During the second etching process based on the photoresist layer, the selectivity ratio of the dielectric layer to the photoresist layer is less than 0.5.
[0034] The beneficial effects of the technical solutions provided in this disclosure include at least the following:
[0035] The semiconductor chip provided in this embodiment has a semiconductor layer and a film stack. One side of the film stack has a trench, and the trench wall is composed of a first sidewall, a stepped wall, and a second sidewall connected in sequence. The second sidewall is farther away from the semiconductor layer than the first sidewall, and the inner diameter of the second sidewall is larger than that of the first sidewall. This facilitates the deposition of the metal layer from the larger second sidewall, effectively improving the metal filling coverage and avoiding voids. Furthermore, since the size of the trench is increased only in the part farther from the semiconductor layer, while the size of the rest remains unchanged, it will not have a significant impact on the miniaturization design of the semiconductor chip. The stepped wall, located between the first and second sidewalls, serves to accommodate the space corresponding to the first sidewall and the space corresponding to the second sidewall of the trench, which is beneficial to the metal filling coverage within the trench.
[0036] In other words, the semiconductor chip provided in this embodiment has a hole groove on one side of the film stack. The hole groove wall is designed as a first sidewall, a stepped wall and a second sidewall connected in sequence. Metal is deposited through the larger second sidewall, which is conducive to the deposition of metal in the hole groove, thereby effectively improving the metal filling coverage and avoiding voids. Attached Figure Description
[0037] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0038] Figure 1 This is a schematic diagram of the structure of a semiconductor chip provided in an embodiment of this disclosure;
[0039] Figure 2 This is a schematic diagram of the structure of the membrane stack provided in the embodiments of this disclosure;
[0040] Figure 3 This is a flowchart of a method for fabricating a semiconductor chip according to an embodiment of this disclosure;
[0041] Figure 4 This is a flowchart of another method for fabricating a semiconductor chip provided in this disclosure embodiment;
[0042] Figure 5 This is a schematic diagram of the preparation process provided in the embodiments of this disclosure;
[0043] Figure 6 This is a schematic diagram of the preparation process provided in the embodiments of this disclosure;
[0044] Figure 7 This is a schematic diagram of the preparation process provided in the embodiments of this disclosure.
[0045] Icon labels:
[0046] 10. Semiconductor layer;
[0047] 20. Membrane stacking;
[0048] 210, Ti layer; 220, AlSi layer; 230, TiN layer; 240, dielectric layer;
[0049] 30. Holes and slots;
[0050] 310. First sidewall; 320. Stepped wall; 330. Second sidewall;
[0051] 40. Photoresist layer;
[0052] 410. Etched holes;
[0053] 50. Intermediate groove. Detailed Implementation
[0054] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0055] HEMT (High Electron Mobility Transistor) is a heterojunction field-effect transistor widely used in aerospace, communications, automotive electronics, and switching power supplies, and is receiving particular attention in high-power and high-frequency applications. HEMT chips are a crucial component of HEMTs.
[0056] In related technologies, HEMT chips mainly consist of a semiconductor layer and a film stack grown on the semiconductor layer. The film stack has holes and grooves, within which metal layers are deposited.
[0057] However, due to the size limitations of semiconductor chips, the size of the vias is small, which is not conducive to the deposition and filling of metal layers in the vias, resulting in low metal filling coverage and voids.
[0058] To address the aforementioned technical problems, this disclosure provides a semiconductor chip. Figure 1 This is a schematic diagram of the semiconductor chip structure, combined with... Figure 1 In this embodiment, the semiconductor chip includes a semiconductor layer 10 and a film stack 20.
[0059] The film stack 20 is located on one side of the semiconductor layer 10. The side of the film stack 20 facing away from the semiconductor layer 10 has a hole 30. The wall of the hole 30 includes a first sidewall 310, a step wall 320 and a second sidewall 330 connected in sequence. The second sidewall 330 is farther away from the semiconductor layer 10 than the first sidewall 310. The inner diameter of the second sidewall 330 is larger than the inner diameter of the first sidewall 310. Both the first sidewall 310 and the second sidewall 330 have an angle with the step wall 320. The step wall 320 is parallel to the semiconductor layer 10.
[0060] The semiconductor chip provided in this embodiment has a semiconductor layer 10 and a film stack 20. One side of the film stack 20 has a trench 30. The trench 30 has walls composed of a first sidewall 310, a stepped wall 320, and a second sidewall 330 connected in sequence. The second sidewall 330 is farther away from the semiconductor layer 10 than the first sidewall 310, and the inner diameter of the second sidewall 330 is larger than that of the first sidewall 310. This facilitates the deposition of the metal layer from the larger second sidewall 330, effectively improving the metal filling coverage and avoiding voids. Furthermore, since the size of the trench 30 is increased only in the portion farther from the semiconductor layer 10, while the size of the remaining portion is not increased, it will not have a significant impact on the miniaturization design of the semiconductor chip. The stepped wall 320 is located between the first sidewall 310 and the second sidewall 330, which can accommodate the space of the trench 30 corresponding to the first sidewall 310 and the space of the trench 30 corresponding to the second sidewall 330, which is beneficial to the metal filling coverage within the trench 30.
[0061] In other words, the semiconductor chip provided in this embodiment has a hole 30 on one side of the film stack 20. The hole wall of the hole 30 is designed as a first sidewall 310, a stepped wall 320 and a second sidewall 330 connected in sequence. Metal is deposited through the larger second sidewall 330, which is conducive to the deposition of metal in the hole 30, thereby effectively improving the metal filling coverage and avoiding voids.
[0062] In this embodiment, the semiconductor chip can be either a normally off GaN HEMT chip or a normally on GaNHEMT chip, and this disclosure does not limit it.
[0063] For example, the included angle α between the first sidewall 310 and the step wall 320 is 82° to 92°, and the included angle b between the second sidewall 330 and the step wall 320 is 70° to 80°.
[0064] In the above implementation, the step wall 320 is parallel to the semiconductor layer, that is, the step wall 320 is perpendicular to the epitaxial growth direction of the semiconductor chip. Taking the step wall 320 as a reference, the angle b between the second sidewall 330 and the step wall 320 is smaller than the angle a between the first sidewall 310 and the step wall 320. In other words, the second sidewall 330 is smoother than the first sidewall 310, which makes the holes at the second sidewall 330 more likely to open, thereby facilitating metal deposition.
[0065] In this embodiment, the included angle α between the first sidewall 310 and the step wall 320 is 87°, and the included angle b between the second sidewall 330 and the step wall 320 is 75°.
[0066] Of course, in other embodiments, the included angle α between the first sidewall 310 and the step wall 320, and the included angle b between the second sidewall 330 and the step wall 320, can be adjusted to other values within the above-mentioned angle range according to actual needs.
[0067] For example, the distance L1 between the step wall 320 and the bottom surface of the hole in the trench 30 is 1000-1200 nm. The distance L2 between the step wall 320 and the side of the film stack 20 away from the semiconductor layer 10 is 600-700 nm.
[0068] In this embodiment, the distance L1 between the stepped wall 320 and the bottom surface of the hole in the groove 30 is 1150 nm, and the distance L2 between the stepped wall 320 and the side of the film stack 20 away from the semiconductor layer 10 is 650 nm.
[0069] For example, the width D of the step wall 320 is 5 to 15 nm.
[0070] In this embodiment, the width D of the step wall 320 is 10 nm.
[0071] Figure 2 This is a schematic diagram of the structure of membrane stack 20, combined with Figure 2 In this embodiment, the film stack 20 includes a Ti layer 210, an AlSi layer 220, a TiN layer 230, and a dielectric layer 240.
[0072] A portion of the first sidewall 310 is located in the TiN layer 230, another portion of the first sidewall 310 is located in the dielectric layer 240, the stepped wall 320 is located in the dielectric layer 240, and the second sidewall 330 is located in the dielectric layer 240.
[0073] In the above implementation, the top opening of the trench is located at the dielectric layer 240. In the epitaxial growth direction, one end of the second sidewall 330 is located at the opening of the trench, and the other end of the second sidewall 330 extends toward the TiN layer 230 and is located inside the dielectric layer 240. One end of the first sidewall 310 is located inside the dielectric layer 240, and the other end of the first sidewall 310 extends toward the TiN layer 230 and is located inside the TiN layer 230. The step wall 320 is perpendicular to the epitaxial growth direction.
[0074] The combination of Ti layer 210, AlSi layer 220, and TiN layer 230 is a metal layer primarily used for conductivity. Ti layer 210 acts as an adhesive, exhibiting good adhesion to the semiconductor layer or the front-end dielectric layer. TiN layer 230 serves both an adhesive and a passivation function, preventing oxidation of AlSi layer 220. AlSi layer 220 primarily functions to conduct electron charges.
[0075] For example, the specifications are as follows: the thickness of the Ti layer 210 is about 80 to 120 nm; the thickness of the AlSi layer 220 is about 2 to 4 μm; and the thickness of the TiN layer 230 is about 80 to 120 nm.
[0076] In this embodiment, the thickness of Ti layer 210 is 100 nm, the thickness of AlSi layer 220 is 3 μm, and the thickness of TiN layer 230 is 100 nm.
[0077] Of course, in other embodiments, the thicknesses of the Ti layer 210, AlSi layer 220, and TiN layer 230 may also be other values within the above-mentioned thickness range, and this disclosure does not limit them.
[0078] For example, the dielectric layer 240 may be a SiN layer, a SiO layer, or a composite dielectric layer, etc., and this disclosure does not limit it.
[0079] In this embodiment, the dielectric layer 240 is a SiO layer.
[0080] For example, the thickness of the dielectric layer 240 is 1700–1900 nm.
[0081] In this embodiment, the thickness of the dielectric layer 240 is 1800 nm.
[0082] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor chip according to an embodiment of the present disclosure. This method is used to fabricate... Figure 1 semiconductor chips, combined Figure 3 In this embodiment, the preparation method includes:
[0083] Step 301: Prepare semiconductor layer 10.
[0084] Step 302: Prepare a film stack 20 on one side of the semiconductor layer 10. The film stack 20 includes a Ti layer 210, an AlSi layer 220, a TiN layer 230 and a dielectric layer 240 stacked sequentially.
[0085] Step 303: Prepare a photoresist layer 40 on the side of the film stack 20 that faces away from the semiconductor layer 10.
[0086] Step 304: Perform the first etching based on the photoresist layer 40;
[0087] Step 305: Perform a second etching based on the photoresist layer 40 to obtain the hole 30. The oxygen content of the etching gas in the second etching process is greater than the oxygen content of the etching gas in the first etching process.
[0088] The first and second etching processes are performed separately. Because the oxygen content of the etching gas in the second etching process is greater than that in the first, the photoresist layer recedes more significantly during the second etching. This results in the inner diameter of the second sidewall 330 of the via 30 being larger than the inner diameter of the first sidewall 310. This facilitates metal deposition from the larger second sidewall 330, effectively improving metal coverage and preventing voids. Furthermore, since the size of the first sidewall 310 does not increase during the first etching, but only the size of the second sidewall 330 increases, it does not significantly impact the miniaturization design of the semiconductor chip. The stepped wall 320, located between the first sidewall 310 and the second sidewall 330, serves to accommodate the space corresponding to both the first and second sidewalls of the via 30, further improving the metal coverage within the via 30.
[0089] In other words, by providing a pore groove 30 on one side of the membrane stack 20, and designing the pore wall of the pore groove 30 as a first sidewall 310, a stepped wall 320 and a second sidewall 330 connected in sequence, metal is deposited through the larger second sidewall 330, which is conducive to the deposition of metal in the pore groove 30, thereby effectively improving the metal filling coverage and avoiding voids.
[0090] Figure 4 A flowchart illustrating another method for fabricating a semiconductor chip according to an embodiment of this disclosure, in conjunction with... Figure 4 In this embodiment, the preparation method includes:
[0091] Step 401: Prepare semiconductor layer 10.
[0092] For example, the semiconductor layer 10 can be fabricated on a substrate, which is one of a sapphire substrate, a SiC substrate, a Si substrate, or a GaN substrate.
[0093] In this embodiment, the substrate is a Si substrate.
[0094] Step 402: Prepare a film stack 20 on one side of the semiconductor layer 10.
[0095] In this embodiment, step 402 includes the following steps:
[0096] Step 4021: Ti layer 210, AlSi layer 220 and TiN layer 230 are sequentially prepared on one side of semiconductor layer 10 by physical vapor deposition (PVD), so that Ti layer 210, AlSi layer 220 and TiN layer 230 are stacked sequentially.
[0097] Step 4022: A dielectric layer 240 is prepared on the side of the TiN layer 230 facing away from the semiconductor layer 10 by plasma enhanced chemical vapor deposition (PECVD).
[0098] For example, the dielectric layer 240 may be a SiN layer, a SiO layer, or a composite dielectric layer 240, etc., and this disclosure does not limit it.
[0099] In this embodiment, the dielectric layer 240 is a SiO layer.
[0100] Step 403: Prepare a photoresist layer 40 on the side of the film stack 20 that faces away from the semiconductor layer 10 (see...) Figure 5 ).
[0101] In this embodiment, step 403 includes the following steps:
[0102] Step 4031: Apply photoresist to the side of the film stack 20 that faces away from the semiconductor layer 10.
[0103] For example, the thickness of the photoresist is 3 μm.
[0104] In the above implementation method, setting the thickness of the photoresist to the above value can ensure both its functionality and coating efficiency.
[0105] Step 4032: Pattern the photoresist to obtain photoresist layer 40.
[0106] For example, patterned photoresist is a photoresist layer 40 with a pattern formed by steps such as curing, exposure, and development, in preparation for subsequent etching.
[0107] In this embodiment, the photoresist layer 40 has an etching hole 410, and the angle c between the inner sidewall of the etching hole 410 and the plane where the semiconductor layer 10 is located is 70° to 80°.
[0108] In the above implementation, since the inner wall of the etched hole 410 has a certain angle, a groove with a certain angle can be etched in the subsequent etching steps.
[0109] Step 404: Perform the first etching based on the photoresist layer 40 to obtain the intermediate trench 50 on the film stack 20 (see...) Figure 6 ).
[0110] For example, in step 404, the etching parameters for the first etching are designed as follows:
[0111] Set the etching pressure to 200–300 mTorr, the etching power to 500–700 W, the etching time to 250–350 s, and the etching gas to CHF3, AR, or CF4.
[0112] For example, the flow rate of CHF3 is set to 40-60 sccm, the flow rate of AR is set to 130-170 sccm, and the flow rate of CF4 is set to 50-70 sccm.
[0113] In this embodiment, the etching pressure is set to 250 mTorr, the etching power is set to 600 W, the etching time is set to 293 s, the CHF3 flow rate is set to 50 sccm, the AR flow rate is set to 150 sccm, and the CF4 flow rate is set to 60 sccm.
[0114] Using the above etching parameters, a suitable depth of intermediate groove 50 can be etched on the dielectric layer 240.
[0115] For example, in step 404, the dielectric layer 240 is etched, retaining one-seventh to one-fifth of the total thickness of the dielectric layer 240.
[0116] For example, the total thickness of the dielectric layer 240 is 1800 nm. After the first etching, the etched part of the dielectric layer 240 retains one-seventh to one-fifth of the total thickness (1800 nm).
[0117] In this embodiment, after the first etching, the etching depth of the dielectric layer 240 is 1500nm, that is, the depth of the intermediate trench 50 is 1500nm, and the dielectric layer 240 retains 300nm.
[0118] It is worth noting that the angle d between the inner wall of the intermediate trench 50 and the plane where the semiconductor layer 10 is located is the same as the angle c between the inner sidewall of the etched hole 410 and the plane where the semiconductor layer 10 is located, which is 70° to 80°.
[0119] Step 405: Perform a second etching based on the photoresist layer 40 to obtain the hole 30 based on the intermediate trench 50 (see...). Figure 7 ).
[0120] For example, in step 405, the etching parameters for the second etching are designed as follows:
[0121] The etching pressure was set to 5–11 mTorr, the source radio frequency (SRF) power to 200–400 W, the bias radio frequency (BRF) power to 50–150 W, the etching time to 350–450 s, and the etching gases to CF4 and O2. By adjusting the source RF power, the chemical etching process could be controlled; by adjusting the bias RF power, the physical etching process could be controlled.
[0122] For example, the flow rate of CF4 is set to 70-90 sccm, and the flow rate of O2 is set to 15-25 sccm.
[0123] In this embodiment, the etching pressure is set to 8 mTorr, the source RF power is set to 300W, the bias RF power is set to 100W, the etching time is set to 394s, the CF4 flow rate is set to 80 sccm, and the O2 flow rate is set to 20 sccm.
[0124] During the second etching process, the etching gas was switched from CHF3, AR, and CF4 to CF4 and O2, resulting in an increased O2 content. This led to a more significant retreat of the photoresist layer 40 (the inner diameter of the etched hole 410 increased). Simultaneously, the change in the size of the etched hole 410 also transferred its morphological change to the dielectric layer 240, causing the size of the dielectric layer 240 to also increase, thus forming the step wall 320 and the second sidewall 330.
[0125] It is worth noting that in the first etching, the photoresist layer 40 was consumed by approximately 0.8 μm, while in the second etching, the consumption was approximately 1–2 μm. This demonstrates that increasing the oxygen content of the etching gas leads to a more significant recession of the photoresist layer 40.
[0126] In this embodiment, during the first etching process based on the photoresist layer 40, the selectivity ratio of the dielectric layer 240 to the photoresist layer 40 is greater than 2. During the second etching process based on the photoresist layer 40, the selectivity ratio of the dielectric layer 240 to the photoresist layer 40 is less than 0.5.
[0127] In other words, during the first etching process based on the photoresist layer 40, the selection ratio of the dielectric layer 240 to the photoresist layer 40 is greater than that during the second etching process based on the photoresist layer 40.
[0128] This prevents the photoresist layer 40 from being consumed too quickly during the second etching process, thus avoiding insufficient etching depth.
[0129] The preparation method provided in this disclosure is applicable not only to dry etching of shallow holes (aspect ratio not greater than 5) but also to dry etching of deep holes (aspect ratio greater than 5).
[0130] Step 406: Remove excess photoresist layer 40 (see...) Figure 1 ).
[0131] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0132] The above is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above through embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.
Claims
1. A semiconductor chip with stepped vias, characterized in that, It includes a semiconductor layer (10) and a film stack (20); The film stack (20) is located on one side of the semiconductor layer (10). The side of the film stack (20) facing away from the semiconductor layer (10) has a hole (30). The wall of the hole (30) includes a first sidewall (310), a stepped wall (320), and a second sidewall (330) connected in sequence. The second sidewall (330) is farther away from the semiconductor layer (10) than the first sidewall (310). The inner diameter of the second sidewall (330) is larger than the inner diameter of the first sidewall (310). The first sidewall (310) and the second sidewall (330) both have an angle with the stepped wall (320). The stepped wall (320) is parallel to the semiconductor layer (10).
2. The semiconductor chip according to claim 1, characterized in that, The included angle between the first sidewall (310) and the stepped wall (320) is 82° to 92°; The included angle between the second sidewall (330) and the stepped wall (320) is 70° to 80°.
3. The semiconductor chip according to claim 1, characterized in that, The film stack (20) includes a Ti layer (210), an AlSi layer (220), a TiN layer (230), and a dielectric layer (240); The Ti layer (210), AlSi layer (220), TiN layer (230) and dielectric layer (240) are sequentially stacked on one side of the semiconductor layer (10); A portion of the first sidewall (310) is located in the TiN layer (230), and another portion of the first sidewall (310) is located in the dielectric layer (240); The stepped wall (320) is located in the medium layer (240); The second sidewall (330) is located in the dielectric layer (240).
4. A method for fabricating a semiconductor chip, characterized in that, The preparation method is used to prepare the semiconductor chip according to claim 1, and the preparation method includes: Prepare a semiconductor layer (10); A film stack (20) is prepared on one side of the semiconductor layer (10), the film stack (20) comprising a Ti layer (210), an AlSi layer (220), a TiN layer (230) and a dielectric layer (240) stacked sequentially; A photoresist layer (40) is prepared on the side of the film stack (20) opposite to the semiconductor layer (10); The first etching is performed based on the photoresist layer (40); A second etching is performed based on the photoresist layer (40) to obtain a hole (30), wherein the oxygen content of the etching gas in the second etching process is greater than the oxygen content of the etching gas in the first etching process.
5. The preparation method according to claim 4, characterized in that, The first etching is performed based on the photoresist layer (40), including: The dielectric layer (240) is etched, retaining one-seventh to one-fifth of the total thickness of the dielectric layer (240).
6. The preparation method according to claim 4, characterized in that, The first etching is performed based on the photoresist layer (40), including: Set the etching pressure to 200–300 mTorr, the etching power to 500–700 W, the etching time to 250–350 s, and the etching gas to CHF3, AR, or CF4.
7. The preparation method according to claim 6, characterized in that, The first etching based on the photoresist layer (40) further includes: Set the flow rate of CHF3 to 40–60 sccm, the flow rate of AR to 130–170 sccm, and the flow rate of CF4 to 50–70 sccm.
8. The preparation method according to claim 4, characterized in that, A second etching is performed based on the photoresist layer (40), including: Set the etching pressure to 5–11 mTorr, the source RF power to 200–400 W, the bias RF power to 50–150 W, the etching time to 350–450 s, and the etching gas to CF4 and O2.
9. The preparation method according to claim 8, characterized in that, The second etching based on the photoresist layer (40) further includes: Set the flow rate of CF4 to 70–90 sccm and the flow rate of O2 to 15–25 sccm.
10. The preparation method according to claim 4, characterized in that, The preparation method further includes: During the first etching process based on the photoresist layer (40), the selection ratio of the dielectric layer (240) to the photoresist layer (40) is greater than 2; During the second etching process based on the photoresist layer (40), the selectivity ratio of the dielectric layer (240) to the photoresist layer (40) is less than 0.5.