Apparatus with memory cell calibration mechanism and method of operation thereof

Abstract

Methods, devices, and systems related to tracking charge loss are described. An apparatus may include a tracking mechanism configured to make direct measurements for tracking charge loss in a first type of cells. The apparatus may be configured to specify a set of the first type of cells as a proxy for modeling charge loss at a second type of cells having a different storage density than the first type of cells. The apparatus may use the tracking mechanism to make measurements on the set of proxy first type cells and translate the measurements to account for the charge loss at the second type cells.

Description

Technical Field

[0001] The disclosed embodiments relate to apparatuses, and more particularly, to semiconductor memory devices with memory cell calibration mechanisms and methods of operation thereof. Background Technology

[0002] Memory systems may employ memory devices to store and access information. Memory devices may include volatile memory devices, non-volatile memory devices (e.g., flash memory employing NAND technology or logic gates, NOR technology or logic gates, or combinations thereof), or combined devices. Memory devices utilize electrical energy along with corresponding threshold levels or processing / reading voltage levels to store and access data. However, the performance or characteristics of memory devices change or degrade over time, with use and environmental conditions. Changes in performance or characteristics over time conflict with threshold or processing voltage levels, leading to errors and other performance problems. As memory devices become more dense (e.g., storing several more bits per cell), the altered performance deteriorates further. Attached Figure Description

[0003] The foregoing and other objects, features, and advantages of the invention will become apparent from the following description of the embodiments illustrated in the accompanying drawings, wherein reference characters refer to the same parts throughout the various views. The drawings are not necessarily drawn to scale; rather, the focus is on illustrating the principles of this disclosure.

[0004] Figure 1 This is a block diagram of a computing system according to an embodiment of the present technology.

[0005] Figure 2A and Figure 2B This is an explanation of charge loss.

[0006] Figure 3 This is an instance translation mechanism based on an embodiment of the present technology.

[0007] Figure 4 This is a description of storage state measurement according to an embodiment of the present technology.

[0008] Figure 5 This is a flowchart illustrating an example method of manufacturing / operating equipment according to an embodiment of the present technology.

[0009] Figure 6 This is a schematic view of a system including a device according to an embodiment of the present technology. Detailed Implementation

[0010] As described in more detail below, the technology disclosed herein relates to an apparatus for calibrating memory cells in a device comprising multiple types of cells, such as a memory system, a system having a memory device, related methods, etc. The apparatus can track or measure the amount of charge loss of a first type of memory cell (e.g., a higher-density memory cell, such as a four-level cell (QLC)) and use the obtained charge loss to estimate the charge loss of a second type of memory cell (e.g., a lower-density memory cell, such as a three-level cell (TLC), a multi-level cell (MLC), and / or a single-level cell (SLC)).

[0011] Technological advancements have allowed memory cells (e.g., NAND flash memory cells) to store an increased number of bits. The storage capacity of a memory cell can be expressed as bits per cell (BPC). For example, SLC may have 1 BPC, MLC 2 BPC, TLC 3 BPC, and QLC 4 BPC. For a given die size, increasing the BPC reduces the cost per bit because more bits can be stored on a single die. Furthermore, including cells of various types or densities within a single cell group or device provides additional features and operational flexibility. For example, during periods of high demand or relatively frequent memory access, the device can utilize lower-density cells for temporary memory storage, similar to cache memory. For this write influx, the device can initially receive data using the faster write speed of the lower-density cells. Subsequently, the device can move the initially received data to higher-density cells (e.g., moving 12 bits stored in 12 SLCs to 4 TLCs or 3 QLCs).

[0012] However, different types of memory cells may behave differently. For example, QLC and TLC can have different charge loss patterns. In other words, different types of memory cells may experience different rates of charge loss. Conventional methods for measuring charge loss require separate measurement circuitry. Other conventional methods for tracking and calculating charge loss require relatively large tables to track the write times and / or storage durations of each cell or group of cells. Therefore, such conventional methods require additional resources for each type of memory, such as dedicated measurement circuitry or designated storage space for tracking tables.

[0013] Embodiments of the technology described herein can utilize the resources of one type of memory cell (e.g., QLC) to calculate / track the estimated charge loss of another type of memory cell (e.g., faster or lower-density cells, such as TLC). For example, the device may include circuitry and / or routines for measuring one or more charge loss characteristics of a QLC block. The device may include or select one or more dummy word lines (WLs) of the QLC as proxies for representing and tracking the charge loss behavior of one or more TLC blocks. When estimating the charge loss of a TLC block, the device can use existing circuitry / routines to measure the charge loss characteristics of the corresponding dummy WL without directly measuring or tracking the TLC block. The device may use a translation mechanism to convert the measured charge loss characteristics of the dummy WL into a charge loss estimate of the TLC block. The device can use the same type of resources to estimate and track the charge loss behavior of multiple types of memory cells, rather than relying on separate dedicated resources for each type of cell.

[0014] Figure 1 This is a block diagram of a computing system 100 according to an embodiment of the present technology. The computing system 100 may include a personal computing device / system, an enterprise system, a mobile device, a server system, a database system, a distributed computing system, or the like. The computing system 100 may include a memory system 102 coupled to a host device 104. The host device 104 may include one or more processors capable of writing data to and / or reading data from the memory system 102. For example, the host device 104 may include an upstream central processing unit (CPU).

[0015] Memory system 102 may include circuitry configured to store data (via, for example, a write operation) and provide access to the stored data (via, for example, a read operation). For example, memory system 102 may include a persistent or non-volatile data storage system, such as a NAND-based flash drive system, a solid-state drive (SSD) system, an SD card, or the like. In some embodiments, memory system 102 may include a host interface 112 (e.g., a buffer, transmitter, receiver, and / or the like) configured to facilitate communication with host device 104. For example, host interface 112 may be configured to support one or more host interconnect schemes, such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), Serial AT Accessory (SATA), or the like. Host interface 112 may receive commands, addresses, data (e.g., write data), and / or other information from host device 104. Host interface 112 may also transmit data (e.g., read data) and / or other information to host device 104.

[0016] The memory system 102 may further include a memory controller 114 and a memory array 116. The memory array 116 may include memory cells configured to store unit information. The memory controller 114 may be configured to control the overall operation of the memory system 102, including the operation of the memory array 116.

[0017] In some embodiments, memory array 116 may include a set of NAND flash devices or packages. Each of the packages may include a set of memory cells that store data in their respective charge storage structures. Memory cells may include, for example, floating gates, charge traps, phase transition, ferroelectric, magnetoresistive storage elements, and / or other suitable storage elements configured to permanently or semi-permanently store data. Memory cells may be single-transistor memory cells that can be programmed to a target state to represent information. For example, charge may be placed on or removed from the charge storage structure (e.g., charge trap or floating gate) of the memory cell to program the cell to a specific data state. The stored charge on the charge storage structure of the memory cell may indicate the Vt of the cell. For example, an SLC may be programmed to be the target of two different data states, which may be represented by binary units 1 or 0. Moreover, some flash memory cells may be programmed to be the target of more than two data states. An MLC may be programmed to any of four data states (e.g., represented by binary 00, 01, 10, 11) to store two data bits. Similarly, a TLC may be programmed to be eight (i.e., 1... 3 One of the data states is used to store three data bits, and the QLC can be programmed to be 16 (i.e., 1...). 4 One of the data states can store four data bits.

[0018] Such memory cells can be arranged in rows (e.g., each corresponding to a word line 130) and columns (e.g., each corresponding to a bit line). This arrangement can further correspond to different groups of memory cells. For example, each word line 130 may correspond to one or more memory pages. Furthermore, the memory array 116 may contain memory blocks, each containing a set of memory pages. In operation, data can be written to or otherwise programmed (e.g., erased) with respect to individual memory areas of the memory array 116, for example, by writing to page groups and / or memory blocks. In NAND-based memories, a write operation typically involves programming a memory cell in a selected memory page with a specific data value (e.g., a data bit string having a logic 0 or logic 1 value). An erase operation is similar to a write operation, except that an erase operation reprograms an entire memory block or multiple memory blocks to the same data state (e.g., logic 0).

[0019] As an illustrative example, device 100 and its memory array 116 are described as a group of first-type cells 132 (e.g., QLC) with higher density and a group of second-type cells 134 (e.g., TLC) with lower density. In some embodiments, the second-type cells 134 may be permanently configured (via, for example, one or more physical or structural features) to have a lower density. In other embodiments, the second-type cells 134 may be physically or structurally configured to have a maximum capacity matching that of the first-type cells 132, but with a dynamically specified configuration to store fewer bits than the maximum capacity. Memory array 116 may contain the first-type cells 132 and the second-type cells 134 together in a single package. Within one or more packages, the first-type cells 132 and the second-type cells 134 may be grouped into separate blocks. For example, a package in memory array 116 may contain one or more QLC blocks and one or more TLC blocks. Moreover, memory array 116 may contain more first-type cells 132 than second-type cells 134.

[0020] In some embodiments, device 100 may use first type cells 132 for primary and / or long-term storage and use second type cells 134 or a subset thereof as dynamic switching memory 136. As an illustrative example, when device 100 is experiencing high usage (e.g., rapidly receiving more than a threshold amount of write commands over a predetermined duration), device 100 may write incoming data to dynamic switching memory 136. Thus, device 100 can utilize the lower density of the lower-density cells and increased operating speed to accommodate relatively rapid data inflows. Later, for example, when the workload decreases, device 100 may move data stored in dynamic switching memory 136 to the higher-density first type cells 132, thereby effectively compressing the received data into a smaller number of cells. Dynamic switching memory 136 may be selectively enabled based on one or more real-time measurements characterizing the workload, such as valid data detected for discarded items, one or more identifiable command patterns, remaining unoccupied examples of second type cells 134, or the like. Dynamic transfer memory 136 can be separated from fixed cache 138 (e.g., memory designated to always provide transfer memory or cache functionality) and is a complement to fixed cache 138.

[0021] While memory array 116 is described with respect to memory cells, it should be understood that memory array 116 may include other components (not shown). For example, memory array 116 may also include other circuit components for accessing and / or programming (e.g., writing) data and for other functionalities, such as multiplexers, decoders, buffers, read / write drivers, address registers, data output / data input registers, etc.

[0022] As described above, memory controller 114 can be configured to control the operation of memory array 116. Memory controller 114 may include processor 122, such as a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. Processor 122 can execute instructions encoded in hardware, firmware, and / or software (e.g., instructions stored in controller embedded memory 124) to perform various processes, logic flows, and routines for controlling the operation of memory system 102 and / or memory array 116.

[0023] Furthermore, the memory controller 114 may further include an array controller 128 that controls or monitors detailed or target aspects of the operation of the memory array 116. For example, the array controller 128 may provide a communication interface between the processor 122 and the memory array 116 (e.g., components therein). The array controller 128 may be used as a multiplexer / demultiplexer, for example, for handling data feeds along flash devices serially connected to the memory array 116.

[0024] The logic circuitry within the memory controller 114, the corresponding firmware, or a combination thereof, can implement a calibration mechanism 150 that adjusts one or more aspects of data access based on the state of the stored charge. To provide background on the calibration mechanism 150, Figure 2A and Figure 2B This is an explanation of charge loss. Figure 2A This diagram illustrates the charge distribution within a single cell (left) and the Vt distribution (e.g., relative to the programming verification level; right) for a given bit value after an initial programming operation. When a memory cell is programmed, at least the target amount of charge is stored in the charge trapping layer (CTL) to represent the corresponding bit value. During write / programming operations, some charge may unintentionally appear or be placed in the tunnel layer (TNL) and / or the semiconductor substrate (polysilicon) layer.

[0025] At the end of a write / programming operation, the memory system 102 can read or verify the result to ensure accuracy. In practice, the memory system 102 can perform verification to ensure that the stored charge exceeds the access level (e.g., the program-verify (PV) level) corresponding to the target bit value. Different cells can retain different amounts of charge in the CTL, thus resulting in a concave curve in the Vt distribution of the cells storing the target value.

[0026] Figure 2BThis section explains charge loss in relation to both individual cells and the Vt distribution. Charge loss corresponds to the migration of charge from the CTL to other locations within the memory cell (e.g., TNL and / or polysilicon). This displacement of stored charge effectively reduces Vt. Because memory cells may suffer or experience charge loss at different rates, the Vt of cells storing location values ​​may change at different rates. Therefore, the Vt distribution for location values ​​may decrease (e.g., shift to the left) and / or widen. Some cells with lower Vt and / or experiencing faster / larger charge loss at initial programming may shift below the PV level. In practice, memory cells with Vt values ​​shifted below the PV level may experience data corruption and reflect bit values ​​different from those initially stored.

[0027] This charge loss behavior can vary depending on the cell type (e.g., based on BPC density). For example, QLC and TLC can have different charge loss characteristics or patterns. Therefore, dedicated charge loss tracking and / or estimation may be required for different types of cells or associated memory blocks.

[0028] Refer again Figure 1 The calibration mechanism 150 (implemented via, for example, logic, software routines / instructions, firmware, or a combination thereof within the processor 122, memory array 116) can be configured to estimate and / or track the charge loss of memory cells and accordingly control adjustments to data processing (e.g., read level voltage adjustment). For a memory array 116 having multiple types of cells (e.g., memory blocks with different BPCs, such as first type cell 132 and second type cell 134), the calibration mechanism 150 may have different tracking mechanisms. For example, the calibration mechanism 150 may include a first tracking mechanism 152 and a second tracking mechanism 160.

[0029] The first tracking mechanism 152 may include circuitry, software instructions / routines, firmware, or a combination thereof configured to track the first type of cell 132 (e.g., a memory block with a denser BPC configuration). The first tracking mechanism 152 may directly track or estimate the data storage behavior (e.g., charge loss) of the first type of cell 132. In some embodiments, the first tracking mechanism 152 may maintain a first tracking list 152 that identifies blocks of the first type of cell 132 based on the amount of charge loss, a corresponding offset of the read level voltage, or the like. For example, the first tracking mechanism 152 may group or bin QLC blocks according to a predetermined range of charge loss or corresponding offset.

[0030] In some embodiments, the first tracking mechanism 152 may include a first measurement mechanism 156 (e.g., a dedicated circuitry and / or operating instructions) configured to directly measure one or more aspects of charge loss in the target first type cell 132. The device 100 may be configured to trigger the first measurement mechanism 156 and obtain the resulting measurements of the block of first type cells 132. The resulting measurements may be used to identify the bin and corresponding access adjustment 158 ​​of each of the measured blocks (e.g., QLC blocks). Details regarding the first tracking mechanism 152 are described below.

[0031] The second tracking mechanism 154 may include circuitry, software instructions / routines, firmware, or a combination thereof configured to track the second type of cell 134 (e.g., a memory block with a less dense BPC configuration). The second tracking mechanism 154 may indirectly track or estimate the data storage behavior (e.g., charge loss) of the second type of cell 134 based on the utilization of the first measurement mechanism 156. For example, the second tracking mechanism 154 may have proxy access groups 162 for a given group (e.g., one or more blocks) of the second type of cell 134. The proxy access group 162 may include one or more examples (e.g., one or more word lines) of access groups 140 of the first type of cell 132 that act as proxies for several target blocks of the second type of cell 134. The second tracking mechanism 154 may utilize the first measurement mechanism 156 to measure memory characteristics (e.g., charge loss) and generate proxy measurements 164 representing the memory state of several target memory blocks.

[0032] As an illustrative example, whenever a data operation (e.g., write) is performed on one or more word lines in a corresponding TLC block, device 100 (via, for example, processor 122, logic and circuitry in memory array 116, second tracking mechanism 154, or a combination thereof) can simultaneously manipulate (e.g., write to) proxy access groups 162 in a QLC block. Following manipulation, second tracking mechanism 154 can directly measure the storage characteristics (e.g., charge loss) of proxy access groups 162 using first measurement mechanism 156, thereby generating proxy measurement 164. Second tracking mechanism 154 further calculates translated measurement 168 based on processing proxy measurement 164 according to translation mechanism 168. Translated measurement 168 can be a mapping or estimate of the state of data in a target second type cell 134 (e.g., TLC) using measured characteristics of the corresponding first type cell 132 (e.g., QLC). Translation mechanism 168 can include processes, equations, lookup tables, or the like that reflecting predetermined relationships or connections between charge loss patterns across different cell types. In other words, translation mechanism 168 can be configured to provide a charge loss estimate associated with the measurable charge loss at the cell with the first BPC under the same conditions (e.g., holding time) for the cell with the second BPC.

[0033] In some embodiments, whenever a read is required at a second type cell 134, device 100 may use translation mechanism 168 to derive and use access adjustment 158. For example, device 100 may (1) perform a measurement of proxy access group 162 using first measurement mechanism 156, (2) translate the measurement results into translated measurements 166 for a set of target TLCs, (3) derive access adjustment 158 ​​(e.g., read level voltage offset) based on translated measurements 166, and (4) apply access adjustment 158, all in response to a read command targeting a TLC cell.

[0034] In other embodiments, device 100 may track a second trace list 170 according to update trigger 172 (e.g., a predetermined timing or condition). The second trace list 170 may contain translated measurements 166 of a set of second-type blocks. Measurements of the second trace list 170 may be updated according to update trigger 172. For updates, similar to the first trace list 154, the device may measure the corresponding proxy access group 162, perform translation, and store the resulting translated measurements 166 and / or access adjustments 158. In response to a read command targeting second-type unit 134, device 100 may access the second trace list 170 to derive or calculate the access adjustment 158 ​​of the target unit and use the resulting access adjustment 158 ​​to perform a read operation.

[0035] Figure 3 This is an example translation mechanism 168 according to an embodiment of the present technology. Translation mechanism 168 can be recognized for use with... Figure 1 The target on-state voltage (VPASS) 302 is grouped according to different values ​​of the proxy measurement 164 or corresponding charge loss levels. For each box or VPASS value, the translation mechanism 168 can identify various access adjustments 158 based on a predetermined voltage range or corresponding bit value. Therefore, the device 100 can use the translation mechanism 168 (e.g., as a lookup table) to determine the appropriate measurement output 403. Figure 1 Translated measurement 166, access adjustment 168 or both.

[0036] In some embodiments, the translation mechanism 168 may include a reflection Figure 1 The translation measurement 166, access adjustment 168, or both are internally adjusted. Therefore, the translation mechanism 168 can be used to directly calculate or output the adjusted access level based on the measurement output 403.

[0037] Figure 4 It is a storage state measurement according to embodiments of the present technology (e.g., Figure 1 The first measurement mechanism (156) is explained. Figure 4This may describe the steps taken to implement the first measurement mechanism 156 or the details for implementing the first measurement mechanism 156. In other words, the first measurement mechanism 156 includes direct measurement of the target unit (e.g., Figure 1 Details or steps related to one or more aspects of charge loss in the first type unit 132).

[0038] When directly measuring one or more aspects, the first measurement mechanism 156 can be configured, for example, by incrementally increasing... Figure 1 The access packet voltage 402 of the target access packet 140 varies (e.g., word line voltage, read level voltage, or the like). Figure 1 Device 100 (via, for example) Figure 1 Processor 122, Figure 1 The logic circuitry, software instructions or routines, firmware, or a combination thereof in the memory array 116 can determine the measurement output 403 as the voltage level of the access block voltage 402 that satisfies predetermined conditions. For example, when calibration enable 404 is active, when initially reading or interfering with stored data, when the calibration register value 406 changes, or when series current 408 (e.g., flowing through...) Figure 1 The current of access group 140; I string When a predetermined threshold is reached, when a predetermined duration has elapsed, or similar, device 100 can detect and record the access group voltage 402. Measurement output 403 can correspond to the recorded data. Figure 1 The results of the first measurement mechanism 156 in the first tracking list 154 and Figure 3 The VPASS 302. Furthermore, the measurement output 403 can correspond to a direct measurement. Figure 1 Proxy access group 162 Figure 1 The proxy measurement is 164.

[0039] In some embodiments, the first measurement mechanism 156 may comprise a series of stages or portions. For example, the first measurement mechanism 156 may begin after establishing an initial state 412, such as by setting bit lines to predetermined levels (e.g., analog source voltage levels), setting word lines to voltage source levels (e.g., VCC), or a combination thereof. Subsequently, the first measurement mechanism 156 may implement an initial ramp-up portion 414, which incrementally increases the access packet voltage 402 according to an initial step size 415 (e.g., a predetermined increment and / or duration) until a measurement minimum 422 is reached. During the initial ramp-up portion 414, one or more bit lines may be pre-charged.

[0040] Once the access group voltage 402 reaches the measurement minimum 422, the first measurement mechanism 156 can implement the measurement section 416. The measurement section 416 can be synchronized with the active state of calibration enable 404.

[0041] During measurement phase 416, device 100 may incrementally increase access packet voltage 402 by measurement step size 417 (e.g., a predetermined increment and / or duration), which differs from the initial step size 415 in voltage and / or duration. For example, the initial step size 415 may have a relatively large voltage increment and a short duration to shorten the duration for establishing the measurement minimum 422 at access packet voltage 402. In contrast, measurement step size 417 may have a smaller voltage increment and / or a longer duration than the initial step size 415 to provide finer measurement granularity and / or sufficient measurement duration to increase measurement accuracy.

[0042] While iteratively / incrementally increasing the access group voltage 402, device 100 can monitor measurement conditions. Measurement conditions may correspond to read conditions or similar changes in the electrical balance of access group 140 and its corresponding cells. Measurement conditions may be represented by a change in calibration register value 406 and / or the series current 408 reaching a threshold level. Device 100 can detect the level of access group voltage 402 during measurement conditions. Device 100 can store the detected level as a measurement output 403.

[0043] In some embodiments, device 100 may continue to increase the access block voltage 402 after a measurement condition has been met. For example, device 100 may continue measuring portion 416 until the access block voltage 402 reaches an adjusted access level 424. Device 100 may access a predetermined lookup table to determine an offset value corresponding to the measurement output 403 while continuing to incrementally increase the measurement portion 416. Thus, device 100 may (e.g., while incrementally increasing the measurement portion 416) dynamically calculate the adjusted access level 424 as a combination of the determined offset value and the measurement output 403. When the voltage reaches or exceeds the adjusted access level 424, device 100 may stop the incremental increase of the measurement portion 416 and the access block voltage 402. Alternatively, device 100 may issue an interrupt to reset the access block voltage 402, for example, in response to an error condition or other reset condition.

[0044] Device 100 may implement full sensing portion 418 after measurement portion 416. During full sensing portion 418, device 100 may prepare for sensing, for example, by operating a sensing amplifier, to detect the amount of charge stored in the corresponding memory cell. After full sensing portion 418, device 100 may reset access packet voltage 402 and other related conditions and return to a reset state (e.g., before T0).

[0045] In other embodiments, device 100 may implement the first measurement mechanism 156 by applying a voltage pulse and measuring the response at the memory cell. For example, device 100 may determine that Vt is greater than the number of bits / memory cells to which the voltage pulse is applied. Therefore, device 100 may determine the highest Vt that can be used to calculate measurement output 403.

[0046] As described in further detail herein, device 100 may use the first measurement mechanism 156 for the second tracking mechanism 160. Device 100 may identify proxy access groups 162 associated with one or more target TLC blocks. For example, device 100 selects a dummy word line with QLC mode in the target TLC block. Device 100 may determine the measurement output 403 of the dummy word line (e.g., proxy measurement 164 representing charge loss) and translate the measurement output 403 according to the translation mechanism 168. Figure 1 The translated measurement 166 is used to update the read offset bin adjustment of the target TLC block (e.g., Figure 1 Access adjustment 158). In some embodiments, device 100 may update the read offset bin without evaluating timers (e.g., timers used to track the duration elapsed since the last write / refresh), temperature, or both.

[0047] In some embodiments, the device 100 can use a start-up-based method. Figure 1 Update trigger 172. For example, update trigger 172 may initiate a first measurement mechanism 156 during read error handling, media scanning, periodic scanning, or the like.

[0048] Figure 5 This describes an operating device (e.g., according to embodiments of the present technology) Figure 1 The flowchart illustrates an example method 500 (including the device 100, memory system 102, memory controller 114, memory array 116, and / or other circuitry). Method 500 can be used (via, for example...) Figure 1 The processor 122, the logic within the memory array 116, other logic circuits, or combinations thereof are implemented. Figure 1 The calibration mechanism 150 includes Figure 1 The second tracking mechanism 160. In other words, method 500 can be used to calculate and / or track the target unit (e.g., Figure 1 The first type of unit 132, containing QLC (e.g.) Figure 1 The charge loss of the less dense second-type cells 134 (e.g., TLC) and the translated measurement of the corresponding storage state 166.

[0049] At frame 502, device 100 can be determined. Figure 1The first type of cell 132 is a proxy group. As an illustrative example, the memory array 116 (e.g., a flash memory array) may include the first type of cell 132 and the second type of cell 134. In some embodiments, the first type of cell 132 and the second type of cell 134 may be contained within a block. The memory block may contain the second type of cell 134 configured to store a reduced number of BPCs smaller than their maximum BPC. For example, the memory block may contain QLC second type of cell 134, which is dynamically configured (e.g., "in operation" or during the deployment and use of the memory array 116) to store three or fewer bits, thereby operating as TLC, MLC, or SLC. Compared to a larger or maximum bit density configuration, the device 100 may operate the block at a reduced storage density to reduce operation time (e.g., write and read durations). For example, the device 100 may utilize the second type of cell 134 to intermittently store data, similar to a cache memory.

[0050] Given a higher capacity default configuration, device 100 may include a configuration to track charge loss of cells operating under a BPC (e.g., maximum capacity). Figure 1 The first tracking mechanism 152. Device 100 can maintain the first type unit 132 as... Figure 1 The proxy access group 162 is used to model the charge loss of the second type of cells 134 within the same block. For example, within the block, device 100 (via, for example, processor 122, one or more logic circuits in memory array 116, or a combination thereof) may identify a group of cells (along, for example, a dummy or proxy word line) to continue operating as high / maximum storage capacity and to serve as proxy access group 162. In contrast, the remaining cells (e.g., second type of cells 134) may store content or payload data and / or be connected to other / individual word lines. The identification of the proxy group allows the first tracking mechanism 152 to track or estimate the charge loss of the second type of cells 134 within the same block over time (e.g., degradation of accessible data or content data within the block).

[0051] In other embodiments, the memory block may include reserved word lines. Device 100 may utilize reserved word lines as first type cells 132 and proxy access groups 162. For example, device 100 may implement proxy access groups 162 by programming memory cells connected to the reserved word lines into QLC mode. Thus, device 100 may use reserved word lines to track charge loss using a first tracking mechanism 152.

[0052] At block 504, device 100 may populate a proxy group (e.g., first type cell 132 or proxy access group 162). For example, device 100 may populate proxy access group 162 by storing predetermined data values ​​to establish an initial state for tracking and observing charge loss over time. In some embodiments, device 100 may populate proxy access group 162 when a corresponding memory block (e.g., a first word line therein) is written to or refreshed.

[0053] At box 506, device 100 can identify triggering events used to estimate charge loss. For example, device 100 can identify... Figure 1 The update trigger 172 is satisfied. When the trigger event is identified, device 100 may implement a first tracking mechanism 152 to ultimately calculate and generate an estimated charge loss of the memory block (e.g., the second type cell 134 therein) and the appropriate adjustment amount necessary to access the stored data in its degraded state. In some embodiments, device 100 may initiate charge loss estimation during a read error handling process, media scan, periodic scan, or a combination thereof.

[0054] At box 508, device 100 can obtain a proxy measurement 164 that models the charge loss at the second type cell 134 (e.g., Figure 4 The measurement output 403. In other words, the device 100 can generate the measurement output 403 by implementing the first tracking mechanism 152 to operate directly on the first type cell 132 (e.g., the proxy access group 162 in the block). The obtained proxy measurement 164 may include or represent the charge loss (e.g., change or degradation away from the initial state) at the first type cell 132 over time.

[0055] Device 100 can be incrementally increased Figure 4 The access packet voltage 402 is used to obtain the proxy measurement 164. In some embodiments, the device 100 may incrementally increase the access packet voltage 402 on the proxy word line along with other (e.g., all) word lines in the memory block. The device 100 may use Figure 4 The initial step size of 415 is used to raise the word line voltage to Figure 4 The minimum measurement value is 422. Afterwards, device 100 can be used. Figure 4The measurement step size 417 is used to increase the word line voltage to exceed or exceed the measurement minimum 422. During the iterative / incremental increase, the device 100 may monitor one or more circuits in the memory array 116 to detect a predetermined reaction associated with the first type cell 132. In response to detecting the predetermined reaction, the device 100 may determine the corresponding voltage of the access block voltage 402 as a measurement output 403. The device 100 may use the measurement output 403 as a proxy measurement 164 to model or represent the charge loss at the second type cell 134 in the memory block. The device 100 may continue to incrementally increase the access block voltage 402 during and after the determination of the measurement output 403 and in parallel with other steps described below.

[0056] At box 510, device 100 can calculate translated measurement 166 based on surrogate measurement 164 (e.g., measurement output 403). For example, device 100 can use measurement output 403 as... Figure 1 The translation mechanism 168 takes input to calculate the translated measurement 166, which represents the relationship between the charge loss at the first type cell 132 and the charge loss at the second type cell 134. The translated measurement 166 may include an estimate of the charge loss at the second type cell 134.

[0057] At block 512, device 100 can derive access adjustment 158 ​​based on translated measurement 166. Device 100 can derive access adjustment 158 ​​to adjust the read level voltage of second type cell 134 to compensate for charge loss. Therefore, device 100 can derive access adjustment 158 ​​using the existing first tracking mechanism 152 without having to separately dedicate to tracking / estimating the charge loss of second type cell 134. For example, device 100 can derive access adjustment 158 ​​without or rather without tracking the storage duration dedicated to or additionally used for second type cell 134, such as without adjusting the temperature during storage at second type cell 134, and / or without directly measuring the charge loss at second type cell 134.

[0058] In some embodiments, method 500 may combine the steps described in blocks 510 and 512 into a single step. For example, translation mechanism 168 may internally include an access adjustment 158 ​​that translates the measurement 166 and directly outputs a measurement output 403 suitable for measurement output 403.

[0059] At block 514, device 100 can access data stored at second-type unit 134 using access adjustment 158. Device 100 can calculate adjusted access level 424 based on the combination of address adjustment 158 ​​and translated measurement 166. In some embodiments, translation mechanism 168 may internally include translated measurement 166 and access adjustment 158, thereby directly outputting adjusted access level 424 based on measurement output 403.

[0060] Device 100 can use an adjusted access level 424 to read from the second type cell 134. In some embodiments, the word line voltage increment can continue beyond the determination of the measurement output 403. During or in parallel with this increment, device 100 can perform necessary calculations for the adjusted access level 424. In effect, device 100 can increase the word line voltage of the second type cell 134 to the adjusted access level 424. Device 100 can use the adjusted access level 424 to operate a sense amplifier to read from the second type cell 134.

[0061] Figure 6 This is a schematic view of a system including a device according to an embodiment of the present technology. (See above references) Figures 1 to 5 Any of the aforementioned devices (e.g., memory devices) can be incorporated into any of numerous larger and / or more complex systems, a representative example of which is... Figure 6 System 680 is schematically shown in the figure. System 680 may include a memory device 600, a power supply 682, a driver 684, a processor 686, and / or other subsystems or components 688. The memory device 600 may include features substantially similar to those of the device described above with reference to one or more figures, and therefore may include various features for executing direct read requests from a host device. The resulting system 680 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative systems 680 may include, but are not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. Components of system 680 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of system 680 may also include remote devices and any of a wide variety of computer-readable media.

[0062] As will be understood from the foregoing, specific embodiments of the present technology have been described herein for illustrative purposes, but various modifications may be made without departing from this disclosure. Furthermore, certain aspects of the new technology described in the context of a particular embodiment may be combined or omitted in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments necessarily exhibit such advantages to fall within the scope of the present technology. Therefore, this disclosure and related technologies may cover other embodiments not explicitly shown or described herein.

[0063] In the embodiments described above, the device has been described in the context of a NAND flash memory device. However, as a supplement to or alternative to a NAND flash memory device, the device configured according to other embodiments of the present technology may also include other types of suitable storage media, such as devices incorporating NOR-based non-volatile storage media (e.g., NAND flash memory), magnetic storage media, phase-change storage media, ferroelectric storage media, dynamic random access memory (DRAM) devices, etc.

[0064] As used herein, the term "processing" includes manipulating signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, calculating results, executing instructions, assembling, transmitting, and / or manipulating data structures. The term "data structure" includes information arranged as bits, words or codewords, blocks, files, input data, system-generated data (e.g., calculated or generated data), and program data. Furthermore, as used herein, the term "dynamic" describes processes, functions, actions, or executions that occur during the operation, use, or deployment of the corresponding device, system, or embodiment, and after or concurrently with the running of manufacturer's or third-party firmware. Dynamic processes, functions, actions, or executions may occur after design, manufacturing, and initial testing, setup, or configuration.

[0065] The above embodiments have been described in sufficient detail to enable those skilled in the art to make and use them. However, those skilled in the art will understand that the technology may have additional embodiments and may be practiced without referring to certain details of the embodiments described above with reference to one or more of the figures.

Claims

1. A memory device comprising: A memory array comprising non-transient rewritable memory cells grouped into blocks and configured to store charges representing stored data. The memory block is configured to include second-type cells, each designated to store a second number of bits, the second-type cells being configured to store accessible data, and The memory block includes word lines configured as first type cells, each of which is specified to store a first number of bits greater than the second number of bits, and the first type cells are configured as proxies for modeling charge loss in the second type cells; and Logic circuitry coupled to the memory array and configured to: The first type of memory cell is filled with predetermined data values ​​to observe charge loss over time, wherein the first type of memory cell is filled to indicate the storage state of the second type of memory cell; The measurement output is obtained directly from the operation on the first type of unit; The translated measurements of the second type of unit are calculated using the measurement output and translation mechanism. The translated measurement includes an estimate of the charge loss at the second type of cell, and The translation mechanism described therein represents the relationship between the charge loss at the first type of cell and the charge loss at the second type of cell; and Access adjustments are derived based on the translated measurements, wherein the access adjustments are used to adjust the read level voltage to take into account the charge loss at the second type cell when reading from the second type cell.

2. The memory device of claim 1, wherein the second type of cell is a three-level cell (TLC) and the first type of cell is a four-level cell (QLC).

3. The memory device according to claim 1, wherein the second type cell (1) has a maximum storage capacity greater than the first number of bits and (2) is dynamically configured to store a capacity less than the maximum capacity to reduce write time compared to the first type cell.

4. The memory device of claim 1, wherein the logic circuitry is configured to obtain the measurement output and calculate the translated measurement during a read error handling process, a media scan, a periodic scan, or a combination thereof.

5. The memory device of claim 1, wherein the logic circuitry is configured to derive the access adjustment, (1) without tracking the storage duration at the second type cell, (2) without directly measuring the charge loss at the second type cell, and (3) without adjusting the temperature, or a combination thereof.

6. A method of operating a memory device, the memory device comprising rewritable memory cells configured to store charges representing stored data, the method comprising: A first type of memory cell configured to have a first storage density is identified, wherein the first type of memory cell is configured as a proxy for a second type of memory cell having a second storage density; The first type of memory cell is filled with predetermined data values ​​to observe charge loss over time; The measurement output is obtained directly from the operation on the first type of cell, wherein the measurement output reflects the charge loss at the first type of cell; Based on the measurement output and translation mechanism, the translated measurement is calculated, wherein the translation mechanism maps the measured charge loss at the first type of cell to the estimated charge loss at the second type of cell; and Access adjustments are derived based on the translated measurements, wherein the access adjustments are used to adjust the read level voltage of the second type of cell.

7. The method of claim 6, wherein obtaining the measurement output comprises: Incrementally increase the access packet voltage on the first type of cell; The measurement output is determined as the access group voltage that causes a predetermined response associated with the first type of cell; The method further includes: The adjusted access level is calculated by combining the access adjustment with the translated measurement; and The second type of cell is read using the adjusted access level.

8. The method according to claim 7, wherein: The first type of unit and the second type of unit include memory blocks. The first type of unit is connected to the surrogate word line; Wherein the first storage density is the maximum storage density of the memory block; The second type of cell (1) is connected to a separate storage word line and (2) is dynamically configured to store a second storage density less than the maximum storage density; The access packet voltage is incrementally increased during and after the determination of the measurement output, and while calculating the translated measurement, deriving the access adjustment, and calculating the adjusted access level; Reading the second type of unit includes: Simultaneously and incrementally increase the voltage on the memory word line with the access packet voltage; and The voltage at the storage word line is increased to at least the adjusted access level.

9. The method according to claim 8, wherein: The maximum storage density of the memory block is four bits per unit; and The second type of cell is a QLC that is dynamically configured to perform TLC operations to reduce read and write times.

10. The method of claim 7, wherein incrementally increasing the access packet voltage comprises: The access group voltage is increased to the minimum measured value based on the initial step size; and The access packet voltage is increased above the minimum measurement value by using a measurement step size that has a smaller value, a longer duration, or both compared to the first step length.

11. A memory device comprising: A rewritable memory cell is divided into blocks and configured to store charges representing stored data, the memory cell comprising a first type of cell and a second type of cell designated to store a different number of bits in each cell; and Logic circuitry coupled to the rewritable memory cell and configured to: A proxy access group is determined, comprising a set of first-type cells, the proxy access group being configured to model the charge loss of the second-type cells; The proxy access group is populated to establish an initial state for tracking the charge level at the second type of cell; The measurement output is obtained directly from the proxy access group, wherein the measurement output represents the charge loss over time from the initial state; and Using the measurement output, an access adjustment for reading the second type of cell is derived based on the translation of the measurement output to represent the estimated charge loss at the second type of cell.

12. The memory device according to claim 11, wherein: The rewritable memory unit is a flash memory unit; The second type of unit is a three-level cell (TLC); and The first type of unit is a four-level unit (QLC).

13. The memory device of claim 11, wherein the second type cell (1) has a maximum storage capacity greater than a first number of bits and (2) is configured to store a capacity less than the maximum capacity to reduce write time.

14. The memory device according to claim 13, wherein: The second type of unit includes a memory block and is dynamically configured to store a capacity smaller than the maximum capacity; and The proxy access group is a word line within the memory block configured as an operation of the first type of cell.

15. The memory device of claim 11, wherein the logic circuitry is configured to derive the access adjustment rather than (1) tracking the storage duration at the second type cell, (2) directly measuring the charge loss at the second type cell, (3) adjusting the temperature, or a combination thereof.

16. The memory device of claim 11, wherein the logic circuitry is configured to obtain the measurement output and calculate the translated measurement during a read error handling process, a media scan, a periodic scan, or a combination thereof.

17. The memory device of claim 11, wherein the logic circuitry is configured to: Incrementally increase the access packet voltage on the proxy access group; The measurement output is determined as the access group voltage that causes a predetermined response associated with the first type of cell; Based on the measurement output and translation mechanism, the translated measurement is calculated, and the translation mechanism maps the measured charge loss at the first type of cell to the charge loss estimate of the second type of cell; The access adjustment is derived based on the translated measurements; The adjusted access level is calculated by combining the access adjustment with the translated measurement; and The second type of cell is read using the adjusted access level.

18. The memory device according to claim 17, wherein: The first type of unit and the second type of unit include memory blocks. The proxy access group includes the first type of unit connected to the proxy word line; The first storage density is the maximum storage density of the memory block; The second type of cell (1) is connected to a separate storage word line and (2) is dynamically configured to store a second storage density less than the maximum storage density; The logic circuit is further configured to: During and after determining the measurement output, and in parallel with (1) calculating the translated measurement, (2) deriving the access adjustment of (1) and calculating the adjusted access level, the access group voltage continues to be increased incrementally; The second type of unit is read based on the following: Incrementally increase the voltage on the storage word line that matches the access packet voltage; and The voltage at the storage word line is increased to at least the adjusted access level.

19. The memory device according to claim 18, wherein: The maximum storage density of the memory block is four bits per unit; and The second type of cell is a QLC that is dynamically configured to store three or fewer bits per cell to reduce read and write times.

20. The memory device of claim 17, wherein the logic is further configured to incrementally increase the access packet voltage based on: The access group voltage is increased to the minimum measured value based on the initial step size; and The access packet voltage is increased above the minimum measurement value by using a measurement step size that has a smaller value, a longer duration, or both compared to the first step length.

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