3D DRAM with unenlarged trimming

Abstract

Embodiments of the present technology may include semiconductor processing methods and systems. Methods and systems may include providing a substrate to a processing region of a semiconductor processing chamber, wherein the substrate includes one or more pairs of alternating semiconductor material layers and sacrificial material layers. The method includes forming one or more vertically extending features through one or more pairs of alternating semiconductor material layers and sacrificial material layers, thereby forming one or more sidewalls having alternately exposed lateral ends of the semiconductor material layers and sacrificial material layers. The method includes forming a protective material layer on exposed lateral ends of the semiconductor material layer. The method includes laterally recessing at least a portion of the sacrificial material layer from the one or more vertically extending features and trimming a portion of the semiconductor material layer adjacent the one or more vertically extending features.

Description

[0001] This application claims priority to U.S. Patent Application No. 63 / 588,931, filed on October 9, 2023, entitled “3D DRAM WITH ENLARGE-LESSTRIM,” the entirety of which is incorporated herein by reference. Technical Field

[0002] This technology relates to semiconductor systems and processes. More specifically, this technology relates to three-dimensional (3D) dynamic random access memory (DRAM) devices (3D DRAM) and methods for forming such devices. Background Technology

[0003] Integrated circuits can be fabricated by creating intricately patterned material layers on a substrate surface. Creating patterned material on the substrate requires controlled methods for forming and removing exposed material. Material properties can affect device operation and also how the films are removed relative to each other. During formation and removal, material may be accidentally removed, potentially leading to wasted space within the device. As devices continue to shrink, the problem caused by this wasted area within the device becomes increasingly severe.

[0004] Therefore, there is a need for improved systems and methods for producing high-quality devices and structures. This technology can meet these and other needs. Summary of the Invention

[0005] This technology generally relates to semiconductor devices and methods of forming such devices. The method includes: providing a substrate to a processing region of a semiconductor processing chamber, wherein the substrate includes one or more pairs of alternating semiconductor material layers and sacrificial material layers. The method includes: forming one or more vertically extending features through the one or more pairs of alternating semiconductor material layers and sacrificial material layers. The method includes: forming one or more sidewalls having lateral ends with alternating exposure of semiconductor material layers and sacrificial material layers. The method includes: forming a protective material layer on the exposed lateral ends of the semiconductor material layers. The method includes: causing at least a portion of the sacrificial material layer to be laterally recessed from the one or more vertically extending features. The method includes: trimming a portion of the semiconductor material layer adjacent to the one or more vertically extending features.

[0006] In one embodiment, the method includes forming a protective material layer by selectively oxidizing or nitriding exposed lateral ends of a semiconductor material. In a further embodiment, the method includes laterally recessing a sacrificial material before forming the protective material layer. Furthermore, in another embodiment, the method further includes filling the laterally recessed portion of the sacrificial material with a dielectric material. Additionally or alternatively, the method includes removing the dielectric material before trimming. In more embodiments, the protective material layer is formed by directional deposition on exposed lateral ends of the semiconductor material. Further, in another embodiment, the thickness of the protective material layer is from about 5 Å to about 500 Å. In more embodiments, the semiconductor material layer is, as appropriate, doped silicon, and the sacrificial material layer includes silicon-germanium. In another embodiment, one or more vertically extending features have a first width before trimming the semiconductor material layer and a second width after trimming the semiconductor material layer, wherein the second width is about 10% or less larger than the first width. In a further embodiment, the thickness of the semiconductor material layer is about 400% or more greater than the thickness of the sacrificial material layer. In one embodiment, the method includes removing a protective material layer after trimming the semiconductor material layer.

[0007] This technology also relates generally to a semiconductor processing method. The method includes: providing a substrate to a processing region of a semiconductor processing chamber, wherein the substrate comprises alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials. The method includes: etching one or more access holes through the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials to expose lateral ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials. The method includes: wherein the etching forms one or more sidewalls, the one or more sidewalls having alternatingly exposed lateral ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials. The method includes: forming a protective material layer on the exposed lateral ends of the silicon-containing materials. The method includes: causing at least a portion of the silicon-and-germanium-containing materials to be laterally recessed from one or more access holes. The method includes: trimming a portion of the silicon-containing material adjacent to the access holes.

[0008] In one embodiment, the substrate comprises more than 20 pairs of alternating silicon-containing materials and silicon-and-germanium-containing materials. In more embodiments, the thickness of the silicon-and-germanium-containing materials is less than or about 30 nm. Further, in another embodiment, the thickness of the silicon-containing materials is about 400% or more greater than the thickness of the silicon-and-germanium-containing materials. Additionally or alternatively, in an embodiment, the method includes etching one or more vertically extending features at the ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials opposite to the exposed lateral ends, thereby exposing the outer ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials, wherein the etching removes at least a portion of the patterned stack and forms one or more outer walls having alternating exposed outer ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials. The method includes forming a second protective layer on the exposed outer ends of the silicon-containing materials. In an embodiment, the method includes laterally recessing at least a portion of the silicon-and-germanium-containing materials from one or more vertically extending features. And, in an embodiment, the method includes trimming a portion of the semiconductor material layer adjacent to the access hole.

[0009] In one embodiment, the method includes etching one or more vertically extending features at the ends of paired alternating silicon-containing material layers and silicon-and-germanium-containing material layers opposite to the exposed lateral ends, thereby exposing the outer ends of the paired alternating silicon-containing material layers and silicon-and-germanium-containing material layers. In further embodiments, the method includes wherein the etching removes at least a portion of the patterned stack and forms one or more outer sidewalls having alternately exposed outer ends of paired alternating silicon-containing material layers and silicon-and-germanium-containing material layers. In one embodiment, the method includes forming a second protective layer on the exposed outer ends of the silicon-containing material.

[0010] This technology also relates generally to a method for forming a three-dimensional dynamic random access memory (3D DRAM) device. The method includes: providing a substrate to a processing region of a semiconductor processing chamber, wherein the substrate includes one or more pairs of alternating silicon-containing material layers and silicon-and-germanium-containing material layers. The method includes: forming one or more access holes through the one or more pairs of alternating silicon-containing material layers and silicon-and-germanium-containing material layers to form one or more sidewalls, the one or more sidewalls including alternating exposed lateral ends of the silicon-containing material layers and silicon-and-germanium-containing material layers. The method includes: forming a protective material layer on the exposed lateral ends of the silicon-containing material layers. The method includes: causing at least a portion of the silicon-and-germanium-containing material layers to be laterally recessed from the one or more access holes. The method includes: trimming a portion of the silicon-containing material layer adjacent to the one or more access holes.

[0011] Such techniques offer numerous advantages over conventional systems and methods for forming 3D-DRAM devices. For example, by forming devices as discussed herein, only minor widening or even no widening of the access aperture is required to etch recesses within it, even when the access aperture defines a high aspect ratio structure. Therefore, the devices and methods discussed herein can provide increased recess dimensions, such as increased channel dimensions in the case of 3D DRAM. Embodiments of this technique, along with their numerous advantages and features, are described in more detail below with reference to the accompanying drawings. Attached Figure Description

[0012] The nature and advantages of the technology disclosed herein can be further understood by referring to the rest of the specification and the accompanying drawings.

[0013] Figure 1A A top plan view of an exemplary processing system according to some embodiments of the present technology is shown.

[0014] Figure 1B A schematic cross-sectional view of an exemplary processing system according to some embodiments of the present technology is shown.

[0015] Figure 2 The diagram illustrates the operation of exemplary methods of semiconductor processing according to some embodiments of the present technology.

[0016] Figures 3A to 3H A cross-sectional view of an exemplary semiconductor structure according to some embodiments of the present technology is shown.

[0017] Several figures are included for illustrative purposes only. It should be understood that these figures are for illustrative purposes only and should not be considered to be drawn to scale unless specifically stated otherwise. Furthermore, as schematic diagrams, these figures are intended to aid understanding and may not include all aspects or information compared to actual representations, and may include exaggerated material for illustrative purposes.

[0018] In the accompanying drawings, similar parts and / or features may have the same element symbol. Furthermore, parts of the same class may be distinguished by adding a letter after the element symbol (this letter distinguishes similar parts). If only the first element symbol is used in the description, then regardless of the letter, this description applies to any similar parts having the same first element symbol. Detailed Implementation

[0019] In dynamic random access memory (DRAM) devices such as 3D DRAM, alternating material layers can be formed on a substrate. These alternating material layers may include pairs of alternating silicon-containing materials and silicon-and-germanium-containing materials. As the number of layers increases, the challenges of feature formation also increase, at least in part due to the high aspect ratio of the device. For example, during 3D DRAM processing, vertically extending vias can be formed through two or more layers of material. Subsequent processing may require the removal of material extending horizontally away from the vias. Due to the lack of a line-of-sight of the vias, such horizontally extending recesses, referred to herein as “blind recesses,” are difficult to properly trim, especially as device dimensions continue to increase while larger aspect ratios in the formed features are desired. While 3D DRAM is used as an example of such blind recesses, it should be clear that these challenges are equally applicable to various devices having one or more blind recesses formed by the main channel.

[0020] Initial efforts to improve 3D DRAM devices included increasing the size of the SiGe layer compared to silicon. This allowed for the etching of all or part of the SiGe while retaining silicon. Thus, the controlled silicon layer and the etched portions could be controlled during layer deposition. However, such a structure was insufficient for high aspect ratio structures because only a certain percentage of SiGe could be present without causing mechanical failure. Attempts were made to reduce the germanium concentration without decreasing the SiGe layer thickness, but these attempts failed to achieve the germanium concentration required for selective etching compared to silicon. Attempts were made to utilize thinner SiGe layers than silicon and to trim the silicon recesses after SiGe removal. However, such efforts resulted in via recesses, adversely shortening the length of the semiconductor channel. In existing methods, the width of the vias can be more than doubled to trim acceptable channels. This phenomenon requires vias of insufficient width to properly trim blind recesses, or results in unacceptable dimensional losses, especially as devices continue to shrink.

[0021] Surprisingly, this technology has discovered that, through careful control of deposition and etching operations, excellent trimming can be achieved in one or more blind recesses without increasing the width of the access area (e.g., sidewalls). That is, controlled trimming of the sacrificial material can be achieved by carefully depositing one or more protective films, while only a small amount or no non-sacrificial material is removed. Therefore, devices formed according to this technology exhibit excellent dimensional control (e.g., in blind recesses) without sacrificing the quality of the trimmed sections.

[0022] Having described the general aspects of a chamber (in which plasma processing can be performed) configured to operate according to embodiments of the present technology, specific methods and component configurations may be discussed. It should be understood that the present technology is not intended to be limited to the specific films and processes discussed, as the techniques described herein can be used to improve many film formation processes and can be applied to various semiconductor processing chambers and operations.

[0023] Figure 1A This figure shows a top plan view of one embodiment of a processing system 10 comprising deposition, processing, etching, baking, and hardening chambers according to an embodiment. In the figure, a pair of front-opening unified transfer boxes 12 supply substrates of various sizes, which are received by a robotic arm 14 and placed into a low-pressure holding area 16, and then placed into one of semiconductor processing chambers 18a to 18f, which are arranged in series blocks 19a to 19c. A second robotic arm 11 can be used to transport substrate wafers from the holding area 16 to the semiconductor processing chambers 18a to 18f and back. The semiconductor processing chambers 18a to 18f can be assembled to perform multiple substrate processing operations, including the formation of stacks of semiconductor materials as described herein, as well as plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and other substrate processing (including plasma treatment, annealing, ashing, etc.).

[0024] Semiconductor processing chambers 18a to 18f may include one or more system components for depositing, plasma processing, hardening, and / or etching dielectrics or other films on a substrate. In one configuration, two pairs of semiconductor processing chambers (e.g., 18c to 18d and 18e to 18f) may be used to deposit dielectric material onto a substrate, and a third pair of semiconductor processing chambers (e.g., 18a to 18b) may be used to process the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 18a to 18f) may be configured to deposit and process alternating stacks of dielectric films on a substrate. Any one or more of the processes described herein may be performed in chambers separate from the manufacturing system, as shown in the various embodiments. It will be understood that other configurations for using system 10 as a chamber for the deposition, processing, etching, annealing, and hardening of dielectric films are conceivable.

[0025] Figure 1BA cross-sectional view of an exemplary semiconductor processing chamber 100 according to some embodiments of the present technology is illustrated. This figure illustrates an overview of a system that may incorporate one or more aspects of the present technology and / or may be specifically configured to perform one or more operations according to embodiments of the present technology. Additional details of the chamber 100 or the methods performed are further described below. According to some embodiments of the present technology, the chamber 100 can be used to form a tensile nitride film, although it is understood that the method can be similarly performed in any chamber in which film formation can occur. The semiconductor processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a cover assembly 106 coupled to the chamber body 102 and enclosing the substrate support 104 within a processing volume 120. A substrate 103 may be provided to the processing volume 120 via an opening 126, which conventionally uses a slit valve or door to seal the opening 126 for processing. During processing, the substrate 103 may be located on the surface 105 of the substrate support. As indicated by arrow 145, the substrate support 104 can rotate along axis 147, and the shaft 144 of the substrate support 104 can be located on axis 147. Alternatively, the substrate support 104 can be raised and rotated as needed during the deposition process.

[0026] A plasma distribution modulator 111 may be disposed in the semiconductor processing chamber 100 to control the plasma distribution across a substrate 103 disposed on a substrate support 104. The plasma distribution modulator 111 may include a first electrode 108 disposed adjacent to the chamber body 102 and separating the chamber body 102 from other components of the cover assembly 106. The first electrode 108 may be part of the cover assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be annular or ring-like components and may be a ring electrode. The first electrode 108 may be a continuous loop surrounding the processing volume 120 in the vicinity of the semiconductor processing chamber 100, or may be discontinuous at selected locations if necessary. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or may be a plate electrode, such as, for example, a secondary gas distributor.

[0027] One or more isolators 110a, 110b may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and from the chamber body 102. The isolators 110a, 110b may be dielectric materials, such as ceramics or metal oxides, for example, alumina and / or aluminum nitride. The gas distributor 112 may define an orifice 118 for dispensing process precursors into the processing volume 120. The gas distributor 112 may be coupled to a first power source 142, such as an RF generator, RF power source, DC power source, pulsed DC power source, pulsed RF power source, or any other power source that may be coupled to the semiconductor processing chamber. In some embodiments, the first power source 142 may be an RF power source.

[0028] The gas distributor 112 can be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 can also be formed from conductive or non-conductive components. For example, the body of the gas distributor 112 can be conductive, while the panel of the gas distributor 112 can be non-conductive. This can be achieved, for example, by... Figure 1B The first power source 142 shown supplies power to the gas distributor 112, or in some embodiments the gas distributor 112 may be grounded.

[0029] A first electrode 108 may be coupled to a first tuning circuit 128, which controls the ground path of the semiconductor processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or may include a variable capacitor or other circuit elements. The first tuning circuit 128 may be or may include one or more inductors 132. The first tuning circuit 128 may be any circuit that can implement variable or controllable impedance under plasma conditions present in the processing volume 120 during processing. In some embodiments shown, the first tuning circuit 128 may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B, which is series coupled to the first electronic controller 134. A second inductor 132B can be disposed between the first electronic controller 134 and a node that branches the first and second circuits, both of which are connected to the first electronic sensor 130. The first electronic sensor 130 can be a voltage or current sensor and can be coupled to the first electronic controller 134, which can provide a degree of closed-loop control for the plasma environment within the processing volume 120.

[0030] The second electrode 122 may be coupled to the substrate support 104. The second electrode 122 may be embedded within the substrate support 104 or coupled to the surface of the substrate support 104. The second electrode 122 may be any other distributed arrangement of a plate, perforated plate, mesh, wire mesh, or conductive element. The second electrode 122 may be a tuning electrode and may be coupled to a second tuning circuit 136 via a conduit 146, for example, a cable with a selected resistance (e.g., 50 ohms) disposed in a shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, the second electronic controller 140 being a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor and may be coupled to the second electronic controller 140 to provide further control over the plasma environment in the processing volume 120.

[0031] The third electrode 124 may be coupled to the substrate support 104, and the third electrode 124 may be a bias electrode and / or an electrostatic clamping electrode. The third electrode may be coupled to the second power source 150 via a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, pulsed RF source, or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power.

[0032] It can be used with any semiconductor processing chamber used for plasma or heat treatment. Figure 1B The cover assembly 106 and substrate support 104 are included. During operation, the semiconductor processing chamber 100 provides real-time control of the plasma environment within the processing volume 120. A substrate 103 can be disposed on the substrate support 104, and process gases can be flowed through the cover assembly 106 via inlet 114 according to any desired flow pattern. The gases can exit the semiconductor processing chamber 100 via outlet 152. A power supply can be coupled to a gas distributor 112 to create plasma within the processing volume 120. In some embodiments, a third electrode 124 can be used to subject the substrate to an electrical bias.

[0033] Once plasma is excited in processing volume 120, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. Electronic controllers 134 and 140 can then be used to adjust the flow properties of the ground path represented by the two tuning circuits 128 and 136. Setpoints can be transmitted to the first tuning circuit 128 and the second tuning circuit 136 to provide independent control over the deposition rate and the uniformity of plasma density from center to edge. In embodiments where the electronic controllers are variable capacitors, electronic sensors can adjust the variable capacitors to independently maximize the deposition rate and minimize thickness non-uniformity.

[0034] Each tuning circuit 128, 136 may have a variable impedance, which can be adjusted using corresponding electronic controllers 134, 140. When the electronic controllers 134, 140 are variable capacitors, the capacitance range of each variable capacitor, as well as the inductance of the first inductor 132A and the second inductor 132B, can be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, and may have a minimum value within the capacitance range of each variable capacitor. Therefore, when the capacitance of the first electronic controller 134 is at its minimum or maximum, the impedance of the first tuning circuit 128 may be high, resulting in a minimum aerial coverage or lateral coverage of the plasma shape above the substrate support. When the capacitance of the first electronic controller 134 approaches the value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma can grow to its maximum, effectively covering the entire working area of ​​the substrate support 104. When the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber wall, and the aerial coverage of the substrate support may decrease. The second electronic controller 140 may have a similar effect, which can increase or decrease the air coverage of plasma above the substrate support as the capacitance of the second electronic controller 140 changes.

[0035] Electronic sensors 130 and 138 can be used to tune corresponding circuits 128 and 136 in a closed loop. Depending on the type of sensor used, setpoints for current or voltage can be installed in each sensor, and the sensors can be equipped with control software that determines the adjustments to the corresponding electronic controllers 134 and 140 to minimize deviations from the setpoints. Thus, the plasma shape can be selected and dynamically controlled during processing. It should be understood that although the above discussion is based on electronic controllers 134 and 140 that can be variable capacitors, any electronic component with adjustable characteristics can be used to provide adjustable impedance for tuning circuits 128 and 136.

[0036] Figure 2The figures illustrate exemplary operations in a method 200 for forming a semiconductor structure according to embodiments of the present technology. Method 200 may include one or more operations prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the operations described herein. For example, the method may begin after the deposition of multiple layers, as in the production of 3D DRAM structures. However, as explained above, it is understood that the figures only illustrate one exemplary process in which the processes according to embodiments of the present technology may be employed, and this specification is not intended to limit the technology to this process or structure alone. Some or all of these operations may be performed in the chambers or systems described above, or some or all of these operations may be performed in different chambers on the same system tool, which may include chambers in which the operations of method 200 may be performed.

[0037] Prior to the commencement of the operations illustrated herein, method 200 may include additional operations. For example, additional processing operations may include forming a structure on a substrate, operations that may include forming and removing material. The prior processing operations may be performed in a chamber in which method 200 is performed, or may be performed in one or more other semiconductor processing chambers before transferring the substrate to a semiconductor processing chamber in which method 200 is performed. In any case, method 200 may, as appropriate, include transferring the substrate to a processing area of ​​a semiconductor processing chamber such as semiconductor processing chamber 100 described above, or to another chamber that may include the components described above. The substrate may be disposed on a substrate support, which may be a base such as substrate support 104, and may be located in the processing area of ​​the chamber, such as processing volume 120 described above. Method 200 may be described Figures 3A to 3H The operations shown in the illustration will be described in the operation description of method 200. Figures 3A to 3H The diagram is shown. It should be understood that... Figures 3A to 3H This is only a partial schematic diagram, and the substrate may contain any number of structural blocks having the aspects illustrated in the diagram, as well as alternative structural aspects that may still benefit from the operation of this technology. Nevertheless, as Figure 3A As shown, the semiconductor structure 300 may have multiple material layers deposited over the substrate 305. The semiconductor structure 300 may be formed of any number of materials, such as a substrate wafer or substrate made of silicon or silicon-containing materials, germanium, other substrate materials, and one or more materials that may be formed over the substrate during semiconductor processing.

[0038] like Figure 3AAs illustrated, substrate 305 can be any number of materials, such as a substrate wafer or substrate made of silicon or silicon-containing materials, germanium, other substrate materials, and one or more materials that can be formed on the substrate during semiconductor processing. In embodiments, substrate 305 may include a bulk substrate, an epitaxial growth substrate, and / or a silicon-on-insulator wafer. As used herein, the term "semiconductor substrate" refers to a substrate in which the entire substrate is composed of a semiconductor material. A semiconductor substrate may include any suitable semiconductor material and / or a combination of semiconductor materials used to form a semiconductor structure. For example, the semiconductor layer may comprise one or more materials, such as crystalline silicon (e.g., Si). <100> or Si <111> The semiconductor material may include silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 300 includes semiconductor materials such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 305 includes one or more of the following: silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although some examples of materials that can form substrates have been described herein, any material that can serve as the basis for passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) falls within the spirit and scope of this disclosure.

[0039] In embodiments, the semiconductor material may be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In embodiments, any suitable process, such as ion implantation, may be used to dope the substrate. As used herein, the term "n-type" refers to a semiconductor generated during manufacturing by doping an intrinsic semiconductor with an electron donor element. The term n-type derives from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the well (or hole). In contrast to an n-type semiconductor, a p-type semiconductor has a greater hole concentration than an electron concentration. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers.

[0040] In embodiments, the prior processing may form one or more materials on substrate 305. For example, in embodiments, the substrate may be pre-treated with alternating pairs of semiconductor materials 310 (which may be silicon-containing materials) and sacrificial materials 315 (which may be silicon- and germanium-containing materials), which is suitable for the formation of device 300 (such as a 3D DRAM structure). As illustrated in FIG4A, film stacks may be deposited on substrate 305. Film stacks may include multiple cell stacks (e.g., a three-cell stack in the illustrated example), portions of which are sacrificed for forming 3D DRAM cells. Obviously, this method forms three layers of 3D DRAM cells. In other examples, repeating the cell stacks of film stacks can form additional 3D DRAM cell layers. Furthermore, one example using cell stacks in film stacks can form a single 3D DRAM cell layer.

[0041] However, in embodiments, the pairs of alternating silicon-containing materials 310 and silicon- and germanium-containing materials 315 formed on the substrate may include more than 10 pairs of alternating silicon-containing materials 310 and silicon- and germanium-containing materials 315, such as more than 20 pairs, more than 30 pairs, more than 32 pairs, more than 34 pairs, more than 36 pairs, more than 38 pairs, more than 40 pairs, more than 44 pairs, more than 48 pairs, more than 50 pairs, more than 52 pairs, more than 56 pairs, more than 60 pairs, more than 64 pairs, more than 68 pairs, more than 72 pairs, or any range or value therein.

[0042] The thickness of each pair of alternating silicon and germanium materials 315 and silicon material 31 can be greater than or about 30 nm. In this way, sufficient space is provided to accommodate the insulator volume discussed below. Therefore, in embodiments, each pair can have a thickness greater than or about 35 nm, such as greater than or about 40 nm, greater than or about 45 nm, greater than or about 50 nm, greater than or about 55 nm, greater than or about 60 nm, greater than or about 65 nm, greater than or about 70 nm, greater than or about 75 nm, greater than or about 80 nm, greater than or about 85 nm, greater than or about 90 nm, greater than or about 95 nm, greater than or about 100 nm, or any range or value between these.

[0043] However, unlike previous units, this technology can provide an increased ratio of semiconductor material layers to sacrificial material layers. That is, the processes and methods discussed herein can provide a single, selective deposition and etching independent of the sacrificial layer. Therefore, due to the possibility of a reduced amount of weak sacrificial layer while maintaining the overall pair thickness required for robust insulator volume formation, the semiconductor structure 300 according to this technology can exhibit improved mechanical strength and stability.

[0044] In embodiments, the thickness of the semiconductor material may be about 10% or more greater than the thickness of the sacrificial material layer, such as about 20% or more, about 30% or more, about 40% or more, about 50% or more, about 60% or more, about 70% or more, about 80% or more, about 90% or more, about 100% or more, about 125% or more, about 150% or more, about 175% or more, about 200% or more, about 250% or more, about 300% or more, about 350% or more, about 400% or more, about 450% or more, about 500% or more, about 550% or more, about 600% or more, about 650% or more, about 700% or more, or any range or value between these values.

[0045] At least in part, due to the increased thickness of the semiconductor material, the doping content of the sacrificial layer is not particularly limited. For example, in embodiments where the sacrificial material is SiGe, the germanium content can range from about 1% to about 50% of the layer weight, such as less than or about 45%, less than or about 40%, less than or about 35%, less than or about 30%, less than or about 25%, less than or about 20%, less than or about 15%, less than or about 10%, less than or about 5%, or greater than or about 2.5%, greater than or about 5%, greater than or about 7.5%, greater than or about 10%, greater than or about 15%, greater than or about 20%, greater than or about 25%, greater than or about 30%, greater than or about 35%, greater than or about 40%, greater than or about 45%, or any range or value between these values, without negatively impacting the mechanical stability of the structure, at least in part due to the reduced thickness of the sacrificial material layer.

[0046] Regardless of the ratio of semiconductor layer 310 to sacrificial layer 315, such as Figure 3A As illustrated, the semiconductor device 300 may have an access via 325 formed therein. Although only one access via 325 is shown, it should be clear that more than one access via may be provided based on the device and device orientation. Nevertheless, the access via 325 may be formed through one or more cells of the semiconductor device 300 to provide access to the layers of the cells. In embodiments, the access via 325 may be formed by any method known in the art. For example, in embodiments, the access via 325 may be patterned using a mask 302 and then etched. As illustrated, the etching may be any etching suitable for extending through both the semiconductor material 310 and the sacrificial material 315.

[0047] like Figure 3BThe drawn, as appropriate, operation 205 may include lateral removal of a portion of the sacrificial material 315. By removing a portion of the sacrificial material, one or more additional deposition operations can be performed to form a protective layer 330. Figure 3C While one or more removal processes can be performed at operation 205 based on the selected semiconductor material and sacrificial material, in some embodiments, the etching process is a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process). In embodiments, the extent to which the sacrificial material 315 is laterally removed is controlled by the duration of the etching process. For example, in embodiments, the sacrificial material 315 may be laterally removed based on the desired length of the trench and isolation recess. In some embodiments, the selective wet etching process may include hydrofluoric acid (HF), fluoride (F2), or NH4OH etchant.

[0048] Although initial removal of the sacrificial material at operation 205 may be unnecessary in the embodiments, as will be discussed in more detail below, when utilizing this operation, it may be desirable to at least partially fill the formed recess 335 at operation 210, depending on the circumstances. For example, dielectric material can be filled into the recess 335 using one or more non-line of sight deposition methods such as atomic layer deposition (ALD) and / or chemical vapor deposition (CVD). In the embodiments, suitable dielectric materials may include silicon oxide, silicon nitride, combinations thereof, and other dielectrics known in the art.

[0049] By utilizing discretionary operation 210, the sidewalls of the access hole 325 can be oxidized at operation 215 to form a protective layer 330. That is, by utilizing discretionary fill operation 210, the protective layer 330 can be avoided from forming within the recess 335 and can therefore be formed on the vertically extending sidewalls 340 of the access hole 325. Furthermore, by utilizing discretionary fill operation 210, the protective layer 330 can be formed using sidewall oxidation or nitriding known in the art without requiring extensive processing. Moreover, after the protective layer 330 is formed, the dielectric material filled into the recess 335 can be easily removed by one or more selective etching processes, thereby allowing further processing without damaging the protective layer 330. However, in embodiments, one or more cleaning operations, such as Siconi™ cleaning, may be required to remove any surface oxides present prior to the formation of the protective layer 330.

[0050] However, as discussed above, in embodiments, the fill operation 210 may be unnecessary, depending on the circumstances. Instead, directional deposition can be used to deposit the protective layer 330 on the vertically extending sidewalls 340 of the access hole 325. While various deposition methods known in the art can be utilized, in embodiments, the directional deposition operation may include physical vapor deposition (PVD), ion beam deposition (IBD), electron beam (EB) deposition, electron beam ion-assisted deposition (EB-IAD), or a combination thereof. Nevertheless, the protective layer 330 may be formed of one or more materials, such as one or more of the dielectric materials discussed above. That is, by utilizing one or more directional deposition operations at operation 215, the protective layer 330 can be formed primarily on the sidewalls 340 of the access hole 325 due to the selection of one or more line-of-sight deposition methods. Therefore, very little or no protective layer 330 may be formed within the recess 335.

[0051] However, as discussed above, in embodiments, a protective layer 330 can be formed at operation 215 without removing a portion of the sacrificial material at operation 205 or filling the formed recess at operation 210. For example, in embodiments where the sacrificial material is not readily nitrided, as an example, the access hole 325 may undergo a nitriding operation at operation 215 to form a nitrogen-containing protective layer 330. For example, in this instance, the protective layer may comprise silicon nitride. However, it should be understood that one or more additional dielectric formation processes may be utilized based on the materials selected for the sacrificial material and the semiconductor material, provided that the dielectric can be formed on the semiconductor material 310 but not on the sacrificial material 315.

[0052] Although multiple methods are used to form the protective layer 330, the methods can be performed for a sufficient time to allow the protective layer to form a thickness greater than or about 5 Å, such as greater than or about 6 Å, such as greater than or about 7 Å, such as greater than or about 8 Å, such as greater than or about 9 Å, such as greater than or about 10 Å, such as greater than or about 15 Å, such as greater than or about 20 Å, such as greater than or about 30 Å, such as greater than or about 40 Å, such as greater than or about 50 Å, such as greater than or about 75 Å, such as greater than or about 100 Å, such as greater than or about 125 Å, such as greater than or about 150 Å, such as greater than or about 175 Å, such as greater than or about 200 Å, such as greater than or about 250 Å, such as greater than or about 300 Å, such as greater than or about 350 Å, such as greater than or about 400 Å, such as greater than or about 450 Å, such as greater than or about 500 Å, or any range or value between these. In this way, the protective layer 330 can have sufficient thickness to protect the sidewall 340 of the access hole 325 without hindering subsequent operations.

[0053] Therefore, regardless of whether a portion of the sacrificial material is removed in operation 205 or whether the formed recess is filled in operation 210, it is possible to achieve the desired result. Figure 3C A protective layer 330 is formed on the sidewall 340 (e.g., a vertically extending sidewall) of the drawn access hole 325. If operation 205 is not completed, or if filling occurs at operation 210, operation 220 may include lateral removal of sacrificial material from at least a portion of the recess 335, or removal of the dielectric material filling operation 210. In embodiments, lateral removal may include any one or more of the embodiments discussed above with respect to operation 205 as appropriate.

[0054] In this manner, an etching process specifically for the semiconductor material 310 can be performed in the finishing operation 225, such as... Figure 3D The drawing shows that, by utilizing the protective layer 330 discussed herein, an etching process specifically for the semiconductor material can be performed without reducing the width w of the access hole 325. Furthermore, as discussed above, surprisingly, such a process is also compatible with the relatively thin sacrificial material layer 315. For example, unlike conventional systems that only remove the sacrificial material to form a channel (e.g., the thickness of the sacrificial material layer determines the maximum thickness of the formed isolation recess 350), the semiconductor material is etched during trimming.

[0055] Furthermore, surprisingly, the protective layer 330 protects the vertically extending sidewalls 340 of the access hole 325 (e.g., the lateral edges of the formed channel) without inhibiting etching from the corresponding recess 335. Thus, the protective layer 330 advantageously allows etching from within the recess 335 formed due to the removal of sacrificial material, while preventing material removal from the lateral edges. In this manner, the width w of the access hole 325 can be maintained while allowing the channel 345 to be thinned, thereby forming a robust isolation recess 350.

[0056] For example, unlike conventional processing and devices, the width w of an access hole typically retains its original etched width. Therefore, in an embodiment, the width of the access hole after trimming operation 225 may be about 10% or less larger than the width of the access hole before trimming (e.g., an access hole formed by the mask and etching discussed above), such as about 9% or less, about 8% or less, about 7% or less, about 6% or less, about 5% or less, about 4% or less, about 3% or less, about 2% or less, about 1% or less, or any range or value between these. As will be understood, in an embodiment, some width may be lost due to one or more cleaning or removal operations, but most of the width is maintained during trimming.

[0057] Therefore, in embodiments, the method according to this technology can provide excellent channel 345 and isolation 350 thicknesses, while also exhibiting improved mechanical stability and increased channel length. For example, the channel width c can be less than or about 50 nm, such as less than or about 45 nm, such as less than or about 40 nm, such as less than or about 35 nm, such as less than or about 30 nm, such as less than or about 25 nm, such as less than or about 20 nm, or greater than or about 10 nm, such as greater than or about 12.5 nm, such as greater than or about 15 nm, such as greater than or about 17.5 nm, such as about 10 nm, or any range or value between these.

[0058] Furthermore, the isolation width I can be greater than or about 40 nm, such as greater than or about 45 nm, such as greater than or about 50 nm, such as greater than or about 55 nm, such as greater than or about 60 nm, or less than or about 100 nm, such as less than or about 95 nm, such as less than or about 90 nm, such as less than or about 85 nm, such as less than or about 80 nm, such as less than or about 75 nm, such as less than or about 70 nm, such as less than or about 65 nm, such as about 60 nm, or any range or value between these.

[0059] Surprisingly, the width w of the entry aperture can be less than 150 nm, such as less than or about 140 nm, such as less than or about 135 nm, such as less than or about 130 nm, such as less than or about 125 nm, such as less than or about 120 nm, such as less than or about 115 nm, such as less than or about 110 nm, such as less than or about 105 nm, such as less than or about 100 nm, such as less than or about 95 nm, such as less than or about 90 nm, or greater than or about 50 nm, such as greater than or about 55 nm, such as greater than or about 60 nm, such as greater than or about 65 nm, such as greater than or about 70 nm, such as greater than or about 75 nm, such as greater than or about 80 nm, such as greater than or about 85 nm, such as greater than or about 90 nm, such as greater than or about 95 nm, or any range or value in between.

[0060] like Figure 3E As drawn, in operation 230, the protective layer 330 can be removed after the isolation recess 350 has been trimmed to the desired size. The protective layer 330 can be removed by any suitable etching process, such as wet or dry etching. For example, when the protective layer 330 is silicon nitride, a thermal phosphoric acid etching process can be used to remove the protective layer 330.

[0061] After removing the protective layer 330, the semiconductor device 300 can typically re-enter a standard processing flow. For example, in an embodiment, a gate oxide 402, a diffusion barrier layer 404 (such as TiN in the embodiment), one or more gate metals 406, and one or more isolation layers 408 can be formed in the isolation recess 350, and one or more insulating dielectric materials 410 are formed in the access via 325, as can be drawn on... Figure 3F In this way, the capacitor of the semiconductor device 300 is formed in the formed isolation recess 350.

[0062] Surprisingly, however, the methods discussed herein can also be applied to forming transistors on opposite sides of the semiconductor device 300. Therefore, in an embodiment, one or more second access holes 425 may be formed on the outer surface 405 of the semiconductor device 300. Furthermore, a protective layer 430 may be formed along one or more sidewalls 440 of the one or more second access holes 425. And, in an embodiment, according to any one or more of the methods described above, any remaining portion of the sacrificial material 315 may be removed from the recess (if any).

[0063] By utilizing the protective layer 430, which can be formed according to any or more of the methods described above, the remaining portion of the isolation recess 350 can be selectively etched as discussed above, thereby providing the recess 470 to form one or more transistor components, such as Figure 3G The diagram is shown. Surprisingly, as discussed above, by utilizing the protective layer 430, the lateral edges of the channel 445 can be maintained while trimming the transistor recess 470 (e.g., trimming the recess 335 remaining after forming the isolation recess 350). Therefore, the channel length loss due to etching on the capacitor side or transistor side of the semiconductor device 300 may be minimal or even nonexistent.

[0064] Nevertheless, such as Figure 3H Once the desired channel width and / or isolation recess width have been achieved, the protective layer 430 can be removed using any one or more of the methods discussed above. In embodiments, the thickness can be any one or more of the thicknesses discussed above regarding channels, recesses, and access vias. After removing the protective layer 430, the semiconductor structure 300 can re-enter a standard processing flow to form the remainder of the transistor components and 3D DRAM capacitor components, in this instance, such as one or more source / drain regions 480, bit line 482 patterning and filling, electrode 484 formation, etc. However, as discussed herein, although 3D DRAM has been used as an example, it should be understood that the method of the present invention is suitable for forming one or more blind recesses in a variety of devices, including high aspect ratio devices.

[0065] In embodiments, forming the protective layer 330 / 430 may include one or more plasma precursors to the semiconductor structure 300. In embodiments, the deposition precursor may include at least one nitrogen-containing precursor, at least one oxygen-containing precursor, at least one silicon-containing precursor, a combination of the foregoing, and other dielectric precursors known in the art. The silicon-containing precursor may be or may include silanes and disilanes, and other silicon-containing precursors that can be used in semiconductor processing. The nitrogen-containing precursor may be or may include ammonia (NH3) and mixtures of molecular nitrogen and hydrogen (N2 + H2), and other nitrogen-containing precursors useful in semiconductor processing. The deposition precursor may also include at least one carrier gas. Examples of carrier gases may include molecular nitrogen (N2), helium, xenon, or argon, and other carrier gases useful in semiconductor processing. The oxygen-containing precursor may be any oxygen-containing material used or useful in semiconductor processing. For example, oxygen-containing precursors may be or may include vapor (H2O), molecular oxygen (O2), ozone (O3), nitrous oxide (N2O), hydrogen peroxide (H2O2), oxygen-containing plasma, alcohol compounds, or alcohol plasma.

[0066] Embodiments of method 200 may further include: at operation 215 to form a protective layer, and at operation 210, if applicable, generating a plasma effluent of a deposition precursor in a processing region of the semiconductor processing chamber. The deposition plasma can be generated by delivering plasma power to the deposition precursor that has flowed into the processing region. In some embodiments, the plasma power can be delivered by a radio frequency (RF) power source electrically coupled to at least one electrode within the semiconductor processing chamber. In embodiments, the RF power source can deliver power to at least one electrode, which generates an electric field in the processing region of the semiconductor processing chamber that energizes the deposition precursor to form a deposition plasma. The plasma power delivered to the deposition precursor may be less than or about 60 watts, less than or about 55 watts, less than or about 50 watts, less than or about 45 watts, less than or about 40 watts, less than or about 35 watts, less than or about 30 watts, or less. In a non-limiting example, the frequency of the RF power delivered to the deposition precursor may be 13.56 MHz. In some embodiments, plasma power can be continuously supplied to the deposition precursor, while in other embodiments, the plasma power can be pulsed. In pulsed embodiments, the delivered RF plasma power has a pulse frequency of less than or about 10 kHz, and can be less than or about 9 kHz, less than or about 8 kHz, less than or about 7 kHz, less than or about 6 kHz, less than or about 5 kHz, less than or about 4 kHz, less than or about 3 kHz, less than or about 2 kHz, less than or about 1 kHz, or less. In some pulsed embodiments, a shut-off portion of the plasma power duty cycle allows for greater diffusion of the plasma effluent in the deposited silicon and nitrogen-containing material. A longer diffusion time of the plasma effluent can result in a more uniform deposited material.

[0067] In embodiments, the deposition of multiple protective layers into the vias can be performed at deposition temperatures that affect the deposition rate of the material. For example, the processing region of a semiconductor processing chamber may be characterized by the following deposition temperatures: less than or about 550 °C, less than or about 500 °C, less than or about 475 °C, less than or about 450 °C, less than or about 425 °C, less than or about 400 °C, less than or about 375 °C, less than or about 350 °C, or less than or about 300 °C, or lower. By depositing at temperatures below or about 500 °C, this technique protects the device thermal budget.

[0068] In the foregoing description, numerous details have been set forth for illustrative purposes to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0069] Having disclosed several embodiments, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the present technology, several well-known processes and elements have not been described. Therefore, the above description should not be construed as limiting the scope of the present technology. Additionally, methods or processes may be described as performed sequentially or step-by-step, but it should be understood that operations may be performed simultaneously or in a different order than those listed.

[0070] Where range values ​​are provided, unless otherwise expressly specified herein, it should be understood that each intermediate value between the upper and lower limits of the range is also specifically disclosed, with precision to the smallest quantile of the lower limit unit. Any narrower range between any stated value or unstated intermediate value within the stated range and any other stated value or intermediate value within the stated range is also included. The upper and lower limits of this narrower range may be independently included in or excluded from this range, and each range in which any of the limits, no limit, or both limits are included is also covered by this technology, each range being governed by any specifically excluded limit in the stated range. Where the stated range includes one or both of these limitations, ranges excluding one or both of the included limitations are also included. When referring to measurable values ​​(such as quantities, durations, etc.), the terms “about” and / or “approximately” are used herein and in the claims to cover variations from ±20%, ±10%, ±5%, or ±0.1% of the specified value, as such variations are suitable for the systems, elements, circuits, methods, and other implementations described herein. When referring to measurable values, such as quantities, durations, physical properties (such as frequency), the term “substantially” as used herein and in the claims also covers variations from the specified value of ±20%, ±10%, ±5%, or ±0.1%, as such variations are suitable for the systems, elements, circuits, methods, and other implementations described herein.

[0071] As used herein and in the claims, unless expressly specified otherwise, the singular forms “a,” “the,” and “the” include plural expressions. Thus, for example, the expression “precursor” includes multiple such precursors, and the expression “the layer” includes references to one or more layers and equivalents known to those skilled in the art, etc.

[0072] Furthermore, when the terms “comprising,” “including,” “containing,” “containing,” and “having” are used in this specification and claims, they are intended to specify the presence of the stated features, integers, components, or operations, but such expressions do not exclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A semiconductor processing method, comprising the following steps: A substrate is provided to a processing area of ​​a semiconductor processing chamber, wherein the substrate comprises one or more pairs of alternating semiconductor material layers and sacrificial material layers; One or more vertically extending features are formed through the one or more pairs of alternating semiconductor material layers and sacrificial material layers, thereby forming one or more sidewalls, the one or more sidewalls including alternating exposed lateral ends of the semiconductor material layers and the sacrificial material layers; A protective material layer is formed on the exposed lateral end of the semiconductor material layer; At least a portion of the sacrificial material layer is laterally recessed from the one or more vertically extending features; as well as A portion of the semiconductor material layer adjacent to the one or more vertically extending features is trimmed.

2. The semiconductor processing method of claim 1, wherein the protective material layer is formed by selectively oxidizing or nitriding the exposed lateral ends of the semiconductor material.

3. The semiconductor processing method according to claim 1, wherein the sacrificial material is laterally recessed before forming the protective material layer.

4. The semiconductor processing method according to claim 3, further comprising the step of: filling the lateral recessed portion of the sacrificial material with a dielectric material.

5. The semiconductor processing method according to claim 4 further comprises the following step: removing the dielectric material before trimming.

6. The semiconductor processing method of claim 1, wherein the protective material layer is formed by directional deposition on the exposed lateral ends of the semiconductor material.

7. The semiconductor processing method according to claim 1, wherein the thickness of the protective material layer is from about 5 Å to about 500 Å.

8. The semiconductor processing method according to claim 1, wherein the semiconductor material layer is silicon material doped as appropriate, and the sacrificial material layer comprises silicon germanium.

9. The semiconductor processing method of claim 1, wherein the one or more vertically extending features have a first width before trimming the semiconductor material layer and a second width after trimming the semiconductor material layer, wherein the second width is about 10% or less larger than the first width.

10. The semiconductor processing method of claim 1, wherein the thickness of the semiconductor material is about 400% or more greater than the thickness of the sacrificial material layer.

11. The semiconductor processing method according to claim 1, further comprising the step of: removing the protective material layer after trimming the semiconductor material layer.

12. A semiconductor processing method, comprising the following steps: A substrate is provided to a processing area of ​​a semiconductor processing chamber, wherein the substrate comprises alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials. One or more access holes are etched through the pairs of alternating silicon-containing materials and silicon-and-germanium-containing materials to expose the lateral ends of the pairs of alternating silicon-containing materials and silicon-and-germanium-containing materials, wherein the etching forms one or more sidewalls, the one or more sidewalls comprising the alternately exposed lateral ends of the pairs of alternating silicon-containing materials and silicon-and-germanium-containing materials; A protective material layer is formed on the exposed lateral end of the silicon-containing material; At least a portion of the silicon and germanium-containing material is laterally recessed from the one or more inlet holes; as well as A portion of the silicon-containing material adjacent to the inlet hole is trimmed.

13. The semiconductor processing method of claim 12, wherein the substrate comprises more than 20 pairs of alternating silicon-containing materials and silicon- and germanium-containing materials.

14. The semiconductor processing method according to claim 12, wherein the thickness of the silicon and germanium-containing material is less than or about 30 nm.

15. The semiconductor processing method according to claim 12, wherein the thickness of the silicon-containing material is about 400% or more greater than the thickness of the silicon- and germanium-containing material.

16. The semiconductor processing method according to claim 12, further comprising the following steps: One or more vertically extending features are etched at the ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials opposite to the exposed lateral ends, thereby exposing the outer ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials, wherein the etching removes at least a portion of the alternating pairs and forms one or more outer sidewalls, the one or more outer sidewalls comprising the alternately exposed outer ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials; and A second protective layer is formed on the exposed outer end of the silicon-containing material.

17. The semiconductor processing method of claim 16, further comprising the step of: causing at least a portion of the silicon and germanium-containing material to be laterally recessed from the one or more vertically extending features.

18. The semiconductor processing method of claim 17, further comprising the step of: trimming a portion of the silicon-containing material adjacent to the access hole.

19. A method for forming a three-dimensional dynamic random access memory (3D DRAM) device, comprising the following steps: A substrate is provided to a processing area of ​​a semiconductor processing chamber, wherein the substrate comprises one or more pairs of alternating silicon-containing material layers and silicon- and germanium-containing material layers. One or more access holes are formed through the one or more pairs of alternating silicon-containing material layers and silicon- and germanium-containing material layers, thereby forming one or more sidewalls, the one or more sidewalls including the alternating exposed lateral ends of the silicon-containing material layers and the silicon- and germanium-containing material layers; A protective material layer is formed on the exposed lateral end of the silicon-containing material layer; At least a portion of the silicon and germanium-containing material layer is laterally recessed from the one or more access holes; as well as A portion of the silicon-containing material layer adjacent to the one or more access holes is trimmed.

20. The method of claim 19, further comprising the following steps: One or more vertically extending features are etched at the ends of the alternating pairs of silicon-containing material layers and silicon- and germanium-containing material layers opposite to the exposed lateral ends, thereby exposing the outer ends of the alternating pairs of silicon-containing material layers and silicon- and germanium-containing material layers, wherein the etching removes at least a portion of the alternating pairs and forms one or more outer sidewalls, the one or more outer sidewalls comprising the alternately exposed outer ends of the alternating pairs of silicon-containing material layers and silicon- and germanium-containing material layers; and A second protective layer is formed on the exposed outer end of the silicon-containing material.

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