Semiconductor device

Abstract

According to one embodiment, a semiconductor device includes a transistor region and a diode region. The transistor region includes: an n-type first silicon carbide region having a first portion in contact with the first surface; a plurality of p-type second silicon carbide regions; an n-type third silicon carbide region; a plurality of p-type fourth silicon carbide regions connecting the second silicon carbide regions; a first electrode; a second electrode; and a gate electrode. The diode region includes: an n-type first silicon carbide region having a second portion in contact with the first surface; a p-type fifth silicon carbide region; a plurality of p-type sixth silicon carbide regions connecting the fifth silicon carbide regions; a first electrode; and a second electrode. And a seventh silicon carbide region connecting the third silicon carbide region and the fifth silicon carbide region.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0002] Silicon carbide is one of the materials used in semiconductor devices. Compared with silicon, silicon carbide has excellent physical properties such as a band gap of about 3 times, a breakdown electric field strength of about 10 times, and a thermal conductivity of about 3 times. If these properties are effectively utilized, for example, it is possible to realize MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) that have high voltage withstand capability, low loss, and can operate at high temperatures.

[0003] Vertically oriented MOSFETs using silicon carbide have a pn junction diode as a built-in diode. For example, the MOSFET is used as a switching element connected to an inductive load. In this case, return current can flow even when the MOSFET is off, thanks to the built-in diode.

[0004] However, if a body diode is used to carry the return current, stacking defects will grow in the silicon carbide layer due to the recombination energy of the charge carriers, leading to an increase in the MOSFET's on-resistance. This increased on-resistance reduces the MOSFET's reliability. For example, by incorporating a unipolar Schottky barrier diode (SBD) into the MOSFET as a built-in diode, the growth of stacking defects in the silicon carbide layer can be suppressed. By incorporating an SBD into the MOSFET, the MOSFET's reliability is improved.

[0005] MOSFETs can sometimes experience sudden surge currents exceeding their steady-state condition. When a large surge current flows, the applied surge voltage generates heat, potentially damaging the MOSFET. The maximum permissible peak surge current value (I0) of a MOSFET is specified. FSM This is known as surge current withstand capability. In MOSFETs with SBD (Surge Divided MOSFETs), it is desirable to improve surge current withstand capability.

[0006] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2023-77119 Summary of the Invention

[0007] The technical problem that the invention aims to solve The technical problem to be solved by the present invention is to provide a semiconductor device with improved surge current tolerance.

[0008] Means for solving technical problems The semiconductor device of the embodiment includes a plurality of transistor regions and a plurality of diode regions alternately arranged in a first direction. Each transistor region includes: a silicon carbide layer having a first surface and a second surface facing the first surface; the silicon carbide layer includes: an n-type first silicon carbide region having a plurality of first portions connected to the first surface and extending in a second direction orthogonal to the first direction and arranged in the first direction; a plurality of p-type second silicon carbide regions disposed between the first silicon carbide region and the first surface, extending in the second direction and arranged in the first direction; an n-type third silicon carbide region disposed between the second silicon carbide region and the first surface; and a plurality of p-type fourth silicon carbide regions disposed between the first silicon carbide region and the first surface, arranged in the second direction, connecting adjacent second silicon carbide regions; a first electrode connected to the first portions, the second silicon carbide regions, the third silicon carbide region, and the fourth silicon carbide region; a second electrode connected to the second surface; and a plurality of gate electrodes connected to the second silicon carbide region. The diode region comprises: a silicon carbide layer comprising: an n-type first silicon carbide region having a plurality of second portions connected to the first surface and extending in the second direction; a plurality of p-type fifth silicon carbide regions disposed directly between the first silicon carbide region and the first surface, extending in the second direction and disposed in the first direction; a plurality of p-type sixth silicon carbide regions disposed between the first silicon carbide region and the first surface, disposed in the second direction, and connected between adjacent second silicon carbide regions; a first electrode connected to the second portions, the fifth silicon carbide regions, and the sixth silicon carbide regions; and a second electrode. The silicon carbide layer further comprises: a plurality of p-type seventh silicon carbide regions disposed between the first silicon carbide region and the first surface, disposed in the second direction, and connected between adjacent second silicon carbide regions and the fifth silicon carbide regions. Attached Figure Description

[0009] Figure 1 This is a schematic top view of the semiconductor device according to the first embodiment.

[0010] Figure 2 This is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0011] Figure 3 This is a schematic top view of a part of the semiconductor device according to the first embodiment.

[0012] Figure 4This is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0013] Figure 5 This is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0014] Figure 6 This is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0015] Figure 7 This is a schematic top view of a part of the semiconductor device according to the first embodiment.

[0016] Figure 8 This is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0017] Figure 9 This is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0018] Figure 10 This is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0019] Figure 11 This is a schematic top view of a part of the semiconductor device according to the first embodiment.

[0020] Figure 12 This is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0021] Figure 13 This is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0022] Figure 14 This is a schematic top view of the semiconductor device according to the first embodiment.

[0023] Figure 15 This is a schematic top view of the semiconductor device of the first comparative example.

[0024] Figure 16 This is a schematic cross-sectional view of the semiconductor device of the first comparative example.

[0025] Figure 17 This is the equivalent circuit diagram of the semiconductor device of the first comparative example.

[0026] Figure 18 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0027] Figure 19 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0028] Figure 20This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0029] Figure 21 This is a schematic top view of the semiconductor device of the third comparative example.

[0030] Figure 22 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0031] Figure 23 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0032] Figure 24 This is a schematic cross-sectional view of a semiconductor device of a first variation of the first embodiment.

[0033] Figure 25 This is a schematic cross-sectional view of a semiconductor device of a first variation of the first embodiment.

[0034] Figure 26 This is a schematic cross-sectional view of a part of the semiconductor device according to the second embodiment.

[0035] Figure 27 This is a schematic top view of a part of the semiconductor device according to the second embodiment.

[0036] Figure 28 This is a schematic cross-sectional view of a part of the semiconductor device according to the second embodiment.

[0037] Figure 29 This is a schematic top view of a part of the semiconductor device according to the second embodiment.

[0038] Figure 30 This is a schematic cross-sectional view of a part of the semiconductor device according to the second embodiment.

[0039] Figure 31 This is a schematic top view of a part of the semiconductor device according to the second embodiment. Detailed Implementation

[0040] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar parts will be labeled with the same reference numerals, and descriptions of parts that have been described once before will sometimes be omitted.

[0041] Additionally, in the following explanation, n + n, n - and p + p, p - The markings indicate the relative concentration of impurities in each conductivity type. That is, n + This indicates that the concentration of n-type impurities is relatively higher than that of n, n -This indicates that the concentration of n-type impurities is relatively lower than that of n. Additionally, p... + This indicates that the concentration of p-type impurities is relatively higher than that of p-type impurities. - This indicates that the concentration of p-type impurities is relatively lower than that of p-type impurities. Additionally, n-type impurities are sometimes also used. + type, n - The type is abbreviated as n-type, and p + Type, p - The type is abbreviated as p-type.

[0042] Impurity concentration can be measured, for example, using SIMS (Secondary Ion Mass Spectrometry). Furthermore, the relative level of impurity concentration can be determined, for example, based on the carrier concentration obtained using SCM (Scanning Capacitance Microscopy). Additionally, the depth, thickness, and other dimensions of the impurity region can be determined, for example, using images obtained from SEM (Scanning Electron Microscope) or through SIMS.

[0043] In this specification, unless otherwise stated, the impurity concentration of a semiconductor region refers to the maximum impurity concentration of the semiconductor region.

[0044] (First Implementation) The semiconductor device of the first embodiment includes a plurality of transistor regions and a plurality of diode regions alternately arranged in a first direction. Each transistor region includes: a silicon carbide layer having a first surface and a second surface opposite to the first surface; the silicon carbide layer includes: an n-type first silicon carbide region having a plurality of first portions connected to the first surface and extending in a second direction orthogonal to the first direction and arranged in the first direction; a plurality of p-type second silicon carbide regions disposed between the first silicon carbide region and the first surface, extending in the second direction and arranged in the first direction; an n-type third silicon carbide region disposed between the second silicon carbide region and the first surface; and a plurality of p-type fourth silicon carbide regions disposed between the first silicon carbide region and the first surface, arranged in the second direction, connecting adjacent second silicon carbide regions; a first electrode connected to the first portions, the second silicon carbide region, the third silicon carbide region, and the fourth silicon carbide region; a second electrode connected to the second surface; a plurality of gate electrodes opposite to the second silicon carbide regions, extending in the second direction and arranged in the first direction; and a gate insulating layer disposed between the gate electrodes and the second silicon carbide regions. The diode region includes: a silicon carbide layer comprising: an n-type first silicon carbide region having a plurality of second portions adjacent to a first surface and extending in a second direction; a plurality of p-type fifth silicon carbide regions disposed between the first silicon carbide region and the first surface, extending in the second direction and arranged in the first direction; and a plurality of p-type sixth silicon carbide regions disposed between the first silicon carbide region and the first surface, arranged in the second direction, connecting adjacent second silicon carbide regions; a first electrode adjacent to the second portions, the fifth silicon carbide regions, and the sixth silicon carbide regions; and a second electrode. The silicon carbide layer further includes: a plurality of p-type seventh silicon carbide regions disposed between the first silicon carbide region and the first surface, arranged in the second direction, connecting adjacent second silicon carbide regions and fifth silicon carbide regions.

[0045] The semiconductor device of the first embodiment is a planar gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the first embodiment is, for example, a Double Implantation MOSFET (DIMOSFET) with ion implantation forming the body region and source region. Furthermore, the semiconductor device of the first embodiment includes an SBD (Schottky Barrier Diode) as a built-in diode. The MOSFET 100 is a vertical n-channel MOSFET that uses electrons as charge carriers.

[0046] Figure 1 of (a) Figure 1 (b) is a schematic top view of the semiconductor device according to the first embodiment. Figure 1 (a) is a configuration diagram of the various regions of MOSFET100. Figure 1(b) is a diagram showing the pattern of electrodes and wiring on the upper surface of MOSFET100.

[0047] Figure 2 of (a) Figure 2 (b) is a schematic cross-sectional view of a portion of the semiconductor device of the first embodiment. Figure 3 This is a schematic top view of a part of the semiconductor device according to the first embodiment. Figure 4 , Figure 5 This is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0048] Figure 2 (a) is Figure 3 AA' section. Figure 2 (b) is Figure 3 BB' section. Figure 4 yes Figure 2 An enlarged schematic cross-sectional view of a portion of (a). Figure 5 yes Figure 2 Enlarged schematic cross-sectional view of part (b).

[0049] Figure 6 of (a) Figure 6 (b) is a schematic cross-sectional view of a portion of the semiconductor device of the first embodiment. Figure 7 This is a schematic top view of a part of the semiconductor device according to the first embodiment. Figure 8 , Figure 9 This is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0050] Figure 6 (a) is Figure 7 CC' section. Figure 6 (b) is Figure 7 DD' section. Figure 8 yes Figure 6 An enlarged schematic cross-sectional view of a portion of (a). Figure 9 yes Figure 6 Enlarged schematic cross-sectional view of part (b).

[0051] Figure 10 of (a) Figure 10 (b) is a schematic cross-sectional view of a portion of the semiconductor device of the first embodiment. Figure 11 This is a schematic top view of a part of the semiconductor device according to the first embodiment. Figure 12 , Figure 13 This is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0052] Figure 10 (a) is Figure 11EE' section. Figure 10 (b) is Figure 11 FF' section. Figure 12 yes Figure 10 An enlarged schematic cross-sectional view of a portion of (a). Figure 13 yes Figure 10 Enlarged schematic cross-sectional view of part (b).

[0053] like Figure 1 As shown in (a), the MOSFET 100 has multiple transistor regions 101, multiple diode regions 102 and a termination region 103.

[0054] Multiple transistor regions 101 and multiple diode regions 102 are alternately arranged in a first direction parallel to the first surface P1. A transistor region 101 is, for example, sandwiched between two diode regions 102 in the first direction. A diode region 102 is, for example, sandwiched between two transistor regions 101 in the first direction.

[0055] The width of transistor region 101 in the first direction ( Figure 1 (a) w1) is, for example, the width of diode region 102 in the first direction ( Figure 1 w2) in (a) is large.

[0056] exist Figure 1 In (a), an example is shown where two transistor regions 101 and three diode regions 102 are arranged in the first direction. However, the number of transistor regions 101 and diode regions 102 is not limited to that number.

[0057] A MOSFET and an SBD are provided in transistor region 101. An SBD is provided in diode region 102. No MOSFET is provided in diode region 102.

[0058] Termination region 103 surrounds transistor region 101 and diode region 102. A structure that increases the breakdown voltage of MOSFET 100 is provided in termination region 103. Such structures include, for example, reduced surface field (RESURF) and guard rings.

[0059] The MOSFET100 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, an interlayer insulating layer 20, a gate electrode pad 22, and a gate wiring 24.

[0060] Within the silicon carbide layer 10, n + Type 26, n drain region -Type 28 drift region (first silicon carbide region), p-type bulk region 30 (second silicon carbide region), n + The p-type source region 32 (third silicon carbide region), the p-type anode region 34 (fifth silicon carbide region), the p-type first bridging region 36 (fourth silicon carbide region), the p-type second bridging region 38 (sixth silicon carbide region), and the p-type third bridging region 40 (seventh silicon carbide region).

[0061] The drift region 28 comprises multiple first parts 28a and multiple second parts 28b.

[0062] Figure 2 of (a) Figure 2 of (b) Figure 3 , Figure 4 , Figure 5 This is a diagram representing transistor region 101.

[0063] like Figure 2 of (a) Figure 2 of (b) Figure 3 , Figure 4 , Figure 5 As shown, transistor region 101 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. Within the silicon carbide layer 10 of transistor region 101, there are n... + Type 26, n drain region - Type 28 drift region (first silicon carbide region), multiple p-type bulk regions 30 (second silicon carbide region), multiple n-type drift ... + The source region 32 (third silicon carbide region) of the p-type type and the first bridging region 36 (fourth silicon carbide region) of multiple p-type types.

[0064] in addition, Figure 3 Only the patterns of the drift region 28, the body region 30, the first bridging region 36, and the gate electrode 18 are shown.

[0065] In transistor region 101, source electrode 12, the first portion 28a of drift region 28, drain region 26, and drain electrode 14 constitute an SBD. Additionally, source electrode 12, body region 30, drift region 28, drain region 26, and drain electrode 14 constitute a pn junction diode.

[0066] A silicon carbide layer 10 is disposed between the source electrode 12 and the drain electrode 14. A silicon carbide layer 10 is disposed between the gate electrode 18 and the drain electrode 14. The silicon carbide layer 10 is single-crystal SiC. For example, the silicon carbide layer 10 is 4H-SiC.

[0067] The silicon carbide layer 10 has a first surface ( Figure 2 of (a) Figure 2 (b) "P1") and the second side ( Figure 2 of (a) Figure 2 (P2 in (b)). The first surface P1 is opposite the second surface P2. Hereinafter, the first surface will sometimes be referred to as the surface and the second surface as the back surface. In addition, hereafter, "depth" refers to the depth relative to the first surface.

[0068] The first face P1 is, for example, a face tilted at an angle of 0 degrees or more but less than 8 degrees relative to the (0001) face. The second face P2 is, for example, a face tilted at an angle of 0 degrees or more but less than 8 degrees relative to the (000-1) face. The (0001) face is called the silicon face. The (000-1) face is called the carbon face.

[0069] n + A drain region 26 of type n is disposed on the back side of the silicon carbide layer 10. The drain region 26 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 26 is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 the following.

[0070] n - A drift region 28 is disposed between the drain region 26 and the first surface P1. A drift region 28 is disposed between the source electrode 12 and the drain electrode 14. A drift region 28 is disposed between the gate electrode 18 and the drain electrode 14.

[0071] Drift region 28 is disposed on drain region 26. Drift region 28 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in drift region 28 is lower than that in drain region 26. The n-type impurity concentration in drift region 28 is, for example, 4 × 10⁻⁶. 14 cm -3 Above and 1×10 17 cm -3 The thickness of the drift region 28 is, for example, 5 μm or more and 150 μm or less.

[0072] The drift region 28 comprises multiple first portions 28a. The first portions 28a are connected to the first surface P1.

[0073] The first portion 28a extends in a second direction orthogonal to the first direction. The first portion 28a is repeatedly arranged in the first direction. The first portion 28a is sandwiched between two adjacent volume regions 30 in the first direction.

[0074] Part 28a functions as the n-type semiconductor region of the SBD.

[0075] A p-shaped volume region 30 is disposed between the drift region 28 and the first surface P1. The volume region 30 extends in the second direction. The volume region 30 is repeatedly arranged in the first direction.

[0076] A portion of the body region 30 functions as the channel region of the MOSFET 100. The body region 30 also functions as the p-type semiconductor region of the pn junction diode.

[0077] The body region 30 includes, for example, a low-concentration region and a high-concentration region. The high-concentration region is located between the low-concentration region and the first surface P1. The p-type impurity concentration in the high-concentration region is higher than that in the low-concentration region.

[0078] Body region 30, for example, contains aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in body region 30 is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 1×10 21 cm -3 Furthermore, the p-type impurity concentration in the body region 30 is defined by the p-type impurity concentration at a location half the depth of the body region 30.

[0079] The depth of the body region 30 is, for example, greater than 0.3 μm and less than 1.0 μm.

[0080] The potential of the body region 30 is fixed at the source electrode 12.

[0081] n + A source region 32 is disposed between the body region 30 and the first surface P1. The source region 32 extends, for example, in a second direction.

[0082] Source region 32 contains, for example, phosphorus (P) as an n-type impurity. The concentration of n-type impurities in source region 32 is higher than that in drift region 28.

[0083] The n-type impurity concentration in source region 32 is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 The depth of the source region 32 is shallower than the depth of the bulk region 30. The depth of the source region 32 is, for example, 0.1 μm or more and 0.3 μm or less.

[0084] The first bridging region 36 of the p-type is disposed between the drift region 28 and the first surface P1. The first bridging region 36 is repeatedly configured in the second direction.

[0085] The first bridging region 36 connects two adjacent volume regions 30 in the first direction. The first bridging region 36 extends, for example, in the first direction. The first bridging region 36 intersects, for example, with the volume region 30. The first bridging region 36 overlaps, for example, with the volume region 30.

[0086] The first bridging region 36 divides the first portion 28a extending in the second direction. The first bridging region 36 connects two adjacent body regions 30 separated by the n-type first portion 28a through a p-type silicon carbide region.

[0087] The distance in the second direction between two adjacent first bridging regions 36 in the second direction ( Figure 3 dx in the figure is, for example, less than the width of the transistor region 101 in the first direction. Figure 1 (w1 in (a)). The distance dx in the second direction between two adjacent first bridging regions 36 is, for example, more than 10 μm and less than 200 μm.

[0088] The width of the second direction of the first bridging region 36 ( Figure 3 (wx) for example, is less than the first distance in the first direction of the two adjacent first parts 28a ( Figure 2 of (a) Figure 3 d1 in the first bridging region 36, the width of the second direction ( Figure 3 (wx) is, for example, the first distance in the first direction between two adjacent first parts 28a. Figure 2 of (a) Figure 3 Less than half of d1 in the middle.

[0089] The first distance d1 in the first direction between two adjacent first portions 28a is, for example, more than 3 μm and less than 30 μm. The width wx in the second direction of the first bridging region 36 is, for example, more than 1 μm and less than 10 μm.

[0090] The first bridging region 36, for example, contains aluminum (Al) as a p-type impurity. The p-type impurity concentration in the first bridging region 36 is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 1×10 21 cm -3 the following.

[0091] The p-type impurity concentration of the first bridging region 36 is substantially the same as that of the bulk region 30. Furthermore, the p-type impurity concentration of the first bridging region 36 is defined by the p-type impurity concentration at a location half the depth of the first bridging region 36.

[0092] The depth of the first bridging region 36 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the first bridging region 36 is, for example, substantially the same as the depth of the volume region 30.

[0093] The potential of the first bridging region 36 is fixed to the potential of the source electrode 12.

[0094] In addition, Figure 3 The example shown illustrates the case where two first bridging regions 36 are configured in the second direction, but there can also be three or more first bridging regions 36.

[0095] A gate electrode 18 is disposed on the first surface P1 side of the silicon carbide layer 10. The gate electrode 18 extends in a second direction parallel to the first surface P1 and orthogonal to the first direction. Multiple gate electrodes 18 are arranged parallel to each other in the first direction. The gate electrode 18 has a so-called stripe shape.

[0096] The gate electrode 18 is a conductive layer. The gate electrode 18 is, for example, polysilicon containing p-type or n-type impurities.

[0097] The gate electrode 18 is, for example, opposite to the portion of the body region 30 that is in contact with the first surface P1. The gate electrode 18 is, for example, opposite to the portion of the drift region 28 that is in contact with the first surface P1.

[0098] A gate insulating layer 16 is disposed between the gate electrode 18 and the body region 30. The gate insulating layer 16 is disposed between the gate electrode 18 and the drift region 28.

[0099] The gate insulating layer 16 is, for example, silicon oxide. The gate insulating layer 16 can, for example, be made of a high-k insulating material (a high dielectric constant insulating material).

[0100] An interlayer insulating layer 20 is disposed on the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 20 is disposed between the gate electrode 18 and the source electrode 12. The interlayer insulating layer 20 is, for example, silicon oxide.

[0101] The source electrode 12 is disposed on the first surface P1 side of the silicon carbide layer 10. The source electrode 12 is connected to the first surface P1.

[0102] The source electrode 12 is connected to the first part 28a of the drift region 28, the body region 30, the source region 32 and the first bridging region 36.

[0103] The source electrode 12 contains a metal. The metal forming the source electrode 12 is, for example, a stacked structure of titanium (Ti) and aluminum (Al).

[0104] The portion of the source electrode 12 that connects to the body region 30, the source region 32, and the first bridging region 36 is, for example, a metal silicide. The metal silicide may be, for example, a titanium silicide or a nickel silicide. The portion of the source electrode 12 that connects to the first portion 28a of the drift region 28 may not have a metal silicide.

[0105] The junction between the body region 30, the source region 32, and the first bridging region 36 and the source electrode 12 is, for example, an ohmic junction. The junction between the first portion 28a of the drift region 28 and the source electrode 12 is, for example, a Schottky junction.

[0106] The drain electrode 14 is disposed on the second surface P2 side of the silicon carbide layer 10. The drain electrode 14 is connected to the second surface P2. The drain electrode 14 is connected to the drain region 26.

[0107] The drain electrode 14 is, for example, a metal or a metal semiconductor compound. The drain electrode 14 may contain at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag) and gold (Au).

[0108] The connection between the drain region 26 and the drain electrode 14 is, for example, an ohmic connection.

[0109] Figure 6 of (a) Figure 6 of (b) Figure 7 , Figure 8 , Figure 9 This is a diagram representing diode region 102.

[0110] like Figure 6 of (a) Figure 6 of (b) Figure 7 , Figure 8 , Figure 9 As shown, diode region 102 includes a silicon carbide layer 10, a source electrode 12 (first electrode), and a drain electrode 14 (second electrode). The silicon carbide layer 10 of diode region 102 contains n... + Type 26, n drain region - The drift region 28 (first silicon carbide region), multiple p-type anode regions 34 (fifth silicon carbide region), and p-type second bridging region 38 (sixth silicon carbide region).

[0111] also, Figure 7 Only the patterns of drift region 28, anode region 34, and second bridging region 38 are shown.

[0112] In diode region 102, source electrode 12, the second portion 28b of drift region 28, drain region 26, and drain electrode 14 constitute an SBD. Additionally, source electrode 12, anode region 34, drift region 28, drain region 26, and drain electrode 14 constitute a pn junction diode.

[0113] The drift region 28 contains multiple second parts 28b. The second parts 28b are connected to the first surface P1.

[0114] The second part 28b extends in the second direction. The second part 28b is repeated in the first direction. The second part 28b is sandwiched between two adjacent anode regions 34 in the first direction.

[0115] Part 28b functions as the n-type semiconductor region of the SBD.

[0116] The p-type anode region 34 is disposed between the drift region 28 and the first surface P1. The anode region 34 functions as the p-type semiconductor region of the pn junction diode.

[0117] The anode region 34 includes, for example, a low-concentration portion and a high-concentration portion. The high-concentration portion is located between the low-concentration portion and the first surface P1. The p-type impurity concentration in the high-concentration portion is higher than that in the low-concentration portion.

[0118] Anode region 34 may contain aluminum (Al) as a p-type impurity. The concentration of p-type impurity in anode region 34 may be, for example, 1 × 10⁻⁶. 16 cm -3 Above and 1×10 21 cm -3 Furthermore, the p-type impurity concentration in the anode region 34 is defined by the p-type impurity concentration at a location half the depth of the anode region 34.

[0119] The width of the anode region 34 in the first direction ( Figure 7 (wb) For example, the width of the first direction of the volume region is greater than 30.

[0120] The depth of the anode region 34 is substantially the same as the depth of the bulk region 30. The depth of the anode region 34 is, for example, 0.3 μm or more and 1.0 μm or less.

[0121] The potential of the anode region 34 is fixed at that of the source electrode 12.

[0122] The second bridging region 38 of the p-shape is disposed between the drift region 28 and the first surface P1. The second bridging region 38 is repeatedly configured in the second direction.

[0123] The second bridging region 38 connects two adjacent anode regions 34 in the first direction. The second bridging region 38 extends, for example, in the first direction. The second bridging region 38 intersects, for example, with the anode region 34. The second bridging region 38 overlaps, for example, with the anode region 34.

[0124] The second bridging region 38 divides the second portion 28b extending in the second direction. The second bridging region 38 connects two adjacent anode regions 34 that are separated by the n-type second portion 28b through a p-type silicon carbide region.

[0125] The distance in the second direction between two adjacent second bridging regions 38 ( Figure 7 (dy) is, for example, less than the width of the transistor region 101 in the first direction ( Figure 1 (w1 in (a)). The distance dy between the two adjacent second bridging regions 38 in the second direction is, for example, more than 10 μm and less than 200 μm.

[0126] The width of the second bridging region 38 in the second direction ( Figure 7 (wy) for example, is less than the width in the first direction of the anode region 34 ( Figure 7 The width of the second bridging region 38 in the second direction (wb). Figure 7 The width of the anode region 34 in the first direction is, for example, wy. Figure 7 Less than half of the wb in the middle.

[0127] Additionally, the width of the second bridging region 38 in the second direction ( Figure 7 (wy) for example, the second distance in the first direction between two adjacent second parts 28b ( Figure 6 of (a) Figure 7 The width of the second direction of the second bridging region 38 is smaller than d2. Figure 7 (wy) is, for example, the second distance in the first direction between two adjacent second parts 28b. Figure 6 Less than half of d2 in (a).

[0128] The second distance d2 in the first direction between two adjacent second portions 28b is, for example, more than 3 μm and less than 30 μm. The width wy in the second direction of the second bridging region 38 is, for example, more than 1 μm and less than 10 μm.

[0129] The second distance in the first direction between two adjacent second parts 28b ( Figure 6 of (a) Figure 7 d2 in the example is the first distance in the first direction of the two adjacent first parts 28a ( Figure 2 d1) in (a) are essentially equal.

[0130] The second bridging region 38, for example, contains aluminum (Al) as a p-type impurity. The p-type impurity concentration in the second bridging region 38 is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 1×10 21 cm -3 the following.

[0131] The p-type impurity concentration in the second bridging region 38 is substantially the same as that in the anode region 34. The p-type impurity concentration in the second bridging region 38 is substantially the same as that in the first bridging region 36. Furthermore, the p-type impurity concentration in the second bridging region 38 is defined by the p-type impurity concentration at a location half the depth of the second bridging region 38.

[0132] The depth of the second bridging region 38 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the second bridging region 38 is, for example, substantially the same as the depth of the anode region 34. The depth of the second bridging region 38 is, for example, substantially the same as the depth of the first bridging region 36.

[0133] The potential of the second bridging region 38 is fixed to the potential of the source electrode 12.

[0134] In addition, Figure 7 The example shows two second bridging regions 38 configured in the second direction, but there can also be three or more second bridging regions 38.

[0135] The source electrode 12 is disposed on the first surface P1 side of the silicon carbide layer 10. The source electrode 12 is connected to the first surface P1.

[0136] The source electrode 12 is connected to the second part 28b of the drift region 28, the anode region 34 and the second bridging region 38.

[0137] The portion of the source electrode 12 that connects to the body region 30, the anode region 34, and the second bridging region 38 is, for example, a metal silicide. The metal silicide may be, for example, a titanium silicide or a nickel silicide. The portion of the source electrode 12 that connects to the second portion 28b of the drift region 28 may not have a metal silicide.

[0138] The connection between the anode region 34 and the second bridging region 38 and the source electrode 12 is, for example, an ohmic connection. The connection between the second portion 28b of the drift region 28 and the source electrode 12 is, for example, a Schottky connection.

[0139] Figure 10 of (a) Figure 10 of (b) Figure 11 , Figure 12 , Figure 13This is a diagram showing the boundary between transistor region 101 and diode region 102.

[0140] like Figure 10 of (b) Figure 11 as well as Figure 13 As shown, the silicon carbide layer 10 at the boundary between transistor region 101 and diode region 102 includes a p-type third bridging region 40 (seventh silicon carbide region).

[0141] The third bridging region 40 of the p-type is disposed between the drift region 28 and the first surface P1. The third bridging region 40 is repeatedly configured in the second direction.

[0142] The third bridging region 40 connects the adjacent body region 30 and anode region 34 in the first direction.

[0143] The third bridging region 40 divides the drift region 28 extending in the second direction in the first surface. The third bridging region 40 connects the adjacent body region 30, which is separated from the n-type drift region 28, to the anode region 34 through the p-type silicon carbide region.

[0144] The third bridging region 40 is connected, for example, to the first bridging region 36 and the second bridging region 38. The first bridging region 36, the second bridging region 38 and the third bridging region 40 are continuous, for example, in a first direction.

[0145] The distance in the second direction between two adjacent third bridging regions 40 ( Figure 11 The dz value in the transistor region 101 is, for example, smaller than the width in the first direction. Figure 1 (w1 in (a)). The distance dz between the two adjacent third bridging regions 40 in the second direction is, for example, more than 10 μm and less than 200 μm.

[0146] The width of the third bridging region 40 in the second direction ( Figure 11 (wz) for example, is less than the second distance in the first direction of the two adjacent second parts 28b ( Figure 11 (d2 in the middle). The second distance d2 in the first direction between two adjacent second parts 28b is, for example, more than 3 μm and less than 30 μm. The width wz in the second direction of the third bridging region 40 is, for example, more than 1 μm and less than 10 μm.

[0147] The third bridging region 40, for example, contains aluminum (Al) as a p-type impurity. The p-type impurity concentration in the third bridging region 40 is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 1×10 21 cm -3 the following.

[0148] The p-type impurity concentration in the third bridging region 40 is substantially the same as, for example, the p-type impurity concentration in the body region 30 and the anode region 34. The p-type impurity concentration in the third bridging region 40 is substantially the same as, for example, the p-type impurity concentration in the first bridging region 36. The p-type impurity concentration in the third bridging region 40 is substantially the same as, for example, the p-type impurity concentration in the second bridging region 38. Furthermore, the p-type impurity concentration in the third bridging region 40 is defined by the p-type impurity concentration at a location half the depth of the third bridging region 40.

[0149] The depth of the third bridging region 40 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the third bridging region 40 is, for example, substantially the same as the depth of the body region 30 and the anode region 34. The depth of the third bridging region 40 is, for example, substantially the same as the depth of the first bridging region 36. The depth of the third bridging region 40 is, for example, substantially the same as the depth of the second bridging region 38.

[0150] The potential of the third bridging region 40 is fixed to the potential of the source electrode 12.

[0151] In addition, Figure 11 The example shown illustrates the case where two third bridging regions 40 are configured in the second direction, but there can also be more than three third bridging regions 40.

[0152] The source electrode 12 is disposed on the first surface P1 side of the silicon carbide layer 10. The source electrode 12 is connected to the first surface P1.

[0153] The source electrode 12 is connected to the third bridging region 40.

[0154] The portion of the source electrode 12 that connects to the third bridging region 40 is, for example, a metal silicide. The metal silicide may be, for example, a titanium silicide or a nickel silicide.

[0155] The connection between the third bridging region 40 and the source electrode 12 is, for example, an ohmic connection.

[0156] Figure 14 This is a schematic top view of the semiconductor device according to the first embodiment. Figure 14 It is a diagram showing the pattern of the volume region 30 projected onto the first surface P1 and the pattern of the anode region 34 projected onto the first surface P1. Figure 14 The pattern of the body region 30 and the pattern of the anode region 34 are patterns projected onto the first surface P1 in a direction perpendicular to the first surface P1.

[0157] In addition, Figure 14 In the process, the area where the first bridging region 36 intersects with the body region 30 is also identified as the body region 30. In addition, the area where the second bridging region 38 intersects with the anode region 34 is also identified as the anode region 34.

[0158] The occupancy of the anode region 34 projected onto the first surface P1 per unit area is greater than that of the volume region 30 projected onto the first surface P1 per unit area. In other words, within a region of a specified size, the occupancy of the anode region 34 projected onto the first surface P1 is greater than that of the volume region 30 projected onto the first surface P1. That is, the occupancy ratio of pn junction diodes in diode region 102 is greater than that of pn junction diodes in transistor region 101.

[0159] The occupancy rate of the anode region 34 projected onto the first surface P1 is, for example, more than 1.2 times and less than 3 times the occupancy rate of the volume region 30 projected onto the first surface P1.

[0160] The aforementioned unit area is not particularly limited as long as it is a size that allows for comparison of the average occupancy of the body region 30 of the transistor region 101 and the average occupancy of the anode region 34 of the diode region 102. For example, the aforementioned unit area is 30μm × 30μm = 900μm. 2 .

[0161] Furthermore, the contact area per unit area between the source electrode 12 and the anode region 34 in diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in transistor region 101. That is, the contact resistance per unit area between the source electrode 12 and the anode region 34 in diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in transistor region 101.

[0162] Next, the function and effects of the MOSFET 100 in the first embodiment will be explained.

[0163] Figure 15 of (a) Figure 15 (b) is a schematic top view of the semiconductor device of the first comparative example. Figure 15 (a) is a configuration diagram of the regions of the MOSFET of the first comparative example. Figure 15 (b) is a diagram showing the pattern of the electrodes and wiring on the upper surface of the MOSFET of the first comparative example. Figure 15 of (a) Figure 15 (b) is the same as the first embodiment. Figure 1 of (a) Figure 1 The diagram corresponding to (b).

[0164] Figure 16 This is a schematic cross-sectional view of the semiconductor device of the first comparative example. Figure 16 yes Figure 15 (a) is a cross-sectional view of transistor region 101. Figure 16 It is the same as the first embodiment. Figure 2 The diagram corresponding to (a).

[0165] The MOSFET of the first comparative example differs from the MOSFET 100 of the first embodiment in that it does not have a diode region 102.

[0166] In the transistor region 101 of the MOSFET in the first comparative example, the MOSFET and SBD are arranged in the same manner as in the MOSFET 100 of the first embodiment.

[0167] Figure 17 This is the equivalent circuit diagram of the semiconductor device of the first comparative example. Between the source electrode 12 and the drain electrode 14, a pn junction diode and an SBD are connected in parallel with the transistor as built-in diodes.

[0168] For example, consider the case where a MOSFET is used as a switching element connected to an inductive load. When the MOSFET is off, due to the load current caused by the inductive load, a voltage that is positive relative to the drain electrode 14 may be applied to the source electrode 12. In this case, a forward current flows through the built-in diode. This state is also known as the reverse conduction state.

[0169] The forward voltage (Vf) at which forward current begins to flow in the SBD is lower than the forward voltage (Vf) of the pn junction diode. Therefore, initially, forward current flows in the SBD.

[0170] The forward voltage (Vf) of an SBD is, for example, 1.0V. The forward voltage (Vf) of a pn junction diode is, for example, 2.5V.

[0171] The SBD operates as a single pole. Therefore, even if a forward current flows through it, stacking defects will not grow in the silicon carbide layer 10 due to the recombination energy of the charge carriers.

[0172] Figure 18 of (a) Figure 18 (b) is an explanatory diagram of the operation and effect of the semiconductor device according to the first embodiment. Figure 18 of (a) Figure 18 (b) is a schematic cross-sectional view of the first comparative example. Figure 18 of (a) Figure 18 (b) is with Figure 16 The corresponding diagram.

[0173] Figure 18 of (a) Figure 18 (b) is a graph showing the current flowing through the built-in diode of the MOSFET in the first comparative example. Figure 18 (a) indicates the state where the forward current flows only through the SBD. Figure 18(b) indicates the state of forward current flowing through the SBD and pn junction diodes.

[0174] Right now, Figure 18 (a) indicates a state where the voltage applied between the pn junctions of a pn junction diode is lower than the forward voltage (Vf) of the pn junction diode. Additionally, Figure 18 (b) indicates a state in which the voltage applied between the pn junctions of a pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0175] exist Figure 18 of (a) Figure 18 In (b), the dashed arrow represents the current flowing through the SBD. Figure 18 In (b), the solid arrow represents the current flowing through the pn junction diode.

[0176] like Figure 18 As shown in (a), the current flowing through the SBD winds around to the bottom of the body region 30. Therefore, an electrostatic potential propagates in the drift region 28, which is opposite to the bottom of the body region 30. This propagation of the electrostatic potential reduces the voltage applied between the body region 30 and the drift region 28.

[0177] Therefore, at the bottom of the body region 30, it is difficult to exceed the forward voltage (Vf) of the pn junction diode. In other words, compared with the case where the SBD is not provided, the forward voltage (Vf) of the pn junction diode of the MOSFET of the first comparative example can be increased. Therefore, the bipolar operation of the pn junction diode is suppressed, and the formation of stacking defects in the silicon carbide layer 10 due to the recombination energy of charge carriers is suppressed.

[0178] The forward voltage (Vf) of the pn junction diode of the MOSFET in the first comparative example depends on the spacing between two adjacent SBDs in the first direction. By reducing the spacing between two adjacent SBDs in the first direction, the forward voltage (Vf) of the pn junction diode of the MOSFET in the first comparative example can be increased.

[0179] MOSFETs sometimes momentarily exceed their steady-state and are subjected to large surge currents. The surge current flows from the source electrode 12 to the drain electrode 14.

[0180] When a large surge current flows through, a large surge voltage is applied, causing overheating and damage to the MOSFET. The maximum permissible peak surge current value (I0) of a MOSFET is specified. FSM This is known as surge current withstand capability. In MOSFETs with SBD (Surge Divided MOSFETs), it is desirable to improve surge current withstand capability.

[0181] When a large surge voltage is applied to the MOSFET of the first comparative example, the voltage applied between the pn junctions of the pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0182] When the voltage applied between the pn junctions of a pn junction diode is higher than the forward voltage (Vf) of the pn junction diode, such as Figure 18 As shown in (b), current also flows through the pn junction diode.

[0183] Figure 19 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment. Figure 19 This is a schematic cross-sectional view of the second comparative example. Figure 19 It is compared with the first example. Figure 16 The corresponding diagram.

[0184] The second comparative example MOSFET differs from the first comparative example MOSFET in that it does not contain an SBD in the transistor region. The built-in diode of the second comparative example MOSFET is only a pn junction diode.

[0185] Figure 20 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment. Figure 20 This is a graph showing the voltage and current characteristics of the built-in diodes of the MOSFET in the first comparative example and the MOSFET in the second comparative example.

[0186] like Figure 20 As shown, in the second comparative example, the MOSFET flows through the pn junction diode when a voltage greater than or equal to the forward voltage Vf2 of the pn junction diode is applied. On the other hand, in the first comparative example, the MOSFET flows through the SBD before a forward voltage Vf1 is applied to the pn junction diode. In the first comparative example, the MOSFET flows through the pn junction diode when a voltage greater than or equal to the forward voltage Vf1 is applied.

[0187] The MOSFET in the first comparative example operates unipolar before the forward voltage Vf1, therefore the current increase slope is smaller than that of the MOSFET in the second comparative example. Therefore, the maximum allowable peak current value I of the MOSFET in the second comparative example is... FSM 2. In comparison, the maximum allowable peak current value I of the MOSFET in the first comparative example FSM 1. Smaller. In other words, the surge current tolerance of the MOSFET in the first comparative example is smaller than that of the MOSFET in the second comparative example.

[0188] Figure 21 This is a schematic top view of the semiconductor device of the third comparative example. Figure 21 It is the same as the first embodiment. Figure 11The corresponding diagram.

[0189] The difference between the MOSFET of the third comparative example and the MOSFET 100 of the first embodiment is that the silicon carbide layer 10 does not include the first p-type bridging region 36 (fourth silicon carbide region), the second p-type bridging region 38 (sixth silicon carbide region), and the third p-type bridging region 40 (seventh silicon carbide region).

[0190] The MOSFET of the third comparative example, like the MOSFET 100 of the first embodiment, includes a diode region 102 arranged alternately with the transistor region 101. By including the diode region 102, the surge current tolerance of the MOSFET of the third comparative example is improved. This will be described in detail below.

[0191] Figure 22 of (a) Figure 22 (b) is an explanatory diagram of the operation and effect of the semiconductor device according to the first embodiment. Figure 22 of (a) Figure 22 (b) is a schematic cross-sectional view of the MOSFET of the third comparative example. Figure 22 of (a) Figure 22 (b) is the same as the first embodiment. Figure 10 The diagram corresponding to (a) shows that the MOSFET of the third comparative example has the same characteristics as that of the first embodiment. Figure 10 The structure shown in (a) is the same as the structure shown in the diagram.

[0192] Figure 22 of (a) Figure 22 (b) is a graph showing the current flowing through the built-in diode of the MOSFET in the third comparative example. Figure 22 (a) indicates the state where the forward current flows only through the SBD. Figure 22 (b) indicates the state of forward current flowing through the SBD and pn junction diodes.

[0193] Right now, Figure 22 (a) indicates a state where the voltage applied between the pn junctions of a pn junction diode is lower than the forward voltage (Vf) of the pn junction diode. Additionally, Figure 22 (b) indicates a state in which the voltage applied between the pn junctions of a pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0194] exist Figure 22 of (a) Figure 22 In (b), the dashed arrow represents the current flowing through the SBD. Figure 22 In (b), the solid arrow represents the current flowing through the pn junction diode.

[0195] The second distance d2 in the first direction between two adjacent second portions 28b in the diode region 102, which sandwich the anode region 34, is substantially equal to the first distance d1 in the first direction between two adjacent first portions 28a in the first direction, which sandwich the body region 30. In other words, in the diode region 102, the second portions 28b are arranged at the same interval as the first portions 28a in the transistor region 101. Further, in the diode region 102, the SBD region is arranged at the same interval as the transistor region 101.

[0196] Therefore, as Figure 22 As shown in (a), in diode region 102, the current flowing through the SBD extends to the bottom of anode region 34. Therefore, at the bottom of anode region 34, it is not easy to exceed the forward voltage (Vf) of the pn junction diode. The forward voltage (Vf) of the pn junction diode in diode region 102 is increased by setting the SBD region.

[0197] When the voltage applied between the pn junctions of a pn junction diode is higher than the forward voltage (Vf) of the pn junction diode, such as Figure 22 As shown in (b), current also flows through the pn junction diode.

[0198] In the MOSFET of the third comparative example, for example, the occupancy rate per unit area of ​​the anode region 34 projected onto the first surface P1 is greater than the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1. That is, the occupancy rate of pn junction diodes in diode region 102 is greater than the occupancy rate of pn junction diodes in transistor region 101.

[0199] Furthermore, for example, the contact area per unit area between the source electrode 12 and the anode region 34 in diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in transistor region 101. That is, the contact resistance per unit area between the source electrode 12 and the anode region 34 in diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in transistor region 101.

[0200] Therefore, the current flowing through the pn junction diode in diode region 102 is greater than the current flowing through the pn junction diode in transistor region 101.

[0201] Furthermore, by allowing a large current to flow through the pn junction diode in diode region 102, carrier propagation and heat propagation occur in the adjacent transistor region 101. This promotes conductivity modulation in the transistor region 101 adjacent to diode region 102. Consequently, the current flowing through the pn junction diode in the transistor region 101 adjacent to diode region 102 increases.

[0202] Figure 23 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment. Figure 23 This is a graph showing the voltage and current characteristics of the built-in diodes of the MOSFETs in the first comparative example, the second comparative example, and the third comparative example.

[0203] like Figure 23 As shown, in the third comparative example, the MOSFET flows through the SBD before the forward voltage Vf3 of the pn junction diode is applied. In the third comparative example, the MOSFET flows through the pn junction diode when a voltage greater than the forward voltage Vf3 is applied.

[0204] In the diode region 102 of the MOSFET in the third comparative example, the SBD region is provided at the same interval as the transistor region 101. Therefore, the forward voltage Vf3 of the pn junction diode of the MOSFET in the third comparative example is the same as the forward voltage Vf1 of the pn junction diode of the MOSFET in the first comparative example.

[0205] On the other hand, the current exceeding the forward voltage Vf3 of the pn junction diode in the MOSFET of the third comparative example is greater than the current exceeding the forward voltage Vf1 of the pn junction diode in the MOSFET of the first comparative example. This is because, compared to the MOSFET of the first comparative example, the current flowing through the pn junction diode in diode region 102 and the pn junction diode in transistor region 101 adjacent to diode region 102 is greater.

[0206] Since the current increases after exceeding the forward voltage Vf3 of the pn junction diode, the maximum allowable peak current value I of the MOSFET in the third comparative example is... FSM 3. Maximum allowable peak current value I of the MOSFET in the first comparison example FSM 1. Compared to the first comparative example, the surge current withstand capability of the MOSFET in the third comparative example is greater. In other words, the surge current withstand capability of the MOSFET in the third comparative example is greater than that in the first comparative example.

[0207] As described above, the MOSFET of the third comparative example has improved surge current tolerance by having a diode region 102 disposed between transistor regions 101.

[0208] In the MOSFET 100 of the first embodiment, the silicon carbide layer 10 includes a first p-type bridging region 36 (fourth silicon carbide region), a second p-type bridging region 38 (sixth silicon carbide region), and a third p-type bridging region 40 (seventh silicon carbide region), thereby further improving the surge current tolerance compared to the MOSFET of the third comparative example. Details will follow.

[0209] For example, in the MOSFET of the third comparative example, the inrush current flowing through the MOSFET may cause deviations within the chip. The reason for these deviations is believed to be due to deviations in the start-up of the pn junction diodes located in diode region 102 and transistor region 101, and the subsequent rise in forward current.

[0210] If the surge current deviates within the chip, for example, the heat generation increases locally. As a result, the MOSFET is locally damaged, leading to a reduction in surge current tolerance.

[0211] In the MOSFET 100 of the first embodiment, a plurality of p-type body regions 30 and a plurality of p-type anode regions 34 extending in the second direction are connected by p-type regions in the first direction by a first p-type bridging region 36 (fourth silicon carbide region), a second p-type bridging region 38 (sixth silicon carbide region), and a third p-type bridging region 40 (seventh silicon carbide region), respectively. The first bridging region 36, the second bridging region 38, and the third bridging region 40 connecting the body regions 30 and the anode regions 34 promote the movement of holes in the first direction, thereby enabling the start of operation of the pn junction diode provided in the diode region 102 and the transistor region 101, and the rise of the forward current after the start of operation, to be uniform within the chip.

[0212] According to the MOSFET 100 of the first embodiment, deviations in the inrush current flowing through the MOSFET within the chip can be suppressed. Therefore, the inrush current tolerance of the MOSFET 100 according to the first embodiment is improved.

[0213] The distance in the second direction between two adjacent first bridging regions 36 ( Figure 3 The dx in the transistor region 101 is preferably smaller than the width in the first direction. Figure 1 (w1 in (a)). By making the distance dx in the second direction smaller than the width w1 in the first direction of the transistor region 101, it is possible to further homogenize the start of operation of the pn junction diode provided in the transistor region 101 and the rise of the forward current after the start of operation within the chip.

[0214] The width of the second direction of the first bridging region 36 ( Figure 3 The wx in the middle is preferably less than the first distance in the first direction between two adjacent first parts 28a. Figure 2 of (a) Figure 3 (d1 in the middle). By making the width wx of the second direction of the first bridging region 36 smaller than the first distance d1 of the first direction between the two adjacent first portions 28a, it is possible to suppress the decrease of the forward voltage (Vf) of the pn junction diode of the transistor region 101.

[0215] The width of the second bridging region 38 in the second direction ( Figure 7 The width of the anode region 34 in the first direction (wy) is preferably smaller than that in the first direction. Figure 7 The width of the second bridging region 38 in the second direction (wb). Figure 7 (wy) for example, the width of the anode region 34 in the first direction ( Figure 7 The smaller wb in the diode region 102 allows for suppression of the decrease in the forward voltage (Vf) of the pn junction diode.

[0216] From the viewpoint of suppressing the reduction of the forward voltage (Vf) of the pn junction diode in diode region 102, the width of the second direction of the second bridging region 38 ( Figure 7 The width of the anode region 34 in the first direction is preferably wy) Figure 7 The width of the second bridging region 38 in the second direction is less than half of the wb. From the viewpoint of suppressing the reduction of the forward voltage (Vf) of the pn junction diode in the diode region 102, the width of the second bridging region 38 in the second direction is less than half of the wb. Figure 7 The wy in the sample is preferably below 10 μm.

[0217] The width of the second bridging region 38 in the second direction ( Figure 7 The distance between two adjacent second parts 28b in the first direction (wy) is preferably less than the second distance in the first direction (wy) Figure 6 (a) and Figure 7 (d2 in the middle). By making the width wy of the second direction of the second bridging region 38 smaller than the second distance d2 of the first direction between the two adjacent second parts 28b, it is possible to suppress the decrease of the forward voltage (Vf) of the pn junction diode in the diode region 102.

[0218] From the viewpoint of increasing the on-current of MOSFET 100, the width of transistor region 101 in the first direction ( Figure 1 In (a), w1) is preferably greater than the width of the diode region 102 in the first direction. Figure 1 w2 in (a).

[0219] (First variation) The semiconductor device of the first variant differs from the semiconductor device of the first embodiment in that the depth of the fourth silicon carbide region is greater than the depth of the second silicon carbide region, and the depth of the sixth silicon carbide region is greater than the depth of the fifth silicon carbide region.

[0220] Figure 24 of (a) Figure 24 of (b) Figure 25 of (a) Figure 25 (b) is a schematic cross-sectional view of a semiconductor device of a first variation of the first embodiment. Figure 24of (a) Figure 24 (b) is the same as the first embodiment. Figure 2 of (a) Figure 2 The diagram corresponding to (b). Additionally, Figure 25 of (a) Figure 25 (b) is the same as the first embodiment. Figure 6 of (a) Figure 6 The diagram corresponding to (b).

[0221] like Figure 24 of (a) Figure 24 As shown in (b), in the MOSFET of the first modified example, the depth of the first bridging region 36 (fourth silicon carbide region) of the p-type is deeper than the depth of the body region 30 (second silicon carbide region) of the p-type. Furthermore, as... Figure 25 of (a) Figure 25 As shown in (b), the depth of the second bridging region 38 (sixth silicon carbide region) of the p-type is greater than the depth of the anode region 34 (fifth silicon carbide region) of the p-type.

[0222] By increasing the depth of the first bridging region 36 and the second bridging region 38 of the p-type, the movement of holes in the first direction can be further facilitated. Therefore, the surge current tolerance of the MOSFET according to the first modified example is further improved.

[0223] (Second variation) The semiconductor device of the second modification differs from the semiconductor device of the first embodiment in that the p-type impurity concentration in the fourth silicon carbide region is higher than that in the second silicon carbide region, and the p-type impurity concentration in the sixth silicon carbide region is higher than that in the fifth silicon carbide region.

[0224] In the second modified MOSFET, the p-type impurity concentration in the first bridging region 36 (fourth silicon carbide region) of the p-type is higher than the p-type impurity concentration in the body region 30 (second silicon carbide region) of the p-type. Furthermore, the p-type impurity concentration in the second bridging region 38 (sixth silicon carbide region) of the p-type is higher than the p-type impurity concentration in the anode region 34 (fifth silicon carbide region) of the p-type.

[0225] The high p-type impurity concentration in the first bridging region 36 and the second bridging region 38 of the p-type further promotes the movement of holes in the first direction. Therefore, the surge current tolerance of the MOSFET according to the second modification is further improved.

[0226] Based on the first embodiment and its variations, a semiconductor device with improved surge current tolerance can be provided.

[0227] (Second Implementation) The semiconductor device of the second embodiment differs from that of the semiconductor device of the first embodiment in that the fourth silicon carbide region does not intersect with the second silicon carbide region, and the sixth silicon carbide region does not intersect with the fifth silicon carbide region. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0228] The semiconductor device in the second embodiment is the same as that in the first embodiment, and is a planar gate type vertical MOSFET 200 using silicon carbide.

[0229] Figure 26 of (a) Figure 26 (b) is a schematic cross-sectional view of a portion of the semiconductor device according to the second embodiment. Figure 27 This is a schematic top view of a part of the semiconductor device according to the second embodiment. Figure 26 (a) is Figure 27 AA' section. Figure 26 (b) is Figure 27 BB' section.

[0230] Figure 28 of (a) Figure 28 (b) is a schematic cross-sectional view of a portion of the semiconductor device of the second embodiment. Figure 29 This is a schematic top view of a part of the semiconductor device according to the second embodiment. Figure 28 (a) is Figure 29 CC' section. Figure 28 (b) is Figure 29 DD' section.

[0231] Figure 30 of (a) Figure 30 (b) is a schematic cross-sectional view of a portion of the semiconductor device according to the second embodiment. Figure 31 This is a schematic top view of a part of the semiconductor device according to the second embodiment. Figure 30 (a) is Figure 31 EE' section. Figure 30 (b) is Figure 31 FF' section.

[0232] The MOSFET200 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, an interlayer insulating layer 20, a gate electrode pad 22, and a gate wiring 24.

[0233] In the silicon carbide layer 10, n + Type 26, n drain region - Type 28 drift region (first silicon carbide region), p-type bulk region 30 (second silicon carbide region), n+ The p-type source region 32 (third silicon carbide region), the p-type anode region 34 (fifth silicon carbide region), the p-type first bridging region 36 (fourth silicon carbide region), the p-type second bridging region 38 (sixth silicon carbide region), and the p-type third bridging region 40 (seventh silicon carbide region).

[0234] The drift region 28 comprises multiple first parts 28a and multiple second parts 28b.

[0235] Figure 26 of (a) Figure 26 of (b) Figure 27 This is a diagram representing transistor region 101.

[0236] like Figure 26 of (a) Figure 26 of (b) Figure 27 As shown, transistor region 101 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. Within the silicon carbide layer 10 of transistor region 101, there are n... + Type 26, n drain region - Type 28 drift region (first silicon carbide region), multiple p-type bulk regions 30 (second silicon carbide region), multiple n-type drift ... + The source region 32 (third silicon carbide region) of the p-type type and the first bridging region 36 (fourth silicon carbide region) of multiple p-type types.

[0237] in addition, Figure 27 Only the patterns of the drift region 28, the body region 30, the first bridging region 36, and the gate electrode 18 are shown.

[0238] The first bridging region 36 of the p-type is disposed between the drift region 28 and the first surface P1. The first bridging region 36 is repeatedly configured in the second direction.

[0239] The first bridging region 36 connects two adjacent volume regions 30 in the first direction. The first bridging region 36 is configured repeatedly in the first direction, for example. Two adjacent first bridging regions 36 in the first direction sandwich the volume region 30 in between.

[0240] The first bridging region 36 divides the first portion 28a extending in the second direction. The first bridging region 36 connects two adjacent body regions 30 separated by the n-type first portion 28a sandwiched in the middle through a p-type silicon carbide region.

[0241] The distance in the second direction between two adjacent first bridging regions 36 is, for example, less than the width in the first direction of transistor region 101. The distance in the second direction between two adjacent first bridging regions 36 is, for example, more than 10 μm and less than 200 μm.

[0242] The width of the first bridging region 36 in the second direction is, for example, smaller than the distance between two adjacent first portions 28a. The distance between two adjacent first portions 28a is, for example, more than 3 μm and less than 30 μm. The width of the first bridging region 36 in the second direction is, for example, more than 1 μm and less than 10 μm.

[0243] The first bridging region 36, for example, contains aluminum (Al) as a p-type impurity. The p-type impurity concentration in the first bridging region 36 is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 1×10 21 cm -3 The p-type impurity concentration in the first bridging region 36 is substantially the same as that in the bulk region 30.

[0244] The depth of the first bridging region 36 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the first bridging region 36 is, for example, substantially the same as the depth of the volume region 30.

[0245] In addition, Figure 27 The example shows two first bridging regions 36 configured in the second direction, but there can also be three or more first bridging regions 36.

[0246] Figure 28 of (a) Figure 28 of (b) Figure 29 This is a diagram representing diode region 102.

[0247] like Figure 28 of (a) Figure 28 of (b) Figure 29 As shown, diode region 102 includes a silicon carbide layer 10, a source electrode 12 (first electrode), and a drain electrode 14 (second electrode). The silicon carbide layer 10 of diode region 102 contains n... + Type 26, n drain region - The system includes a p-type drift region 28 (first silicon carbide region), multiple p-type anode regions 34 (fifth silicon carbide region), and a p-type second bridging region 38 (sixth silicon carbide region).

[0248] also, Figure 29 Only the patterns of drift region 28, anode region 34, and second bridging region 38 are shown.

[0249] The drift region 28 contains multiple second parts 28b. The second parts 28b are connected to the first surface P1.

[0250] The second bridging region 38 of the p-shape is disposed between the drift region 28 and the first surface P1. The second bridging region 38 is repeatedly configured in the second direction.

[0251] The second bridging region 38 connects two adjacent anode regions 34 in the first direction. The second bridging region 38 is, for example, repeatedly configured in the first direction. An anode region 34 is sandwiched between two adjacent second bridging regions 38 in the first direction.

[0252] The second bridging region 38 divides the second portion 28b extending in the second direction. The second bridging region 38 connects the two adjacent anode regions 34, which are separated by the n-type second portion 28b sandwiched in the middle, through the p-type silicon carbide region.

[0253] The distance in the second direction between two adjacent second bridging regions 38 is, for example, less than the width in the first direction of transistor region 101. The distance in the second direction between two adjacent second bridging regions 38 is, for example, more than 10 μm and less than 200 μm.

[0254] The width of the second bridging region 38 in the second direction is, for example, less than the distance between two adjacent second portions 28b. The distance between two adjacent second portions 28b is, for example, more than 3 μm and less than 30 μm. The width of the second bridging region 38 in the second direction is, for example, more than 1 μm and less than 10 μm.

[0255] The distance between two adjacent second parts 28b is substantially equal to the distance between two adjacent first parts 28a.

[0256] The second bridging region 38, for example, contains aluminum (Al) as a p-type impurity. The p-type impurity concentration in the second bridging region 38 is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 1×10 21 cm -3 The p-type impurity concentration in the second bridging region 38 is substantially the same as that in the anode region 34. The p-type impurity concentration in the second bridging region 38 is substantially the same as that in the first bridging region 36.

[0257] The depth of the second bridging region 38 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the second bridging region 38 is, for example, substantially the same as the depth of the anode region 34. The depth of the second bridging region 38 is, for example, substantially the same as the depth of the first bridging region 36.

[0258] In addition, Figure 29The example shows two second bridging regions 38 configured in the second direction, but there can also be three or more second bridging regions 38.

[0259] Figure 30 of (a) Figure 30 of (b) Figure 31 This is a diagram showing the boundary between transistor region 101 and diode region 102.

[0260] like Figure 30 of (b) Figure 31 As shown, the silicon carbide layer 10 at the boundary between transistor region 101 and diode region 102 includes a p-type third bridging region 40 (seventh silicon carbide region).

[0261] The third bridging region 40 of the p-type is disposed between the drift region 28 and the first surface P1. The third bridging region 40 is repeatedly configured in the second direction.

[0262] The third bridging region 40 connects the adjacent body region 30 and anode region 34 in the first direction.

[0263] The third bridging region 40 divides the drift region 28 extending in the second direction in the first surface. The third bridging region 40 connects the adjacent body region 30, which is separated from the n-type drift region 28 by a p-type silicon carbide region, to the anode region 34.

[0264] The first bridging region 36, the second bridging region 38, and the third bridging region 40 are, for example, arranged side by side in the first direction.

[0265] The distance in the second direction between two adjacent third bridging regions 40 is, for example, less than the width in the first direction of transistor region 101. The distance in the second direction between two adjacent third bridging regions 40 is, for example, more than 10 μm and less than 200 μm.

[0266] The width of the third bridging region 40 in the second direction is, for example, smaller than the distance between two adjacent second portions 28b. The distance between two adjacent second portions 28b is, for example, more than 3 μm and less than 30 μm. The width of the third bridging region 40 in the second direction is, for example, more than 1 μm and less than 10 μm.

[0267] The third bridging region 40, for example, contains aluminum (Al) as a p-type impurity. The p-type impurity concentration in the third bridging region 40 is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 1×10 21 cm -3The p-type impurity concentration in the third bridging region 40 is substantially the same as that in the bulk region 30 and the anode region 34. The p-type impurity concentration in the third bridging region 40 is substantially the same as that in the first bridging region 36. The p-type impurity concentration in the third bridging region 40 is substantially the same as that in the second bridging region 38.

[0268] The depth of the third bridging region 40 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the third bridging region 40 is, for example, substantially the same as the depth of the body region 30 and the anode region 34. The depth of the third bridging region 40 is, for example, substantially the same as the depth of the first bridging region 36. The depth of the third bridging region 40 is, for example, substantially the same as the depth of the second bridging region 38.

[0269] In addition, Figure 31 The example shown illustrates the case where two third bridging regions 40 are configured in the second direction, but there can also be more than three third bridging regions 40.

[0270] The occupancy of the anode region 34 projected onto the first surface P1 per unit area is greater than that of the volume region 30 projected onto the first surface P1 per unit area. In other words, within a region of a specified size, the occupancy of the anode region 34 projected onto the first surface P1 is greater than that of the volume region 30 projected onto the first surface P1. That is, the occupancy ratio of pn junction diodes in diode region 102 is greater than that of pn junction diodes in transistor region 101.

[0271] The occupancy rate of the anode region 34 projected onto the first surface P1 is, for example, more than 1.2 times and less than 3 times the occupancy rate of the volume region 30 projected onto the first surface P1.

[0272] The aforementioned unit area is not particularly limited as long as it is a size that allows for comparison of the average occupancy of the body region 30 of the transistor region 101 and the average occupancy of the anode region 34 of the diode region 102. For example, the aforementioned unit area is 30μm × 30μm = 900μm. 2 .

[0273] Furthermore, the contact area per unit area between the source electrode 12 and the anode region 34 in diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in transistor region 101. That is, the contact resistance per unit area between the source electrode 12 and the anode region 34 in diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in transistor region 101.

[0274] In the MOSFET 200 of the second embodiment, similar to the MOSFET 100 of the first embodiment, a p-type first bridging region 36 (fourth silicon carbide region), a p-type second bridging region 38 (sixth silicon carbide region), and a p-type third bridging region 40 (seventh silicon carbide region) are provided, thereby connecting the p-type body region 30 and the p-type anode region 34 extending in the second direction by the p-type region in the first direction. The first bridging region 36, the second bridging region 38, and the third bridging region 40 connecting the body region 30 and the anode region 34 promote the movement of holes in the first direction, thereby enabling the start of operation of the pn junction diode provided in the diode region 102 and the transistor region 101, and the rise of the forward current after the start of operation, to be uniform within the chip.

[0275] According to the MOSFET 200 of the second embodiment, deviations in the inrush current flowing through the MOSFET within the chip can be suppressed. Therefore, the inrush current tolerance of the MOSFET 200 according to the second embodiment is improved.

[0276] Furthermore, in the MOSFET 200 of the second embodiment, the depth of the first bridging region 36 (fourth silicon carbide region) of the p-type can be made deeper than the depth of the body region 30 (second silicon carbide region) of the p-type. In addition, the depth of the second bridging region 38 (sixth silicon carbide region) of the p-type can be deeper than the depth of the anode region 34 (fifth silicon carbide region) of the p-type.

[0277] Furthermore, in the MOSFET 200 of the second embodiment, the p-type impurity concentration in the first bridging region 36 (fourth silicon carbide region) of the p-type can be higher than the p-type impurity concentration in the body region 30 (second silicon carbide region) of the p-type. Additionally, the p-type impurity concentration in the second bridging region 38 (sixth silicon carbide region) of the p-type can be higher than the p-type impurity concentration in the anode region 34 (fifth silicon carbide region) of the p-type.

[0278] Furthermore, in the MOSFET 200 of the second embodiment, the plurality of first bridging regions 36 may not necessarily be arranged along the first direction. Similarly, the plurality of second bridging regions 38 may not necessarily be arranged along the first direction. In addition, the first bridging regions 36, the second bridging regions 38, and the third bridging region 40 may not necessarily be arranged side by side in the first direction.

[0279] According to the second embodiment, a semiconductor device with improved surge current tolerance can be provided.

[0280] In the first and second embodiments, 4H-SiC was used as an example of the SiC crystal structure, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. In addition, the surface of the silicon carbide layer 10 can also be a surface other than the (0001) plane.

[0281] In the first and second embodiments, aluminum (Al) is exemplified as a p-type impurity, but boron (B) can also be used. Furthermore, nitrogen (N) and phosphorus (P) are exemplified as n-type impurities, but arsenic (As), antimony (Sb), etc., can also be used.

[0282] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment may be substituted or modified with the constituent elements of other embodiments. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the claims and their equivalents.

[0283] [Explanation of reference numerals in the attached figures] 10: Silicon carbide layer 12: Source electrode (first electrode) 14: Drain electrode (second electrode) 16: Gate insulating layer 18: Gate electrode 28: Drift region (first silicon carbide region) 28a: Part One 28b: Part Two 30: Body region (second silicon carbide region) 32: Source region (third silicon carbide region) 34: Anode region (Fifth silicon carbide region) 36: First bridging region (fourth silicon carbide region) 38: Second bridging region (sixth silicon carbide region) 40: Third bridging region (Seventh silicon carbide region) 100: MOSFET (Metal-Oxide-Semiconductor Device) 101: Transistor Region 102: Diode Region P1: First Page P2: Second page.

Claims

1. A semiconductor device comprising a plurality of transistor regions and a plurality of diode regions alternately arranged in a first direction. The transistor region includes: A silicon carbide layer having a first surface and a second surface facing the first surface, the silicon carbide layer comprising: an n-type first silicon carbide region having a plurality of first portions that are in contact with the first surface and extend in a second direction orthogonal to the first direction and are disposed in the first direction; Multiple p-type second silicon carbide regions are disposed between the first silicon carbide region and the first surface, extending in the second direction and arranged in the first direction; an n-type third silicon carbide region is disposed between the second silicon carbide region and the first surface; and multiple p-type fourth silicon carbide regions are disposed between the first silicon carbide region and the first surface, arranged in the second direction, connecting adjacent two second silicon carbide regions. The first electrode is connected to the first portion, the second silicon carbide region, the third silicon carbide region, and the fourth silicon carbide region; The second electrode is in contact with the second surface; Multiple gate electrodes are opposite to the second silicon carbide region, extend in the second direction, and are arranged in the first direction; as well as A gate insulating layer is disposed between the gate electrode and the second silicon carbide region. The diode region includes: The silicon carbide layer includes: an n-type first silicon carbide region having a plurality of second portions connected to the first surface and extending in a second direction; a plurality of p-type fifth silicon carbide regions disposed between the first silicon carbide region and the first surface, extending in the second direction and configured in the first direction; and a plurality of p-type sixth silicon carbide regions disposed between the first silicon carbide region and the first surface, configured in the second direction, connecting two adjacent fifth silicon carbide regions. The first electrode connected to the second portion, the fifth silicon carbide region, and the sixth silicon carbide region; as well as The second electrode, The silicon carbide layer further includes a plurality of p-type seventh silicon carbide regions disposed between the first silicon carbide region and the first surface, and arranged in the second direction to connect adjacent second silicon carbide regions with the fifth silicon carbide region.

2. The semiconductor device according to claim 1, wherein, The occupancy rate per unit area of ​​the fifth silicon carbide region projected onto the first surface is greater than the occupancy rate per unit area of ​​the second silicon carbide region projected onto the first surface.

3. The semiconductor device according to claim 2, wherein, The contact area per unit area between the first electrode and the fifth silicon carbide region is greater than the contact area per unit area between the first electrode and the second silicon carbide region.

4. The semiconductor device according to claim 1, wherein, The width of the sixth silicon carbide region in the second direction is smaller than the width of the fifth silicon carbide region in the first direction.

5. The semiconductor device according to claim 1, wherein, The distance in the second direction between two adjacent fourth silicon carbide regions is less than the width in the first direction of the transistor region.

6. The semiconductor device according to claim 1, wherein, The fourth silicon carbide region extends in the first direction and intersects with the second silicon carbide region. The sixth silicon carbide region extends in the first direction and intersects with the fifth silicon carbide region. The fourth silicon carbide region, the sixth silicon carbide region, and the seventh silicon carbide region are continuous in the first direction.

7. The semiconductor device according to claim 1, wherein, The fourth silicon carbide region is deeper than the second silicon carbide region. The sixth silicon carbide region is deeper than the fifth silicon carbide region.

8. The semiconductor device according to claim 1, wherein, The p-type impurity concentration in the fourth silicon carbide region is higher than that in the second silicon carbide region. The p-type impurity concentration in the sixth silicon carbide region is higher than that in the fifth silicon carbide region.

9. The semiconductor device according to claim 1, wherein, The second distance in the first direction between two adjacent second portions sandwiched in the middle of the fifth silicon carbide region is equal to the first distance in the first direction between two adjacent first portions sandwiched in the middle of the second silicon carbide region.

10. The semiconductor device according to claim 1, wherein, The width of the transistor region in the first direction is greater than the width of the diode region in the first direction.

Images