Imaging element and imaging device

Abstract

There is provided an image pickup element including: an element separation wall that partitions an element region of a semiconductor substrate in which the image pickup element is arranged; a plurality of pixels, which are provided in the element region surrounded by the element separation wall so as to be adjacent to each other, and each of which contains a first conductivity type impurity; pixel separation walls which are provided so as to extend in the depth direction of the semiconductor substrate, and which separate the plurality of pixels from each other; and an on-chip lens provided above the light receiving surface of the semiconductor substrate so as to be shared by the plurality of pixels. The pixel separation wall has a slit extending in the depth direction of the semiconductor substrate, and a diffusion region containing a second conductivity type impurity having a conductivity type opposite to the first conductivity type is provided in the slit.

Description

Technical Field

[0001] This invention relates to imaging elements and imaging devices. Background Technology

[0002] In recent years, camera devices have employed a method for detecting phase differences using a pair of phase difference detection pixels as an autofocus function. As an example of this, the camera element disclosed in Patent Document 1 can be mentioned. In the technology disclosed in Patent Document 1, effective pixels for capturing an image of the subject and phase difference detection pixels as described above are respectively provided on the light-receiving surface.

[0003] However, in the technology disclosed in Patent Document 1, when acquiring an image of a subject, the information obtained by the phase difference detection pixel is difficult to utilize as the same information as that from the camera pixel. Therefore, in this technology, the image of the pixel corresponding to the phase difference detection pixel is interpolated using information from effective pixels surrounding the phase difference detection pixel to generate the acquired image. In other words, in the technology disclosed in Patent Document 1, since a phase difference detection pixel is provided for performing phase difference detection, it is difficult to avoid image degradation due to the lack of information in the acquired image corresponding to the phase difference detection pixel.

[0004] Therefore, as a camera device that can improve the accuracy of phase difference detection while avoiding the degradation of the captured image, Patent Document 2 below provides a camera element that can acquire the captured image of the subject and perform phase difference detection on the entire surface of the light-receiving surface of the camera device. Citation List Patent documents

[0005] Patent Document 1: Japanese Patent Application JP 2000-292685 A Patent Document 2: PCT International Application Publication WO 2021 / 193915A Summary of the Invention Technical problems to be solved

[0006] Considering the further miniaturization of camera elements and the stable mass production of camera devices, camera elements still need further improvement in various characteristics. However, the technology disclosed in the aforementioned Patent Document 2 has limitations in further improving these characteristics.

[0007] Therefore, the present invention proposes imaging elements and imaging devices that can further improve various characteristics. Solution to the technical problem

[0008] According to the present invention, an imaging element is provided that performs photoelectric conversion on incident light and generates an electric charge. The imaging element includes: an element separation wall that defines an element region of a semiconductor substrate in which the imaging element is disposed; a plurality of pixels disposed adjacent to each other within the element region surrounded by the element separation wall, and each pixel comprising a first conductivity type impurity; a pixel separation wall that extends along the depth direction of the semiconductor substrate and spaces the plurality of pixels apart; and an on-chip lens disposed above a light-receiving surface of the semiconductor substrate, shared by the plurality of pixels. In the imaging element, the pixel separation wall has a slit extending along the depth direction of the semiconductor substrate. The width of the slit is configured such that it has a maximum width in the thickness direction of the semiconductor substrate at a depth between the light-receiving surface and a front surface of the semiconductor substrate opposite to the light-receiving surface, and a minimum width at a depth of the light-receiving surface or the front surface. A diffusion region is provided within the slit, the diffusion region comprising a second conductivity type impurity having a conductivity type opposite to the first conductivity type. Furthermore, the diffusion region has a first overflow path at the location where the slit has the maximum width, and the first overflow path contains the first conductive impurity.

[0009] Furthermore, according to the present invention, an imaging device is provided, comprising: a semiconductor substrate; and a plurality of imaging elements arranged in a matrix along row and column directions on the semiconductor substrate, the imaging elements performing photoelectric conversion on incident light and generating charge. In the imaging device, each of the imaging elements includes: an element separation wall that defines an element region of the semiconductor substrate in which the imaging elements are arranged; a plurality of pixels disposed adjacent to each other within the element region surrounded by the element separation wall, and each pixel containing a first conductivity type impurity; a pixel separation wall that extends along the depth direction of the semiconductor substrate and spaces the plurality of pixels apart; and an on-chip lens disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels. The pixel separation wall has a slit extending along the depth direction of the semiconductor substrate. The width of the slit is set such that, in the depth direction of the semiconductor substrate, it has a maximum width at a depth between the light-receiving surface and the front surface of the semiconductor substrate opposite to the light-receiving surface; and a minimum width at the depth of either the light-receiving surface or the front surface. A diffusion region is provided within the slit, the diffusion region containing impurities of a second conductivity type having a conductivity type opposite to the first conductivity type. Furthermore, the diffusion region has a first overflow path at the location where the slit has the maximum width, the first overflow path containing the first conductivity type impurities. Attached Figure Description

[0010] Figure 1 This is an explanatory diagram showing an example of the planar structure of a camera device 1 according to an embodiment of the present invention. Figure 2 This is an explanatory diagram showing an example of the planar structure of the imaging element 100a according to a comparative example. Figure 3 This is an explanatory diagram (part 1) showing an example of the cross-sectional structure of the imaging element 100a according to the comparative example. Figure 4 This is an explanatory diagram (part 2) showing an example of the cross-sectional structure of the imaging element 100a according to the comparative example. Figure 5 This is an explanatory diagram (part 3) showing an example of the cross-sectional structure of the imaging element 100a according to the comparative example. Figure 6 This is an explanatory diagram (part 1) used to explain the outline of the first embodiment of the present invention. Figure 7 This is an explanatory diagram (part 2) used to explain the outline of the first embodiment of the present invention. Figure 8 This is an explanatory diagram (part 3) used to explain the outline of the first embodiment of the present invention. Figure 9 This is an explanatory diagram (part 4) used to explain the outline of the first embodiment of the present invention. Figure 10 This is an explanatory diagram (part 1) showing an example of the cross-sectional structure of the imaging element 100 according to a first embodiment of the present invention. Figure 11 This is an explanatory diagram (part 2) showing an example of the cross-sectional structure of the imaging element 100 according to a first embodiment of the present invention. Figure 12 This is an explanatory diagram (part 3) showing an example of the cross-sectional structure of the imaging element 100 according to a first embodiment of the present invention. Figure 13 This is an explanatory diagram (part 4) showing an example of the cross-sectional structure of the imaging element 100 according to a first embodiment of the present invention. Figure 14 This is an explanatory diagram showing a planar construction example of a modified image sensor 100 according to a first embodiment of the present invention. Figure 15 This is an explanatory diagram showing a summary of a second embodiment of the present invention. Figure 16 This is an explanatory diagram (part 1) showing an example of the cross-sectional structure of the imaging element 100 according to a second embodiment of the present invention. Figure 17This is an explanatory diagram (part 2) showing an example of the cross-sectional structure of the imaging element 100 according to a second embodiment of the present invention. Figure 18 This is an explanatory diagram (part 3) showing an example of the cross-sectional structure of the imaging element 100 according to a second embodiment of the present invention. Figure 19 This is an explanatory diagram (part 4) showing an example of the cross-sectional structure of the imaging element 100 according to a second embodiment of the present invention. Figure 20 This is an explanatory diagram (part 5) showing an example of the cross-sectional structure of the imaging element 100 according to a second embodiment of the present invention. Figure 21 This is an explanatory diagram (part 6) showing an example of the cross-sectional structure of the imaging element 100 according to a second embodiment of the present invention. Figure 22 This is an explanatory diagram (part 7) showing an example of the cross-sectional structure of the imaging element 100 according to a second embodiment of the present invention. Figure 23 This is an explanatory diagram (part 1) showing the cross-sectional structure of a manufacturing method of an image sensor 100 according to a second embodiment of the present invention. Figure 24 This is an explanatory diagram (part 2) showing the cross-sectional structure of a manufacturing method of an image sensor 100 according to a second embodiment of the present invention. Figure 25 This is an explanatory diagram (part 3) showing the cross-sectional structure of the camera element 100 in a manufacturing method according to a second embodiment of the present invention. Figure 26 This is an explanatory diagram showing an example of the construction of the imaging element 100a according to the comparative example. Figure 27 This is an explanatory diagram (part 1) showing an example of the construction of a camera element 100 according to a third embodiment of the present invention. Figure 28 This is an explanatory diagram (part 2) showing an example of the construction of the imaging element 100 according to a third embodiment of the present invention. Figure 29 This is an explanatory diagram (part 3) showing an example of the construction of the imaging element 100 according to a third embodiment of the present invention. Figure 30 This is an explanatory diagram (part 4) showing an example of the construction of the imaging element 100 according to a third embodiment of the present invention. Figure 31 This is an explanatory diagram (part 5) showing an example of the construction of the imaging element 100 according to a third embodiment of the present invention. Figure 32This is an explanatory diagram (part 6) showing an example of the construction of the imaging element 100 according to a third embodiment of the present invention. Figure 33A This is an explanatory diagram (part 1) showing the cross-sectional structure of a manufacturing method of an image sensor 100 according to a third embodiment of the present invention. Figure 33B This is an explanatory diagram (part 2) showing the cross-sectional structure of a manufacturing method of an image sensor 100 according to a third embodiment of the present invention. Figure 33C This is an explanatory diagram (part 3) showing the cross-sectional structure of a manufacturing method of an image sensor 100 according to a third embodiment of the present invention. Figure 33D This is an explanatory diagram (part 4) showing the cross-sectional structure of a manufacturing method of an image sensor 100 according to a third embodiment of the present invention. Figure 33E This is an explanatory diagram (part 5) showing the cross-sectional structure of a manufacturing method of an image sensor 100 according to a third embodiment of the present invention. Figure 33F This is an explanatory diagram (part 6) showing the cross-sectional structure of a method for manufacturing an image sensor 100 according to a third embodiment of the present invention. Figure 33G This is an explanatory diagram (part 7) showing the cross-sectional structure of a manufacturing method of an image sensor 100 according to a third embodiment of the present invention. Figure 33H This is an explanatory diagram (part 8) showing the cross-sectional structure of a method for manufacturing an image sensor 100 according to a third embodiment of the present invention. Figure 34 This is an explanatory diagram (part 1) used to explain the background of the fourth embodiment of the present invention. Figure 35 This is an explanatory diagram (part 2) used to explain the background of the fourth embodiment of the present invention. Figure 36A This is an explanatory diagram (part 1) showing an example of the planar structure of the imaging element 100 according to a fourth embodiment of the present invention. Figure 36B This is an explanatory diagram (part 2) showing an example of the cross-sectional structure of the imaging element 100 according to a fourth embodiment of the present invention. Figure 37 This is an explanatory diagram showing an example of the planar layout structure of the imaging element 100 according to a fourth embodiment of the present invention. Figure 38 This is an explanatory diagram showing an example of the planar layout structure of a camera element 100 according to a modified example 1 of the fourth embodiment of the present invention. Figure 39This is an explanatory diagram showing an example of the planar layout structure of the imaging element 100 according to a modified example 2 of the fourth embodiment of the present invention. Figure 40A This is an explanatory diagram (part 1) showing an example of the planar structure of the imaging element 100 according to a modified example 3 of the fourth embodiment of the present invention. Figure 40B This is an explanatory diagram (part 2) showing an example of the cross-sectional structure of the imaging element 100 according to a modified example 3 of the fourth embodiment of the present invention. Figure 41A This is an explanatory diagram (part 1) showing an example of the planar structure of the imaging element 100 according to a fourth embodiment of the present invention. Figure 41B This is an explanatory diagram (part 2) showing an example of the cross-sectional structure of the imaging element 100 according to a modified example 4 of the fourth embodiment of the present invention. Figure 42 This is an explanatory diagram showing an example of the planar layout structure of the imaging element 100 according to a modified example 5 of the fourth embodiment of the present invention. Figure 43 This is an explanatory diagram showing an example of the planar layout structure of the imaging element 100 according to a modified example 6 of the fourth embodiment of the present invention. Figure 44 This is an explanatory diagram showing an example of the planar layout structure of the imaging element 100 according to a modified example 7 of the fourth embodiment of the present invention. Figure 45 This is an explanatory diagram illustrating an example of the schematic functional construction of a camera. Figure 46 This is a block diagram illustrating an example of the schematic functional structure of a smartphone. Figure 47 It is a block diagram illustrating a schematic example of the construction of a vehicle control system. Figure 48 This is an example diagram used to illustrate the installation locations of the vehicle exterior information detection unit and the camera unit. Detailed Implementation

[0011] In the following description, preferred embodiments of the invention will be explained in detail with reference to the accompanying drawings. Note that in this specification and the drawings, components having substantially the same functional structure are indicated by the same reference numerals, and repeated descriptions are omitted. Furthermore, in this specification and the drawings, multiple components having substantially the same or similar functional structures can be distinguished by appending different letters after the same reference numerals. However, where it is not necessary to specifically distinguish each of the multiple components having substantially the same or similar functional structures, they are simply indicated by the same reference numerals.

[0012] Furthermore, the accompanying drawings referenced in the following description are provided to facilitate the explanation and understanding of the various embodiments of the present invention. For ease of understanding, the shapes, dimensions, ratios, etc., shown in the drawings may differ from the actual figures. Additionally, the design of the camera device shown in the drawings can be appropriately modified with reference to the following description and known techniques.

[0013] The shapes described in the following description mean not only geometrically defined shapes, but also shapes that include permissible variations (errors and / or distortions) in the operation and manufacturing of the camera device.

[0014] Furthermore, in the following description, "electrical connection" means that multiple components are directly connected or indirectly connected through other components.

[0015] Furthermore, in the following explanation, "shared" means that different elements (such as pixels) share another element (such as on-chip lenses).

[0016] Please note that the explanations will be given in the following order. 1. Schematic diagram of the camera device 2. Schematic structure of the imaging element according to the comparative example 2.1 Planar Construction 2.2 Cross-sectional structure 3. First Embodiment 3.1 Background and Overview 3.2 Examples 3.3 Variations 4. Second Embodiment 4.1 Background and Overview 4.2 Examples 4.3 Manufacturing Method 5. Third embodiment 5.1 Background and Overview 5.2 Examples 5.3 Manufacturing Method 6. Fourth Embodiment 6.1 Background and Overview 6.2 Example 6.3 Variations 7. Summary 8. Applicable Examples 8.1 Examples of camera applicability 8.2 Examples of application of smartphones 8.3 Examples of Applicability of Moving Bodies 9. Supplement

[0017] [1. Schematic diagram of the camera device] First, it will refer to Figure 1 The schematic structure of a camera device 1 according to an embodiment of the present invention will be described below. Figure 1 This is an explanatory diagram showing an example of the planar structure of a camera device 1 according to an embodiment of the present invention. Figure 1 As shown, an imaging device 1 according to an embodiment of the present invention includes a pixel array section 30, in which a plurality of imaging elements 100 are arranged in a matrix along the row and column directions on a semiconductor substrate 10, for example, made of silicon. Furthermore, the imaging device 1 includes a peripheral circuit section disposed on the semiconductor substrate 10 and surrounding the pixel array section 30. Additionally, the imaging device 1 includes a vertical drive circuit section 32, a column signal processing circuit section 34, a horizontal drive circuit section 36, an output circuit section 38, a control circuit section 40, etc., as peripheral circuit sections. Details of each component of the imaging device 1 will be described below.

[0018] (Pixel array section 30) The pixel array section 30 includes a plurality of imaging elements 100 disposed on the semiconductor substrate 10 and arranged in a matrix in a two-dimensional configuration along the row and column directions. Each imaging element 100 is a device that performs photoelectric conversion on incident light to generate charge, and includes a photoelectric conversion unit (not shown) and a plurality of pixel transistors (e.g., metal-oxide-semiconductor (MOS) transistors (not shown). Here, the plurality of pixel transistors include, for example, four MOS transistors: a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor. Furthermore, in the pixel array section 30, the plurality of imaging elements 100 are arranged in a two-dimensional configuration, for example, according to a Bayer array. Here, the so-called Bayer array is an array pattern as follows: Imaging elements 100 capable of generating charge by absorbing light with green wavelengths (e.g., wavelengths from 495 nm to 570 nm) are arranged in a checkerboard pattern, and in the remaining portion, imaging elements 100 capable of generating charge by absorbing light with red wavelengths (e.g., wavelengths from 620 nm to 750 nm) and imaging elements 100 capable of generating charge by absorbing light with blue wavelengths (e.g., wavelengths from 450 nm to 495 nm) are arranged alternately in each row. Note that the detailed structure of the imaging elements 100 will be described later.

[0019] (Vertical drive circuit section 32) The vertical drive circuit section 32 is formed, for example, by a shift register, selects a pixel drive line 42, provides pulses to the selected pixel drive line 42 for driving the imaging element 100, and drives the imaging element 100 row by row. That is, the vertical drive circuit section 32 sequentially drives the imaging element 100 row by row in the vertical direction. Figure 1The pixel array section 30 selectively scans each imaging element 100 in the vertical direction, and provides the pixel signal, which is generated based on the amount of light received by the photoelectric conversion section (not shown) of each imaging element 100, to the column signal processing circuit section 34, which will be described later, via the vertical signal line 44.

[0020] (Section 34: Signal Processing Circuits) The column signal processing circuit unit 34 is arranged for each column of the imaging element 100, and performs signal processing such as noise removal on each pixel column for the pixel signals output from the imaging element 100 in a row. For example, the column signal processing circuit unit 34 performs signal processing such as correlated double sampling (CDS) and analog-to-digital (AD) conversion for removing fixed-pattern noise inherent in the pixels.

[0021] (Horizontal drive circuit section 36) The horizontal drive circuit section 36 is formed, for example, by a shift register. It sequentially selects each of the column signal processing circuit sections 34 by sequentially outputting horizontal scan pulses, and causes each of the column signal processing circuit sections 34 to output a pixel signal to the horizontal signal line 46.

[0022] (Output circuit section 38) The output circuit section 38 performs signal processing on the pixel signals sequentially supplied from each of the column signal processing circuit sections 34 via the horizontal signal line 46, and outputs the processed pixel signals. The output circuit section 38 can function as, for example, a buffering unit, or it can perform processing such as black level adjustment, column difference correction, and various digital signal processing. Note that buffering refers to temporarily storing pixel signals to compensate for differences in processing speed and transmission speed when exchanging pixel signals. Furthermore, the input / output terminal 48 is a terminal for exchanging signals with external devices.

[0023] (Control circuit section 40) The control circuit unit 40 receives an input clock and data for indicating the operating mode, and outputs data such as internal information of the camera device 1. In other words, the control circuit unit 40 generates clock signals or control signals based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, which serve as references for the operation of the vertical drive circuit unit 32, the column signal processing circuit unit 34, and the horizontal drive circuit unit 36. Then, the control circuit unit 40 outputs the generated clock signals and control signals to the vertical drive circuit unit 32, the column signal processing circuit unit 34, and the horizontal drive circuit unit 36.

[0024] Note that, in the embodiments of the present invention, the structure of the camera device 1 is not limited to... Figure 1 The structure shown.

[0025] [2. Schematic structure of the imaging element according to the comparative example] For example, in the imaging device 1 described above, in order to avoid image degradation and further improve the autofocus function, i.e., to improve the accuracy of phase difference detection, an imaging element 100a capable of performing phase difference detection is provided on the entire surface of the pixel array section 30. Specifically, the imaging element 100a functions as an imaging element during imaging and as a pair of phase difference detection pixels during phase difference detection. By providing such an imaging element 100a on the entire surface of the pixel array section 30, the accuracy of phase difference detection can be improved. Furthermore, since all the imaging elements 100a are capable of imaging the subject, image degradation can be avoided.

[0026] Furthermore, in the imaging element 100a, to improve the accuracy of phase difference detection, a feature is provided for physically and electrically separating the phase difference detection pixels, so as to avoid mixing of the outputs of a pair of phase difference detection pixels during phase difference detection. Additionally, in the imaging element 100a, to avoid degradation of the captured image, an overflow path is provided between a pair of phase difference detection pixels. Specifically, during normal image capture, when the charge of one pixel in a pair of phase difference detection pixels is about to saturate, the charge moves to the other pixel through the aforementioned overflow path, thereby preventing the saturation of that pixel. Thus, by providing such an overflow path, the linearity of the pixel signal output from the imaging element 100a can be ensured, and degradation of the captured image can be prevented.

[0027] The construction of the imaging element 100a as described above will be explained below. Note that the imaging element 100a described below is an imaging element that the inventors repeatedly studied before making the embodiments of the present invention, and is therefore referred to herein as the imaging element 100a according to the comparative example.

[0028] <2.1 Planar Construction> First, it will refer to Figure 2 To illustrate the planar structure of the imaging element 100a according to the comparative example. Figure 2 This is an explanatory diagram showing a planar view of the imaging element 100a according to a comparative example, and more specifically, a cross-section of the imaging element 100a cut parallel to the surface of the semiconductor substrate 10 is shown.

[0029] like Figure 2As shown, the imaging element 100a has an element separation wall 310 that surrounds the element region of the semiconductor substrate 10 and divides the element region of each imaging element 100a. Moreover, the imaging element 100a has pixels 300a and 300b that are adjacent to each other in the element region surrounded by the element separation wall 310.

[0030] Furthermore, pixels 300a and 300b each include a photoelectric conversion unit 302. For example, the photoelectric conversion unit 302 has a first conductivity type (e.g., N-type) impurity in the second conductivity type (e.g., P-type) semiconductor substrate 10. The photoelectric conversion unit 302 is capable of absorbing incident light having red, green, or blue wavelength components to generate an electric charge.

[0031] Furthermore, the photoelectric conversion unit 302 of pixel 300a and the photoelectric conversion component 302 of pixel 300b function as a pair of phase difference detection pixels during phase difference detection. Specifically, the photoelectric conversion unit 302 changes the amount of charge to be generated, i.e., sensitivity, according to the angle of incidence of light relative to its own optical axis (the axis perpendicular to the light-receiving surface). For example, the photoelectric conversion unit 302 has the highest sensitivity when the angle of incidence is 0 degrees, and the sensitivity of the photoelectric conversion unit 302 has a linear symmetry relationship with respect to the angle of incidence with the 0-degree angle of incidence as the object axis. Therefore, in the photoelectric conversion unit 302 of pixel 300a and the photoelectric conversion unit 302 of pixel 300b, light from the same point enters at different angles of incidence and generates charges with amounts corresponding to the angles of incidence, thus causing a shift (phase difference) in the detected image. In other words, the phase difference can be detected by detecting the difference between pixel signals based on the amount of charge generated by the photoelectric conversion unit 302 of pixel 300a and the photoelectric conversion component 302 of pixel 300b. Therefore, this difference (phase difference) between pixel signals is detected as a differential signal, for example, in the detection unit (not shown) of the output circuit section 38. Based on the detected phase difference, the defocusing amount is calculated, and the imaging lens (not shown) is adjusted (moved), thereby enabling autofocus. Note that in the above description, it has been explained that the phase difference is detected as the difference between the pixel signals of the photoelectric conversion unit 302 of pixel 300a and the photoelectric conversion component 302 of pixel 300b, but the present invention is not limited thereto. For example, the phase difference can also be detected as the ratio between the pixel signals of the photoelectric conversion unit 302 of pixel 300a and the photoelectric conversion component 302 of pixel 300b.

[0032] As described above, in the imaging element 100a according to the comparative example, the phase difference can be detected by detecting the difference between pixel signals based on the charge generated by the photoelectric conversion unit 302 of pixel 300a and the photoelectric conversion unit 302 of pixel 300b respectively.

[0033] In addition, such as Figure 2 As shown, pixels 300a and 300b are separated by a pixel separation wall 304 integrally formed with the element separation wall 310. Specifically, the pixel separation wall 304 is configured in the row direction ( Figure 2 Pixels 300a and 300b that are adjacent to each other in the left-right direction (in the column direction) are separated by each other along the column direction (in the column direction). Figure 2 It extends in the vertical direction. Furthermore, the pixel separation wall 304 has a slit 312 at the center O of the imaging element 100a. In other words, the pixel separation wall 304 has two wall portions that protrude from the element separation wall 310 toward the center O of the imaging element 100a along the column direction and face each other across the slit 312. As described above, in the imaging element 100a according to the comparative example, since the slit 312 is provided near the center O of the imaging element 100a, light scattering caused by the pixel separation wall 304 is suppressed. Therefore, light incident on the center O of the imaging element 100a can be incident on the photoelectric conversion unit 302 without being scattered.

[0034] Furthermore, in the semiconductor substrate 10, within the slit 312, a second conductivity type (e.g., P-type) impurity diffuses through the pixel separation wall 304 via conformal doping, thereby forming a diffusion region 306. Similarly, in the semiconductor substrate 10, around the element separation wall 310, a second conductivity type impurity diffuses through the element separation wall 310 via conformal doping, thereby forming a diffusion region 306. The diffusion region 306 within the slit 312 enables electrical isolation between a pair of pixels 300a and 300b to prevent color mixing, thereby further improving the accuracy of phase difference detection. Furthermore, the diffusion region 306 near the element separation wall 310 and the pixel separation wall 304 can suppress the generation of dark current in the imaging element 100a through a pinning effect.

[0035] Furthermore, in the imaging element 100a according to the comparative example, for example, in the region of the slit 312 located on the front side of the semiconductor substrate 10, a first conductivity type (e.g., N-type) impurity can be introduced by ion implantation, thereby forming a channel that serves as an overflow path. Therefore, in the imaging element 100a according to the comparative example, during phase difference detection, a pair of pixels 300a and 300b are separated by the pixel separation wall 304 and the diffusion region 306, and during normal imaging, charge can be exchanged between pixels 300a and 300a through the overflow path. Therefore, in the imaging element 100a according to the comparative example, the accuracy of phase difference detection can be improved while avoiding degradation of the captured image.

[0036] Furthermore, in the imaging element 100a according to the comparative example, as will be described in detail later, transfer gates 400a and 400b for transferring charge are provided on the front side of the semiconductor substrate 10.

[0037] <2.2 Cross-sectional Structure> Next, we will refer to Figures 3 to 5 To illustrate the cross-sectional structure of the imaging element 100a according to the comparative example. Figures 3 to 5 These are explanatory diagrams showing examples of cross-sectional structures of the imaging element 100a according to a comparative example, and they correspond to cross-sections in the thickness direction of the semiconductor substrate 10 obtained by cutting the imaging element 100a at different locations. Specifically, Figure 3 Corresponding to along Figure 2 The cross-section cut by the AA′ line in the middle. Figure 4 Corresponding to along Figure 2 The cross-section of the BB′ line cut in the middle. Figure 5 Corresponding to along Figure 2 The cross-section of the CC′ line cut in the image.

[0038] like Figures 3 to 5 As shown, the imaging element 100a according to the comparative example includes an on-chip lens 200, a color filter 202, a light-shielding portion (light-shielding film) 204, a semiconductor substrate 10, and transmission gates 400a and 400b. Furthermore, the semiconductor substrate 10 includes pixels 300a and 300b, each pixel including a photoelectric conversion portion 302. Additionally, the semiconductor substrate 10 includes a pixel separation wall 304 for separating pixels 300a and 300b, and further includes: an element separation wall 310 surrounding pixels 300a and 300b; and a diffusion region 306 disposed around the pixel separation wall 304 and the element separation wall 310. The stacked structure of the imaging element 100a according to the comparative example will be described below. Here, it will be described according to... Figures 3 to 5 The layered structure will be described sequentially from the top (light-receiving surface 10a side) to the bottom.

[0039] like Figures 3 to 5 As shown, the imaging element 100a includes an on-chip lens 200 disposed above the light-receiving surface 10a of the semiconductor substrate 10 and converging incident light onto the photoelectric conversion unit 302. The imaging element 100a has a structure in which a pair of pixels 300a and 300b are disposed corresponding to one on-chip lens 200. That is, the on-chip lens 200 is shared by two pixels 300a and 300b. Note that the on-chip lens 200 may be formed, for example, from a silicon nitride film (Si3N4) or a resin-based material such as a styrene-based resin, an acrylic resin, a styrene-acrylic copolymer resin, or a siloxane resin.

[0040] Therefore, the incident light converged by the on-chip lens 200 is incident on the photoelectric conversion unit 302 of each of pixels 300a and 300b via the color filter 202 disposed below the on-chip lens 200. The color filter 202 is any one of a color filter that allows the red wavelength component to pass through, a color filter that allows the green wavelength component to pass through, and a color filter that allows the blue wavelength component to pass through. For example, the color filter 202 can be formed of a material in which pigments or dyes are dispersed in a transparent adhesive such as silicone.

[0041] Furthermore, the light-shielding portion 204 is disposed on the light-receiving surface 10a of the semiconductor substrate 10, surrounding the color filter 202. Since the light-shielding portion 204 is disposed between adjacent imaging elements 100a, light can be blocked between the imaging elements 100a to suppress crosstalk between adjacent imaging elements 100a and further improve the accuracy of phase difference detection. The light-shielding portion 204 can be formed of a metallic material, such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or nickel (Ni).

[0042] Furthermore, for example, in the semiconductor substrate 10 of the second conductivity type (e.g., P-type), a photoelectric conversion unit 302 having impurities of the first conductivity type (e.g., N-type) is provided for each of the adjacent pixels 300a and 300b. As described above, the photoelectric conversion unit 302 absorbs light with red, green, or blue wavelength components incident through the color filter 202 and generates an electric charge.

[0043] Furthermore, in the comparative example, the two photoelectric conversion units 302 are physically separated by a pixel separation wall 304. The pixel separation wall 304 includes: a trench (not shown) formed as a through-dTI (deep trench isolation) extending along the film thickness direction of the semiconductor substrate 10 and penetrating the semiconductor substrate 10; and a material made of an oxide film or a metal film embedded in the trench, such as silicon oxide film (SiO2), silicon nitride film, amorphous silicon, polycrystalline silicon, titanium oxide film (TiO2), aluminum, or tungsten. In the imaging element 100a, during phase difference detection, the accuracy of phase difference detection deteriorates when the pixel signals output from a pair of pixels 300a and 300b mix and color mixing occurs. Therefore, in the comparative example, a pixel separation wall 304 penetrating the semiconductor substrate 10 is provided to efficiently physically separate a pair of pixels 300a and 300b. As a result, color mixing can be suppressed, and the accuracy of phase difference detection can be further improved.

[0044] Furthermore, when viewing the image sensor 100a from the light-receiving surface 10a side, a slit 312 is provided in the pixel separation wall 304 located near the center of the image sensor 100a (see [link]). Figure 2 Furthermore, in the region of the slit 312 within the semiconductor substrate 10, a second conductivity type (e.g., P-type) impurity diffuses via the pixel separation wall 304 through conformal doping, forming a diffusion region 306. To further improve the accuracy of phase difference detection, the diffusion region 306 can electrically isolate a pair of pixels 300a and 300b from each other, thereby preventing color mixing.

[0045] Furthermore, in this embodiment, such as Figure 4 and Figure 5 As shown, below the diffusion region 306 (on the front side 10b) within the slit 312, a first conductivity type (e.g., N-type) impurity is introduced by ion implantation to form the diffusion region 320. Specifically, the first conductivity type (e.g., N-type) impurity is introduced into the lower region of the diffusion region 306 by ion implantation, and a cavity is created in the diffusion region 306, thereby forming the diffusion region 320. The diffusion region 320 then serves as an overflow path for the exchange of generated charges between pixels 300a and 300b. Specifically, during normal imaging, when the charge of one of the pixels 300a and 300b is about to saturate, the charge moves to the other pixel through the overflow path, thereby preventing the saturation of that pixel. Thus, by providing such an overflow path, the linearity of the pixel signal output from the imaging element 100a can be ensured, and image degradation can be prevented.

[0046] Furthermore, in this comparative example, a component separation wall 310 is provided in the semiconductor substrate 10, which surrounds pixels 300a and 300b and physically separates adjacent imaging elements 100a. The component separation wall 310 includes: a trench (not shown) formed as a through-division through the semiconductor substrate 10 along the film thickness direction; and a material made of oxide film or metal film embedded in the trench, such as silicon oxide film, silicon nitride film, amorphous silicon, polycrystalline silicon, titanium oxide film, aluminum, or tungsten. That is, in this comparative example, the pixel separation wall 304 and the component separation wall 310 can be formed of the same material.

[0047] Furthermore, in this comparative example, the charge generated in the photoelectric conversion section 302 of pixel 300a and the photoelectric conversion section 302 of pixel 300b is transferred to a charge storage section (not shown) via the transfer gates 400a and 400b of a transfer transistor (one type of pixel transistor) disposed on the front surface 10b of the semiconductor substrate 10 on the side opposite to the light-receiving surface 10a. Specifically, the transfer gates 400a and 400b are formed of, for example, a metal film, and transfer the charge to, for example, a charge storage section (floating diffusion section) disposed in a semiconductor region having a first conductivity type (e.g., N-type) within the semiconductor substrate 10.

[0048] In the following description, various embodiments of the present invention will be described. In each embodiment, unless otherwise specified, the imaging element 100 has a form substantially similar to that of the imaging element 100a of the comparative example.

[0049] [3. First Embodiment] <3.1 Background and Overview> Next, the first embodiment of the present invention will be described. First, before describing this embodiment, reference will be made to... Figures 6 to 9 This will explain the background that prompted the inventors to create this embodiment and the summary of this embodiment. Figures 6 to 9 This is an explanatory diagram used to illustrate the general outline of this embodiment.

[0050] Will refer to Figure 6 To illustrate the imaging element 100a according to the comparative example. Figure 6 The left side shows a plan view of the imaging element 100a according to the comparative example, and this view corresponds to the aforementioned Figure 2 .also, Figure 6 The upper right figure shows a cross-section of the imaging element 100a cut along line aa′ in the left figure. Furthermore, Figure 6 The lower right figure shows the potential energy change in the film thickness (depth) direction of the semiconductor substrate 10 as shown in the upper right figure.

[0051] As mentioned above, such as Figure 6 As shown in the upper left and upper left figures, in the imaging element 100a according to the comparative example, pixels 300a and 300b are physically separated by a pixel separation wall 304 and electrically separated by a diffusion region 306 containing a second conductivity type (e.g., P-type) impurity within a slit 312 provided in the pixel separation wall 304. Furthermore, in the comparative example, an overflow path 314 containing a first conductivity type (e.g., N-type) impurity is provided in the slit 312, which is used to exchange charge between pixels 300a and 300b. Therefore, as... Figure 6As shown in the lower right corner, the potential is deeper (lower) at the location of overflow path 314, and charge can be exchanged between pixels 300a and 300b. Furthermore, as... Figure 6 As shown in the lower right, the potential is shallower (higher) at locations other than the overflow path 314, and pixels 300a and 300b are electrically isolated from each other. Furthermore, in order to suppress the generation of dark current in the imaging element 100a, a second conductivity type (e.g., P-type) impurities are injected at a high concentration around the element separation wall 310 and the pixel separation wall 304.

[0052] Furthermore, during the formation of the overflow path 314, as described above, a first conductivity type (e.g., N-type) impurity is introduced into the semiconductor substrate 10 via ion implantation. At this time, the first conductivity type impurity diffuses into a diffusion region 306 containing a second conductivity type (e.g., P-type) impurity around the sidewall of the pixel separation wall 304 adjacent to the overflow path 314, and the pinning effect of the diffusion region 306 around the sidewall of the pixel separation wall 304 may be weakened. Therefore, if the pinning effect is weakened, dark current is more likely to be generated in the imaging element 100a.

[0053] Therefore, in the imaging element 100a, when performing ion implantation of impurities, it is necessary to control the implantation amount and diffusion state of the impurities with high precision.

[0054] Next, we will refer to Figure 7 This will be used to explain the potential of the diffusion region 306 and the amount of ion implantation of impurities within the slit 312 of the pixel separation wall 304 at various widths.

[0055] When the slit 312 is narrow, the effect of the second conductivity type (e.g., P-type) impurities diffused from the sidewalls of the pixel separation wall 304 via conformal doping is stronger, resulting in a shallower (higher) potential in the diffusion region 306 within the slit 312. Therefore, the amount of second conductivity type impurities implanted for separation between pixels 300a and 300b can be less. On the other hand, the amount of first conductivity type (e.g., N-type) impurities implanted for forming the overflow path 314 capable of exchanging charge between pixels 300a and 300b increases. As a result, when the slit 312 is narrow, the second conductivity type impurities easily diffuse into the diffusion region 306 containing them around the sidewalls of the pixel separation wall 304 adjacent to the overflow path 314, weakening the pinning effect and easily generating dark current in the imaging element 100a.

[0056] When the slit 312 is wider, the distance from the sidewall of the pixel separation wall 304 to the central axis of the slit 312 is longer. Therefore, the concentration of the second conductivity type (e.g., P-type) impurities tends to be lower around the central axis of the slit 312, and the potential tends to be deeper (lower) compared to when the slit 312 is narrower. Therefore, when the slit 312 is wider, the amount of second conductivity type impurities injected for separation between pixels 300a and 300b needs to be increased. As a result, the second conductivity type impurities also tend to diffuse into the photoelectric conversion section 302, which greatly affects the potential of the photoelectric conversion section 302 and increases the risk of white spots. On the other hand, when the slit 312 is wider, since the distance from the sidewall of the pixel separation wall 304 to the central axis of the slit 312 is longer, the amount of first conductivity type (e.g., N-type) impurities injected to form the overflow path 314 capable of exchanging charge between pixels 300a and 300b can be less. Therefore, with a wider slit 312, the pinning effect of the diffusion region 306 around the sidewall of the pixel separation wall 304 adjacent to the overflow path 314 is unlikely to be reduced, and dark current is less likely to be generated in the image sensor 100a.

[0057] In other words, in the comparative example, in order to separate pixels 300a and 300b and exchange charges between pixels 300a and 300b, it is necessary to increase the amount of at least one of the first conductivity type (e.g., N-type) impurities and the second conductivity type (e.g., P-type) impurities injected. Therefore, in the comparative example, the manufacturing time and cost of the imaging device 1 are increased. Furthermore, in the comparative example, in order to prevent fluctuations in the potential and pinning effect of the photoelectric conversion unit 302, etc., it is necessary to control the width of the slit 312 and the amount of impurities injected with high precision, and it is difficult to stably mass-produce the imaging device 1 with the desired characteristics. In particular, when the imaging element 100a is miniaturized, in the comparative example, it is difficult to control the width of the slit 312 and the amount of impurities injected with high precision in order to prevent fluctuations in the potential and pinning effect of the photoelectric conversion unit 302, etc.

[0058] Therefore, in view of the above situation, the inventors created the embodiment described below. In this embodiment, the width of the slit 312 is maximized at the location of the overflow path 314, and the width of the slit 312 is narrower on the light-receiving surface 10a side and the front surface 10b side. With this arrangement, in this embodiment, since the width of the slit 312 is wider at the location of the overflow path 314, the distance from the sidewall of the pixel separation wall 304 to the overflow path 314 is longer. Therefore, according to this embodiment, the amount of first conductivity type (e.g., N-type) impurities injected to form the overflow path 314 can be reduced. Furthermore, as a result, according to this embodiment, the first conductivity type impurities are less likely to diffuse into the diffusion region 306 around the sidewall of the pixel separation wall 304 adjacent to the overflow path 314, the pinning effect is less likely to be reduced, and dark current is less likely to occur in the imaging element 100a. Furthermore, in this embodiment, since the width of the slit 312 is narrower at locations other than the overflow path 314, the influence of the second conductivity type (e.g., P-type) impurity diffused from the sidewall of the pixel separation wall 304 via conformal doping is stronger, resulting in a shallower (higher) potential in the diffusion region 306 within the slit 312. Therefore, in this embodiment, the amount of second conductivity type impurity implanted for separation between pixels 300a and 300b can be less.

[0059] Will refer to Figure 8 The camera element 100 according to this embodiment will be described. Figure 8 The left side shows a plan view of the imaging element 100 according to this embodiment, which corresponds to the aforementioned... Figure 2 .also, Figure 8 The upper right figure shows a cross-section of the imaging element 100 cut along line aa′ in the left figure. Furthermore, Figure 8 The lower right figure shows the potential energy change in the film thickness (depth) direction of the semiconductor substrate 10 as shown in the upper right figure.

[0060] In this embodiment, as Figure 8 As shown in the lower right figure, the potential is deeper (lower) at the location of overflow path 314, and charge can be exchanged between pixels 300a and 300b. Furthermore, as... Figure 8 As shown in the lower right figure, the potential is shallower (higher) at locations other than the overflow path 314, and pixels 300a and 300b are electrically separated from each other.

[0061] Furthermore, in this embodiment, by forming the slit 312 of the pixel separation wall 304 into a conical or stepped shape, the width of the slit 312 can be maximized at the location of the overflow path 314, and the width of the slit 312 can be narrower on the light-receiving surface 10a side and the front surface 10b side. Specifically, as Figure 9As shown on the left, trenches are formed from both the front surface 10b side and the light-receiving surface 10a side of the semiconductor substrate 10. That is, in this embodiment, by forming trenches in two stages, the slit 312 of the pixel separation wall 304 can be made into a tapered shape. Furthermore, as... Figure 9 As shown on the right, trenches of different depths are formed twice from the front side 10b of the semiconductor substrate 10, and further trenches are formed from the light-receiving surface 10a. That is, in this embodiment, by forming trenches in three stages, the slit 312 of the pixel separation wall 304 can be made into a stepped shape.

[0062] As described above, according to this embodiment, the amount of first conductivity type (e.g., N-type) impurities injected to form the overflow path 314 can be reduced. As a result, according to this embodiment, the first conductivity type impurities are less likely to diffuse into the diffusion region 306 around the sidewalls of the pixel separation wall 304 adjacent to the overflow path 314, the pinning effect is less likely to be weakened, and dark current is less likely to appear in the imaging element 100a. Furthermore, according to this embodiment, the amount of second conductivity type impurities injected for separation between pixels 300a and 300b can also be reduced. Moreover, according to this embodiment, even when the imaging element 100 is miniaturized, the potential and pinning effect of the photoelectric conversion section 302, etc., are less likely to fluctuate, thus facilitating stable mass production of the imaging device 1 with the desired characteristics. Details of this embodiment will be described below.

[0063] <3.2 Example> Next, we will refer to Figures 10 to 13 To illustrate an example of the cross-sectional structure of the camera element 100 according to this embodiment. Figures 10 to 13 This is an explanatory diagram showing an example of the cross-sectional structure of the imaging element 100 according to this embodiment; specifically, it is... Figure 5 An enlarged view of a portion of the slit 312 in the cross-section shown.

[0064] First, in this embodiment, as in the comparative example, such as Figure 10As shown at the left end, the pixel separation wall 304 has a slit 312 extending along the film thickness direction (depth direction) of the semiconductor substrate 10. Furthermore, in this embodiment, the width of the slit 312 is at its maximum width in the depth direction of the semiconductor substrate 10, located between the light-receiving surface 10a and the front surface 10b of the semiconductor substrate 10 opposite to the light-receiving surface 10a. Furthermore, in this embodiment, the width of the slit 312 gradually narrows towards the light-receiving surface 10a from the position of maximum width, and also gradually narrows towards the front surface 10b from the position of maximum width. Note that in this embodiment, the position of the maximum width is not particularly limited, as long as it is located at the depth between the light-receiving surface 10a and the front surface 10b. For example, the position of the maximum width can be changed according to the position of the imaging element 100 in the pixel array section 30. Furthermore, for example, the position of the maximum width can be changed according to the color of the light received by the imaging element 100. Furthermore, in Figure 10 In the example shown on the left, the slit 312 has a minimum width at the light-receiving surface 10a. However, in this embodiment, the slit 312 may have a minimum width at the front surface 10b, or it may have a minimum width at both the light-receiving surface 10a and the front surface 10b.

[0065] Furthermore, in this embodiment, such as Figure 10 As shown at the left end, the pixel separation wall 304 includes a pair of wall portions (first wall portion and second wall portion) 304a and 304b facing each other across a slit 312. Furthermore, the surfaces of wall portion 304a facing wall portion 304b and the surfaces of wall portion 304b facing wall portion 304a are linearly symmetrical about the central axis of the slit 312. In addition, the slit 312 has a tapered shape that narrows from its maximum width towards the light-receiving surface 10a and towards the front surface 10b, respectively. Specifically, the surfaces of wall portion 304a and wall portion 304b facing each other each have two regions formed by inclined surfaces, each inclined surface intersecting obliquely with the perpendicular line of the front surface 10b of the semiconductor substrate 10.

[0066] In this embodiment, similarly, a diffusion region 306 containing a second conductivity type (e.g., P-type) impurity is provided in the slit 312, and the diffusion region 306 has an overflow path (first overflow path) 314 containing a first conductivity type (e.g., N-type) impurity at the location where the slit 312 has the maximum width.

[0067] Furthermore, in this embodiment, such as Figure 10 As shown in the second figure from the left, the diffusion region 306 may also include one or more overflow paths (second overflow paths) 314 containing first conductivity type (e.g., N-type) impurities at locations other than where the slit 312 has the maximum width.

[0068] Furthermore, in this embodiment, such as Figure 10 As shown at the right end, the surface of wall portion 304a facing wall portion 304b and the surface of wall portion 304b facing wall portion 304a may each have: two regions formed by an inclined surface that intersects obliquely with the perpendicular line to the front surface 10b of semiconductor substrate 10; and a region formed by a surface perpendicular to the front surface 10b.

[0069] In addition, Figure 11 In the example shown on the left, the width of the slit 312 of the pixel separation wall 304 is at its maximum width in the depth direction of the semiconductor substrate 10, at a depth between the light-receiving surface 10a and the front surface 10b. Furthermore, in this example, the width of the slit 312 is narrower on the side of the light-receiving surface 10a relative to its maximum width position, and also narrower on the side of the front surface 10b relative to its maximum width position. Additionally, in this example, the surface of wall 304a facing wall 304b and the surface of wall 304b facing wall 304a each have a stepped shape, i.e., they have multiple regions formed by surfaces perpendicular to the front surface 10b.

[0070] In addition, Figure 11 In the second example from the left end, at the position of maximum width, the surfaces of wall portion 304a facing wall portion 304b and the surfaces of wall portion 304b facing wall portion 304a have regions formed by surfaces perpendicular to the front surface 10b. Furthermore, in this example, at positions other than the position of maximum width, the surfaces of wall portion 304a facing wall portion 304b and the surfaces of wall portion 304b facing wall portion 304a have regions formed by inclined surfaces, each inclined surface intersecting obliquely with the perpendicular line of the front surface 10b of the semiconductor substrate 10.

[0071] In addition, Figure 11 In the third example from the left, with Figure 11 Unlike the second example from the left end, the surfaces of wall 304a facing wall 304b and the surfaces of wall 304b facing wall 304a have areas formed by inclined surfaces on the light-receiving surface 10a side relative to the maximum width position. These inclined surfaces intersect obliquely with the vertical line of the front surface 10b of the semiconductor substrate 10.

[0072] In addition, Figure 11 In the example shown on the right end of the text, with Figure 11 Unlike the second example from the left end, the surfaces of wall 304a facing wall 304b and the surfaces of wall 304b facing wall 304a have a region formed by an inclined surface on the front side 10b side relative to the maximum width position, which intersects obliquely with the vertical line of the front side 10b of the semiconductor substrate 10.

[0073] exist Figure 10 and Figure 11 In the example shown, the surfaces of wall portion 304a facing wall portion 304b and the surfaces of wall portion 304b facing wall portion 304a are linearly symmetrical about the central axis of slit 312. However, this embodiment is not limited to this; the surfaces of wall portion 304a facing wall portion 304b and the surfaces of wall portion 304b facing wall portion 304a may also be asymmetrical about the central axis of slit 312.

[0074] First, in this embodiment, as Figure 12 As shown at the left end, the surface of wall portion 304a facing wall portion 304b has two regions formed by inclined surfaces, each inclined surface intersecting obliquely with the perpendicular line of the front surface 10b of the semiconductor substrate 10. On the other hand, the surface of wall portion 304b facing wall portion 304a is formed by a surface perpendicular to the front surface 10b. That is, in this embodiment, the surfaces of wall portion 304a and wall portion 304b facing each other and the surfaces of wall portion 304b and wall portion 304a facing each other are asymmetrical about the central axis of slit 312.

[0075] exist Figure 12 In the second example from the left end, similarly, the diffusion region 306 may also include one or more overflow paths (second overflow paths) 314 containing first conductivity type (e.g., N-type) impurities at locations other than where the slit 312 has the maximum width.

[0076] In addition, Figure 12 In the example shown on the right end, the surface of wall portion 304a facing wall portion 304b has: a region formed by an inclined surface that intersects obliquely with a perpendicular line to the front surface 10b of the semiconductor substrate 10; and a region formed by a surface perpendicular to the front surface 10b. On the other hand, the surface of wall portion 304b facing wall portion 304a is formed by a surface perpendicular to the front surface 10b.

[0077] In this embodiment, similarly, in Figure 13 In the example shown on the left, the surface of wall portion 304a facing wall portion 304b has a stepped shape, that is, it has multiple regions formed by a surface perpendicular to the front face 10b. On the other hand, the surface of wall portion 304b facing wall portion 304a is formed by a surface perpendicular to the front face 10b.

[0078] exist Figure 13In the second example from the left end, similarly, at the position of maximum width, the surface of wall portion 304a facing wall portion 304b has a region formed by a surface perpendicular to the front surface 10b. Furthermore, in this example, on the side of the light-receiving surface 10a relative to the position of maximum width, the surface of wall portion 304a facing wall portion 304b has a region formed by a surface perpendicular to the front surface 10b. Furthermore, in this example, on the side of the front surface 10b relative to the position of maximum width, the surface of wall portion 304a facing wall portion 304b has a region formed by an inclined surface that intersects obliquely with the perpendicular line of the front surface 10b of the semiconductor substrate 10. On the other hand, the surface of wall portion 304b facing wall portion 304a is formed by a surface perpendicular to the front surface 10b.

[0079] exist Figure 13 In the third example from the left, similarly, at the position of maximum width, the surface of wall portion 304a facing wall portion 304b has a region formed by a surface perpendicular to the front surface 10b. Furthermore, in this example, at positions other than the position of maximum width, the surface of wall portion 304a facing wall portion 304b has a region formed by inclined surfaces, each inclined surface intersecting obliquely with the perpendicular line of the front surface 10b of the semiconductor substrate 10. On the other hand, the surface of wall portion 304b facing wall portion 304a is formed by a surface perpendicular to the front surface 10b.

[0080] In addition, Figure 13 In the example shown on the right, with Figure 11 Unlike the third example from the left end, the surface of wall 304a facing wall 304b has a region formed by an inclined surface on the front side 10b side relative to the maximum width position, which intersects obliquely with the vertical line of the front side 10b of the semiconductor substrate 10.

[0081] As described above, in this embodiment, the width of the slit 312 is maximized at the location of the overflow path 314, and the width of the slit 312 is narrower on the light-receiving surface 10a side and the front surface 10b side. With this arrangement, in this embodiment, since the width of the slit 312 is wider at the location of the overflow path 314, the distance between the sidewall of the pixel separation wall 304 and the overflow path 314 is longer. Therefore, according to this embodiment, the amount of first conductivity type (e.g., N-type) impurities injected to form the overflow path 314 can be reduced. Furthermore, as a result, according to this embodiment, the first conductivity type impurities are less likely to diffuse into the diffusion region 306 around the sidewall of the pixel separation wall 304 adjacent to the overflow path 314, the pinning effect is less likely to be reduced, and dark current is less likely to occur in the imaging element 100a. Furthermore, in this embodiment, since the width of the slit 312 is narrower at locations other than the overflow path 314, the influence of the second conductivity type (e.g., P-type) impurities diffused from the sidewalls of the pixel separation wall 304 via conformal doping becomes stronger, resulting in a shallower (higher) potential in the diffusion region 306 within the slit 312. Therefore, in this embodiment, the amount of second conductivity type impurities injected for separation between pixels 300a and 300b can be relatively small. Moreover, according to this embodiment, even when the imaging element 100 is miniaturized, the potential and pinning effect of the photoelectric conversion section 302, etc., are unlikely to fluctuate, thus facilitating stable mass production of the imaging device 1 with the desired characteristics.

[0082] Note that this embodiment is not limited to Figures 10 to 13 The structure shown.

[0083] <3.3 Variations> Next, we will refer to Figure 14 The planar structure example of the camera element 100, which is a variation of this embodiment, will be described. Figure 14 This is an explanatory diagram showing an example of the planar structure of the imaging element 100 according to a modified example of this embodiment, and specifically corresponding to... Figure 2 The floor plan shown.

[0084] like Figure 14 As shown on the left, in pixels 300a and 300b, the pixel separation wall 304 is set in the row direction ( Figure 14 Adjacent pixels 300a and 300a in the left-right direction are separated along the column direction. Figure 2 Extending in the vertical direction. In this embodiment, the pixel separation wall 304 is not limited to being configured to pass through the center of the imaging element 100, but may also be configured to pass through, for example, in the vertical direction. Figure 14 The position shown on the left, offset from the center by a predetermined distance in the row direction. For example, in Figure 14In the example shown on the left, the slit 312 of the pixel separation wall 304 can be positioned offset to the left of the center in the row direction by a predetermined distance.

[0085] In addition, such as Figure 14 As shown on the right, the slit 312 of the pixel separation wall 304 is not limited to being located at the center of the imaging element 100, but can also be positioned at a predetermined distance offset from the center in the column direction. For example, in Figure 14 In the example shown on the right, the slit 312 of the pixel separation wall 304 is positioned in the column direction ( Figure 2 The vertical direction (in the diagram) is offset by a predetermined distance relative to the center towards the lower side of the diagram.

[0086] In this modified example, for example, the position of the slit 312 can be changed according to the position of the imaging element 100 in the pixel array section 30. Furthermore, for example, the position of the slit 312 can be changed according to the color of the light received by the imaging element 100.

[0087] [4. Second Embodiment] <4.1 Background and Overview> The second embodiment of the present invention will be described below. First, before describing this embodiment, reference will be made to... Figure 15 This will explain the background that led the inventors to create this embodiment and the summary of this embodiment. Figure 15 This is an explanatory diagram showing a summary of this embodiment. Note that in Figure 15 In the diagram, overflow path 314 is called "OFB", and pixels 300a and 300b are called "L" and "R" respectively.

[0088] Incidentally, although the image sensor 100 needs to be further miniaturized, it can be expected that if the image sensor 100a according to the comparative example is further miniaturized, the control of the potential of the overflow path 314 will become difficult, and the following phenomena will occur significantly.

[0089] like Figure 15As shown on the left, when the potential of the overflow path 314 is higher (shallower), the saturation charge (Qs) of each pixel in pixels 300a and 300b increases. Therefore, since the saturation charge (Qs) of each pixel in pixels 300a and 300b is larger, the phase difference detection accuracy is higher. Furthermore, when acquiring an image of the subject, i.e., when using a pair of pixels 300a and 300b as a single pixel, if the charge of one pixel 300a is saturated, the charge flows into the other pixel 300b, thereby ensuring the linearity of the pixel signal. However, if the potential of the overflow path 314 is too high, it becomes difficult to exchange charge between pixels 300a and 300b, and the charge of one pixel 300a flows into the charge accumulation section of that pixel 300a. Thus, in this case, when a pair of pixels 300a and 300b are set as a single pixel and these charges are to be evaluated collectively, the linearity between the exposure time and the output waveform is lost, and the output result becomes poor.

[0090] On the other hand, such as Figure 15 As shown on the right, when the potential of the overflow path 314 is lower (deeper), the saturation charge (Qs) of each pixel in pixels 300a and 300b decreases. Therefore, the phase difference detection accuracy decreases. However, when acquiring an image of the subject, i.e., when a pair of pixels 300a and 300b are used as a single pixel, charge can easily be exchanged between pixels 300a and 300b. Therefore, when the potential of the overflow path 314 is lower, when one pixel 300a is saturated with charge, charge easily flows into the other pixel 300b, thus suppressing the inflow of charge into the charge accumulation portion of that pixel 300a. As a result, when the potential of the overflow path 314 is lower, and a pair of pixels 300a and 300b are set as a single pixel and these charges are evaluated collectively, the linearity between the exposure time and the output waveform is maintained, and the deterioration of the output result is suppressed.

[0091] As described above, since the potential of the overflow path 314 strongly affects the trade-off between phase difference detection and the linearity of the output waveform, it is necessary to control the potential at an appropriate level. Therefore, especially when miniaturizing the imaging element 100a, it is difficult to stably mass-produce the imaging device 1 with the desired characteristics.

[0092] Furthermore, as the imaging element 100 becomes miniaturized, the distance between the charge accumulation section and the slit 312 becomes shorter. Therefore, during the manufacture of the imaging element 100, first conductivity type (e.g., N-type) impurities diffuse from the charge accumulation section, causing potential fluctuations in the diffusion region 306 within the slit 312, which is used to electrically separate pixels 300a and 300b, making separation between pixels 300a and 300b difficult. Furthermore, due to the potential fluctuations in the diffusion region 306, the potential of the overflow path 314 also fluctuates. In some cases, the potential becomes deeper outside the overflow path 314, and an overflow path may be unintentionally formed. When such an overflow path forms, separation between pixels 300a and 300b becomes difficult. Since phase difference detection uses pixel signals based on the difference in charge between a pair of pixels 300a and 300b, if separation between pixels 300a and 300b cannot be achieved in this way, the pixel signals will mix, and the accuracy of phase difference detection will deteriorate.

[0093] Furthermore, as the imaging element 100 becomes miniaturized, the distance between the transmission gate 400, which operates during phase difference detection, and the overflow path 314 becomes shorter. The voltage applied to the transmission gate 400 causes a large fluctuation in the potential of the overflow path 314, which may lead to poor transmission.

[0094] In other words, as the imaging element 100 becomes further miniaturized, during the manufacture of the imaging element 100, first conductivity type (e.g., N-type) impurities diffuse from the charge accumulation section. This causes potential fluctuations in the diffusion region 306 within the slit 312 used for electrical separation between pixels 300a and 300b, making separation between pixels 300a and 300b difficult to achieve. Furthermore, the distance between the transmission gate 400 and the overflow path 314 becomes shorter, and the potential change in the overflow path 314 increases when the transmission gate 400 is turned on / off for charge accumulation / signal output.

[0095] Therefore, in view of this situation, the inventors have created a second embodiment of the present invention as described below. The inventors have conceived that, in order to suppress potential fluctuations in the overflow path 314 and the diffusion region 306 even when the imaging element 100 is miniaturized, the two can be separated by providing an element separation film (shallow trench isolation (STI)) between the charge accumulation portion and the diffusion region 306 of the slit 312 and the overflow path 314. Furthermore, the inventors have conceived an arrangement in which the transmission gate 400 and the overflow path 314 can be further separated. Thus, the inventors have created the second embodiment based on this concept.

[0096] In this embodiment, by providing an STI between the charge accumulation section and the diffusion region 306 within the slit 312 and the overflow path 314, diffusion of first conductivity type (e.g., N-type) impurities from the charge accumulation section into the diffusion region 306 surrounding the overflow path 314 is suppressed during the manufacture of the imaging element 100. Furthermore, by arranging the charge accumulation section and the transfer gate 400 adjacent to each other, the overflow path 314, separated from the charge accumulation section by the STI, can be further separated from the transfer gate 400. As a result, according to this embodiment, it becomes easy to set the potential of the overflow path 314 to the desired state, and even when miniaturizing the imaging element 100, it is possible to stably mass-produce imaging devices 1 with the desired characteristics. These details of this embodiment will be described in turn below.

[0097] <4.2 Example> Next, we will refer to Figures 16 to 22 To illustrate a construction example of the camera element 100 according to this embodiment. Figures 16 to 22 This is an explanatory diagram showing an example of the construction of the camera element 100 according to this embodiment.

[0098] First, it will be explained Figure 16 The example shown. Figure 16 The upper part is with Figure 2 The corresponding method shows a plan view of an example of the planar structure of the camera element 100 in this embodiment. Figure 16 The lower left portion shows the passage along Figure 16 The cross-section obtained by cutting the imaging element 100 with line E-E' in the upper figure. Figure 16 The lower right part shows along Figure 16 The cross-section obtained by cutting the camera element 100 with line F-F' in the upper figure.

[0099] In this embodiment, similar to the comparative example, the imaging element 100 also includes an element separation wall 310 that surrounds the element region of the semiconductor substrate 10 and divides the element region of each imaging element 100. Furthermore, the imaging element 100 has pixels 300a and 300b that are adjacent to each other in the element region surrounded by the element separation wall 310.

[0100] Furthermore, in this embodiment, pixels 300a and 300b are also separated by a pixel separation wall 304 integrally formed with the element separation wall 310. Specifically, the pixel separation wall 304 is configured in the row direction ( Figure 16 In the upper part of the image, pixels 300a and 300b that are adjacent to each other in the left-right direction are separated along the column direction. Figure 16(Extending in the vertical direction in the upper figure). Furthermore, the pixel separation wall 304 has a slit 312 at the center of the imaging element 100. Additionally, in the region within the slit 312 in the semiconductor substrate 10, a second conductivity type (e.g., P-type) impurity diffuses via the pixel separation wall 304 through conformal doping, forming a diffusion region 306. Furthermore, in this embodiment, similarly, a first conductivity type (e.g., N-type) impurity is introduced into the region located on the front side 10b of the semiconductor substrate 10 within the slit 312 by ion implantation to form an overflow path 314.

[0101] Furthermore, in this embodiment, on the front side 10b of the semiconductor substrate 10, a transfer gate 400 for transferring charge is provided for each pixel in pixels 300a and 300b. The transfer gate 400 has a vertical gate portion 400c, which extends from the front side 10b along the depth direction of the semiconductor substrate 10. Around the vertical gate portion 400c, a diffusion region of a first conductive type impurity, a diffusion region of a second conductive type impurity, and a diffusion region of the first conductive type impurity are sequentially arranged from the photoelectric conversion unit 302 toward the charge storage unit 601, which will be described later. Moreover, by applying a voltage to the transfer gate 400, an inversion channel is formed near the interface of the vertical gate portion 400c, thereby transferring the charge from the photoelectric conversion unit 302 to the charge storage unit 601. In this embodiment, by using the transfer gate 400 containing a vertical gate structure with a vertical gate portion 400c, the gate length in the depth direction of the semiconductor substrate 10 can be ensured, and the distance to the diffusion region 306 within the slit 312 can be increased. Therefore, it is possible to suppress large changes in the potential of the diffusion region 306 within the slit 312 caused by changes in the voltage applied to the transmission gate 400 when the transmission gate 400 is turned on / off.

[0102] Furthermore, in this embodiment, the transmission gate 400 is preferably arranged at the corner of the imaging element 100, so that the transmission gate 400 is further away from the slit 312, that is, the transmission gate 400 is further separated from the overflow path 314. In addition, in this embodiment, on the front side 10b of the semiconductor substrate 10, charge accumulation portions 601a and 601b for accumulating charge are respectively provided adjacent to the transmission gate 400 for each pixel 300a and 300b. The charge accumulation portions 601a and 601b contain a first conductivity type (e.g., N-type) impurity. Note that although not shown in the figures, the two charge accumulation portions 601a and 601b can be electrically connected to each other via wiring.

[0103] Furthermore, in this embodiment, an STI (diffusion region separation wall) 330 is provided so as to facilitate the separation of diffusion regions in the column direction ( Figure 16The charge storage portion 601 and the diffusion region 306 within the slit 312 are separated in the vertical direction (as shown in the upper figure). The STI 330 is formed by embedding an insulating film in a trench extending from the front side 10b of the semiconductor substrate 10. Preferably, the STI 330 extends deeper than the charge storage portion 601 in the depth direction (film thickness direction) of the semiconductor substrate 10. In this embodiment, by providing the STI 330 between the charge storage portion 601 and the diffusion region 306 within the slit 312 and the overflow path 314, the diffusion of first conductivity type (e.g., N-type) impurities from the charge storage portion 601 into the diffusion region 306 can be suppressed during the manufacture of the imaging element 100. Note that, as... Figure 16 As shown in the lower right portion, the STI 330 is surrounded by a diffusion region 322 containing a second conductivity type (e.g., P-type) impurity.

[0104] Furthermore, in this embodiment, since the STI 330 is in the row direction of the imaging element 100 ( Figure 16 The transmission gate 400 is further separated from the overflow path 314 disposed within the slit 312 by the STI 330, as it traverses the element separation wall 310 in the left-right direction in the upper figure. In this embodiment, since the overflow path 314 and the transmission gate 400 can be further separated by the STI 330, large changes in the potential of the overflow path 314 can be suppressed when the transmission gate 400 is turned on / off for charge accumulation / signal output.

[0105] also, Figure 17 Therefore with Figure 16 The upper view shows a planar view of an example of the planar structure of the imaging element 100 in this embodiment. Figure 17 In the example shown, the transmission gate 400 may have a generally vertical triangular shape or a generally triangular shape. Specifically, the transmission gate 400 has a generally vertical triangular shape, and the transmission gate 400 is arranged such that the vertical angle of the vertical triangle is located at the corner of the imaging element 100. Figure 17 In the example shown, with this shape and arrangement, the bevel of the transmission gate 400 can be further separated from the slit 312, thus suppressing the potential change of the overflow path 314 when the transmission gate 400 is turned on / off for charge accumulation / signal output. Furthermore, by arranging the shape of the transmission gate 400 in this way, the channel width through which charge passes during charge transfer can be further widened, thereby suppressing image quality degradation due to poor charge transfer.

[0106] also, Figure 18 Therefore with Figure 16 The upper view shows a planar view of an example of the planar structure of the imaging element 100 in this embodiment. Figure 18 In the example shown, the STI 330 is in the row direction of the image sensor 100 ( Figure 18 The transmission gate 400 does not traverse the element separation wall 310 in the left-right direction, but extends only near the center of the imaging element 100. Therefore, in this example, the transmission gate 400 is not separated from the overflow path 314 within the slit 312 by the STI 330. Furthermore, in this example, by extending the transmission gate 400 between the element separation wall 310 and the STI 330, the transmission gate 400 can be closer to the center of the imaging element 100. As a result, in this example, it is easier to transfer the charge of the photoelectric conversion unit 302 during charge transfer, and image quality degradation due to poor transmission can be suppressed.

[0107] also, Figure 19 Therefore with Figure 16 The upper view shows a planar view of an example of the planar structure of the imaging element 100 in this embodiment. Figure 19 In the example shown, the combination of Figure 17 The example shown and Figure 18 The example shown. Through this arrangement, in Figure 19 In the example shown, since the STI 330 does not traverse the element separation wall 310 in the row direction (left-right direction in the figure) of the imaging element 100, but only extends near the center of the imaging element 100, the transfer gate 400, which has a roughly vertical triangular shape, can extend between the element separation wall 310 and the STI 330. Therefore, according to this example, the area of ​​the transfer gate 400 can be increased. As a result, according to this example, since the channel width through which charge passes during charge transfer can be formed to be wider, image quality degradation due to poor charge transfer can be suppressed. Furthermore, in this example, since the transfer gate 400 can be closer to the center of the imaging element 100, it is easier to transfer the charge of the photoelectric conversion unit 302 during charge transfer, and image quality degradation due to poor transfer can be suppressed.

[0108] also, Figure 20 Therefore with Figure 16 The upper view shows a planar view of an example of the planar structure of the imaging element 100 in this embodiment. Figure 20In the example shown, similar to the previous example, the pixel separation wall 304 is configured to extend along the column direction (vertical direction in the figure) between adjacent pixels 300a and 300b in the row direction (left-right direction in the figure). However, in this example, the slit 312 is not located at the center of the imaging element 100, but at a predetermined distance from the center, thereby separating it from the charge accumulation section 601 and the transmission gate 400 in the column direction. Specifically, in this example, the slit 312 is located at a position offset downwards from the center of the imaging element 100 in the figure. In this example, by doing so, since the diffusion region 306 within the transmission gate 400 and the slit 312 can be further separated from each other, it is possible to suppress potential fluctuations in the diffusion region 306 when the transmission gate 400 is turned on / off for charge accumulation / signal output.

[0109] also, Figure 21 The upper part is with Figure 16 The upper view shows a planar view of an example of the planar structure of the camera element 100 in this embodiment. Figure 21 The lower part is an enlarged view of a cross-section of the imaging element 100 taken along line G-G' in the upper diagram. Figure 21 In the example shown, the STI 330 also extends to the upper side of the slit 312 to have an extension 330a. The extension 330a overlaps with the diffusion region 306, which includes multiple diffusion regions 306a, 306b, and 306c with different concentrations formed by a second conductivity type (e.g., P-type) impurity in the depth direction (film thickness direction) of the semiconductor substrate 10. Furthermore, the overflow path 314 also overlaps with the extension 330a in the depth direction of the semiconductor substrate 10. Thus, during manufacturing, a trench that will become the STI 330 is formed in the semiconductor substrate 10, and impurity implantation for forming the overflow path 314 can be performed using this trench through self-alignment. Therefore, in this example, the potential of the overflow path 314 can be more stably adjusted. Note that, as Figure 21 As shown at the top, the STI 330 and the extension 330a are integrally T-shaped. Furthermore, Figure 21 The cross-section of the STI 330 shown at the bottom is not limited to a trapezoid; it can also be a trapezoid with rounded corners. This shape helps to avoid electric field concentration.

[0110] also, Figure 22 Corresponding to along Figure 16 The image sensor 100 is shown in the upper view, with line E-E' representing a cross-section. In this embodiment, the element separation wall 310 and pixel separation wall 304 are not limited to a DTI (dimension lattice) penetrating the semiconductor substrate 10. For example, in... Figure 22In the example shown, the element separation wall 310 and the pixel separation wall 304 may include a back surface DTI 324 and a diffusion region 326. The back surface DTI 324 has a trench extending from the light-receiving surface 10a through the semiconductor substrate 10 to the middle of its film thickness. The diffusion region 326 is configured to overlap with the back surface DTI 324 in the depth direction (film thickness direction) of the semiconductor substrate 10 and contains a second conductivity type (e.g., P-type) impurity.

[0111] As described above, in this embodiment, by providing an STI 330 between the charge storage portion 601 and the diffusion region 306 within the slit 312 and the overflow path 314, the diffusion of first conductivity type (e.g., N-type) impurities from the charge storage portion 601 into the diffusion region 306 surrounding the overflow path 314 is suppressed during the manufacture of the imaging element 100. Furthermore, by arranging the charge storage portion 601 and the transfer gate 400 adjacent to each other, the overflow path 314, separated from the charge storage portion 601 by the STI 330, can be further separated from the transfer gate 400. As a result, according to this embodiment, it becomes easy to set the potential of the overflow path 314 to a desired state, and even when miniaturizing the imaging element 100, imaging devices 1 with desired characteristics can be stably mass-produced.

[0112] Note that this embodiment is not limited to Figures 16 to 22 The structure shown.

[0113] <4.3 Manufacturing Method> Next, we will refer to Figures 23 to 25 The manufacturing method of the camera element 100 according to this embodiment will be explained. Figures 23 to 25 This is an explanatory diagram showing the cross-sectional structure of the camera element 100 in the manufacturing method according to this embodiment.

[0114] First, it will refer to Figure 23 and Figure 24 The manufacturing method of the camera element 100 according to this embodiment will be explained. Figure 23 Corresponding to along Figure 16 The cross-section of the imaging element 100 taken by line E-E' in the diagram. Figure 24 Corresponding to along Figure 16 The cross-section of the camera element 100 is taken by line H-H'.

[0115] First, trenches penetrating the first conductive semiconductor substrate 10 are formed in the semiconductor substrate 10, and insulating films are buried in these trenches to form element separation walls 310 and pixel separation walls 304 (see [link]). Figure 24 (See the top left view and the second view from the left). Furthermore, a shallow trench is formed from the front side 10b of the semiconductor substrate 10, and an insulating film is buried within this trench to form STI 330 (see...). Figure 24 (Third figure from the left in the upper part). Furthermore, a second impurity is implanted on the front 10b side between the STI 330 and the component separation wall 310, and a first impurity is further implanted (see...). Figure 23 The upper left and middle images, and Figure 24 (The upper right image).

[0116] Furthermore, shallow trenches are formed from the front side 10b of the semiconductor substrate 10, and an insulating film, such as a silicon oxide film, is formed in a manner that covers the bottom surface and sidewalls of these trenches (see [link to documentation]). Figure 23 The upper right end diagram and Figure 23 The left end of the middle section, and Figure 24 (The left-hand view of the middle section and the second view from the left). Furthermore, the polycrystalline silicon film is formed by embedding it into trenches, and the upper surface of the polycrystalline silicon film is planarized (see...). Figure 23 The second and third figures from the left in the middle section, and Figure 24 (The third image from the left in the middle section and the rightmost image). Furthermore, the polysilicon film is patterned using a mask or the like with a predetermined pattern to form the transfer gate 400 (see...). Figure 23 The right end of the middle section and Figure 24 (Lower left view). Furthermore, an insulating film, such as a silicon oxide film, is formed to cover the transmission gate 400, and etching is performed such that the insulating film is left only at the ends of the transmission gate 400 (see...). Figure 23 The lower left-hand diagram and the second diagram from the left; and Figure 24 (The second figure from the left and the right figure from the bottom). Furthermore, by implanting a first impurity into the semiconductor substrate 10 between the transmission gates 400 covered by an insulating film (sidewall), a charge accumulation portion 601 is formed at a desired location (see...). Figure 23 (The lower right image).

[0117] In addition, such as Figure 25 As shown, the shape of the insulating film (sidewall) covering the transmission gate 400 can be a drilled structure embedded in the semiconductor substrate 10. By doing so, the electric field generated by the voltage applied to the transmission gate 400 is mitigated, and the appearance of white spots in the imaging element 100 can be suppressed. At this time, as... Figure 25 As shown, a high-temperature silicon oxide film (HTO) is preferably used as the insulating film covering the transmission gate 400. Note that the manufacturing method is the same as that described in the reference. Figure 23 and Figure 24 The process described is the same, so the details will not be explained here.

[0118] [5. Third Embodiment] <5.1 Background and Overview> The third embodiment of the present invention will be described below. First, before describing this embodiment, reference will be made to... Figure 26 This will explain the background that led the inventors to create this embodiment and the summary of this embodiment. Figure 26 This is an explanatory diagram used to illustrate the general outline of this embodiment, and shows the construction of a comparative example of an imaging element 100a that was repeatedly studied by the inventors prior to forming embodiments of the present invention. Specifically, in Figure 26 The left side shows an example of the planar structure of the imaging element 100a according to the comparative example. Figure 26 The right side shows an example of the cross-sectional structure of the imaging element 100a according to the comparative example, and specifically, shows a cross-section taken along line e-e' in the left figure.

[0119] In the comparative examples, such as Figure 26 As shown, the charge generated in the photoelectric conversion unit 302 of pixels 300a and 300b is transferred to the charge storage unit 601 through the transfer gate 400. To efficiently transfer the charge, it is necessary to improve the modulation of the potential within the semiconductor substrate 10 through the transfer gate 400, and as one countermeasure, increasing the area of ​​the transfer gate 400 is conceivable. However, when the area of ​​the transfer gate 400 is increased, as... Figure 26 As shown in the plan view on the left, the transmission gate 400 is located close to the overflow path 314 within the slit 312. Therefore, when the transmission gate 400 is turned on, the charge is not transferred to the charge storage section 601, but instead is transferred from one pixel 300a to the other pixel 300b. Therefore, in the comparative example, there are limitations in increasing the area of ​​the transmission gate 400.

[0120] Furthermore, in comparative examples, such as Figure 26 As shown in the plan view on the left, the charge storage sections 601 are arranged adjacent to each other, so that they can be shared with other pixels 300 and other imaging elements 100a. Furthermore, in this arrangement, the transmission gate 400 is preferably arranged adjacent to the charge storage section 601. Therefore, the arrangement and size of the transmission gate 400 are limited, and thus, in the comparative example, there are also limitations in increasing the area of ​​the transmission gate 400.

[0121] Therefore, in view of this situation, the inventors created the following embodiment. In this embodiment, the charge storage section 601 is arranged symmetrically in both pixels 300a and 300b at the center of the imaging element 100. As a result, the transmission gate 400 can be expanded in width while maintaining symmetry between pixels 300a and 300b, thereby improving the modulation of the transmission gate 400 within the semiconductor substrate 10. As a result, according to this embodiment, even when the imaging element 100 is miniaturized, charge can be efficiently transferred because the area of ​​the transmission gate 400 can be further expanded and the modulation of the potential can be improved. Furthermore, according to this embodiment, since the photoelectric conversion section 302 can also be expanded, the saturation charge (Qs) of each pixel in pixels 300a and 300b can be increased. These details of this embodiment will be described in turn below.

[0122] <5.2 Example> Next, we will refer to Figures 27 to 32 To illustrate a construction example of the camera element 100 according to this embodiment. Figures 27 to 32 This is an explanatory diagram showing an example of the construction of the camera element 100 according to this embodiment.

[0123] First, it will be explained Figure 27 The example shown. Figure 27 The left side with Figure 26 The left-hand diagram illustrates the planar structure of the imaging element 100 according to this embodiment. Furthermore, Figure 27 The middle section shows a cross-section taken along line f-f' in the left-hand diagram. Figure 27 The right side shows a cross-section taken along line g-g' in the left figure.

[0124] In this embodiment, similar to the comparative example, the imaging element 100 also includes an element separation wall 310 that surrounds the element region of the semiconductor substrate 10 and divides the element region of each imaging element 100. Furthermore, the imaging element 100 has pixels 300a and 300b adjacent to each other in the element region surrounded by the element separation wall 310. In addition, in this embodiment, pixels 300a and 300b are also separated by a pixel separation wall 304 integrally formed with the element separation wall 310. Specifically, the pixel separation wall 304 is configured in the row direction (…). Figure 27 In the left-hand image (in the left-right direction), adjacent pixels 300a and 300b are separated along the column direction ( Figure 27(Extending vertically in the left-hand diagram). Furthermore, the pixel separation wall 304 has a slit 312 at the center of the imaging element 100. Additionally, in the region within the slit 312 in the semiconductor substrate 10, a second conductivity type (e.g., P-type) impurity diffuses via the pixel separation wall 304 through conformal doping, forming a diffusion region 306. Furthermore, in this embodiment, similarly, a first conductivity type (e.g., N-type) impurity is introduced into the region of the slit 312 located on the front side 10b of the semiconductor substrate 10 by ion implantation, thereby forming an overflow path 314.

[0125] Furthermore, in this embodiment, the charge storage portion 601 is arranged at the center of the imaging element 100 on the front side 10b of the semiconductor substrate 10. Additionally, in this embodiment, the charge transfer gate 400 is configured to surround the charge storage portion 601. The transfer gate 400 may have a planar gate structure or a vertical gate structure having a vertical gate portion 400c extending from the front side 10b along the depth direction of the semiconductor substrate 10. Furthermore, in this embodiment, the planar shape of the transfer gate 400 is not particularly limited, but a shape with as few corners as possible is preferred to avoid electric field concentration.

[0126] Furthermore, in this embodiment, the charge storage portion 601 is disposed on the front side 10b within the slit 312, and therefore overlaps with the diffusion region 306 and the overflow path 314 in the depth direction (film thickness direction) of the semiconductor substrate 10.

[0127] Furthermore, in this embodiment, such as Figure 27 As shown in the left side diagram, contact pads 390 connected to ground and sink are provided at all four corners of the camera element 100.

[0128] As described above, in this embodiment, the charge storage section 601 is arranged symmetrically in the center of the imaging element 100 between pixels 300a and 300b. By doing so, in this embodiment, since the transmission gate 400 can be expanded while maintaining symmetry between pixels 300a and 300b, the modulation of the transmission gate 400 within the semiconductor substrate 10 can be improved. As a result, according to this embodiment, even when the imaging element 100 is miniaturized, charge can be transferred efficiently because the area of ​​the transmission gate 400 can be further increased and the potential modulation can be improved. Furthermore, according to this embodiment, since the photoelectric conversion section 302 can also be expanded, the saturation charge (Qs) of each pixel in pixels 300a and 300b can be increased.

[0129] In addition, it will be explained Figure 28 The example shown. Figure 28 With Figure 27 The left-hand diagram illustrates the planar structure of the imaging element 100 according to this embodiment. (As shown...) Figure 28 As shown, the charge storage unit 601 can be electrically connected via wiring 340.

[0130] Next, I will explain Figure 29 The example shown. Figure 29 The left side of the image is based on... Figure 27 The left-hand diagram in the figure shows a planar view of an example of the planar structure of the camera element 100 in this embodiment. Figure 29 The right-hand diagram shows a cross-section taken along line h-h' in the left-hand diagram. Figure 29 In the example shown, the transfer gate 400 may have a vertical gate structure having a plurality of vertical gate portions 400c (specifically, two vertical gate portions 400c) extending from the front side 10b along the depth direction of the semiconductor substrate 10. The vertical gate portions 400c are configured to surround the charge storage portion 601 and to contact the charge storage portion 601.

[0131] Next, I will explain Figure 30 The example shown. Figure 30 The left side of the image is based on... Figure 27 The left-hand diagram in the figure shows a planar view of an example of the planar structure of the camera element 100 in this embodiment. Figure 30 The middle figure shows a cross-section taken along line i-i' in the left figure. Figure 30 The right-hand diagram shows a cross-section taken along line j-j' in the left-hand diagram. Figure 30 In the example shown, the pixel separation wall 304 does not have a slit 312 at the center of the imaging element 100. Specifically, the slit 312 is arranged along the column direction ( Figure 30 (In the right-hand diagram, the vertical direction) extends from the center of the imaging element 100 towards... Figure 30 The lower side of the right-hand side is offset by a predetermined distance. Therefore, in this example, the charge accumulation section 601 is not provided on the front side 10b within the slit 312, and does not overlap with the diffusion region 306 and the overflow path 314 in the depth direction of the semiconductor substrate 10. Note that, for example, the position of the slit 312 can be changed according to the position of the imaging element 100 in the pixel array section 30.

[0132] Next, I will explain Figure 31 The example shown. Figure 31 The left side of the image is based on... Figure 27 The left-hand diagram in the figure shows a planar view of an example of the planar structure of the camera element 100 in this embodiment. Figure 31 The middle figure shows a cross-section taken along line i-i' in the left figure. Figure 31The right-hand diagram shows a cross-section taken along line j-j' in the left-hand diagram. Figure 31 In the example shown, the pixel separator 304 is along the column direction ( Figure 30 In the right-hand figure (vertical direction), there are multiple slits 312 at a position offset from the center of the imaging element 100 by a predetermined distance. Therefore, in this example, the charge storage portion 601 is not provided on the front side 10b within the slits 312, and does not overlap with the diffusion region 306 and the overflow path 314 in the depth direction of the semiconductor substrate 10.

[0133] Next, I will explain Figure 32 The example shown. Figure 32 Therefore, with Figure 27 The left-hand diagram shows a plan view of an example of the planar structure of the imaging element 100 of this embodiment. In the example described so far, contact pads 390 connected to the ground and the sink are provided at all four corners of the imaging element 100. However, this embodiment is not limited to this arrangement, such as... Figure 32 As shown, the contact pads 390 can be provided only in a portion of the four corners of the imaging element 100. By doing so, the restrictions on the arrangement of the components are reduced, for example, the area of ​​the transmission gate 400 can be increased.

[0134] As described above, in this embodiment, the charge storage section 601 is arranged symmetrically in the center of the imaging element 100 between pixels 300a and 300b. By doing so, in this embodiment, since the transmission gate 400 can be expanded while maintaining symmetry between pixels 300a and 300b, the modulation of the transmission gate 400 within the semiconductor substrate 10 can be improved. As a result, according to this embodiment, even when the imaging element 100 is miniaturized, charge can be transferred efficiently because the area of ​​the transmission gate 400 can be further increased and the potential modulation can be improved. Furthermore, according to this embodiment, since the photoelectric conversion section 302 can also be expanded, the saturation charge (Qs) of each pixel in pixels 300a and 300b can be increased.

[0135] Note that this embodiment is not limited to Figures 27 to 32 The structure shown.

[0136] <5.3 Manufacturing Method> Next, we will refer to Figures 33A to 33H The manufacturing method of the camera element 100 according to this embodiment will be explained. Figures 33A to 33H This is an explanatory diagram showing the cross-sectional structure of the camera element 100 in the manufacturing method according to this embodiment.

[0137] like Figure 33AAs shown in the upper part, a silicon nitride film 501 and a tetraethoxysilane (TEOS)-based oxide film 502 are sequentially stacked on a semiconductor substrate 10 having a thermal oxide film (not shown) on its surface. Next, as... Figure 33A As shown in the lower part, the TEOS-based oxide film 502 is patterned.

[0138] Next, as Figure 33B As shown in the upper part, the silicon nitride film 501 and the semiconductor substrate 10 are etched according to a pattern, and the silicon nitride film 503 is formed in such a way that it covers the sidewalls of the formed trench and the upper surface of the TEOS-based oxide film 502. Furthermore, as... Figure 33B As shown in the lower part, a trench is formed through the semiconductor substrate 10 according to the trench pattern.

[0139] like Figure 33C As shown in the upper part, a film 504 containing the second impurity is formed in a manner covering the sidewalls of the trench, and the second impurity is diffused into a portion of the semiconductor substrate 10 by applying heat. Then, as... Figure 33C As shown in the lower part, the silicon nitride film 503 and the TEOS-based oxide film 502 are removed.

[0140] Next, as Figure 33D As shown in the upper part, a polycrystalline silicon film 506 is formed and embedded in the trench. Furthermore, as... Figure 33D As shown in the lower part, the polysilicon film 506 is removed from the region protruding from the trench and the region in the upper part of the trench.

[0141] Next, as Figure 33E As shown in the upper part, a silicon oxide film 507 is formed and embedded in the trench. Furthermore, as... Figure 33E As shown in the lower part, the silicon oxide film 507 protruding from the trench is removed.

[0142] Next, as Figure 33F As shown in the upper part, a tetraethoxysilane (TEOS)-based oxide film 508 is stacked and patterned. Furthermore, as... Figure 33F As shown in the lower part, a second impurity is injected into the semiconductor substrate 10 through the gaps in the pattern to form a diffusion region 509.

[0143] In addition, such as Figure 33G As shown in the upper part, the tetraethoxysilane (TEOS)-based oxide film 508 is removed, and shallow trenches are formed on the front side of the semiconductor substrate 10. A silicon oxide film 510 is then formed to cover the bottom, side, and outermost surfaces of these trenches. Furthermore, a polysilicon film 511 is formed to be embedded in the trenches. Next, a mask 512 is formed on the polysilicon film 511. Additionally, as... Figure 33GAs shown in the lower part, the pattern is formed according to the pattern of the mask 512 to form the transmission gate 400. In addition, first impurities such as impurities are implanted into the region of the semiconductor substrate 10 located between the transmission gates 400.

[0144] In addition, such as Figure 33H As shown in the upper part, an insulating film 513 is formed in a manner that covers the transmission gate 400. Then, as... Figure 33H As shown in the lower part, contact element 514 is formed.

[0145] [6. Fourth Embodiment] <6.1 Background and Overview> The fourth embodiment of the present invention will be described below. First, before describing this embodiment, reference will be made to... Figure 34 and Figure 35 This will explain the background that led the inventors to create this embodiment and the summary of this embodiment. Figure 34 and Figure 35 This is an explanatory diagram used to explain the background of this embodiment. Specifically, Figure 34 This is an explanatory diagram showing a construction example of the imaging element 100a according to a comparative example, wherein a planar construction example of the imaging element 100a is shown on the left, and a cross-sectional construction example is shown on the right, obtained by cutting the imaging element 100a along line P-P' in the left figure. Furthermore, Figure 35 An example of charge movement path is shown in the comparative example.

[0146] In this comparative example, such as Figure 34 As shown, similarly, the imaging element 100a also has an element separation wall 310, which surrounds the element region of the semiconductor substrate 10 and divides the element region of each imaging element 100. Then, the imaging element 100 has pixels 300a and 300b adjacent to each other in the element region surrounded by the element separation wall 310. In this comparative example, similarly, pixels 300a and 300b are separated by a pixel separation wall 304 integrally formed with the element separation wall 310. Specifically, the pixel separation wall 304 is configured in the row direction (… Figure 34 In the left-hand image (in the left-right direction), adjacent pixels 300a and 300b are separated along the column direction ( Figure 34 (Extending vertically in the left-hand image). Furthermore, the pixel separation wall 304 has a slit 312 at the center of the imaging element 100. Additionally, a diffusion region 306, in which a second conductivity type (e.g., P-type) impurity has been diffused, is formed within the slit 312 in the semiconductor substrate 10.

[0147] Furthermore, in this comparative example, on the front side 10b of the semiconductor substrate 10, a transfer gate 400 for transferring charge is provided for each pixel in pixels 300a and 300b. Specifically, the transfer gate 400 is disposed at the center of each of pixels 300a and 300b in a plan view, and has a vertical gate portion 400c extending from the front side 10b along the depth direction of the semiconductor substrate 10 in a cross-sectional view. In this comparative example, as shown from... Figure 34 As can be seen in the right-hand cross-sectional view, the vertical gate portion 400c is located above the pixel centroid 650, which is the center of the photoelectric conversion section 302 of pixels 300a and 300b. Furthermore, by applying a voltage to the transmission gate 400, an inversion channel is generated near the interface of the vertical gate portion 400c. Therefore, the charge from the photoelectric conversion section 302 is transferred to the charge storage section 601 through this channel.

[0148] Furthermore, in this comparative example, the imaging element 100a includes charge storage sections 601a and 601b for storing charge, which are located along the... Figure 34 The component separation wall 310 is provided on the upper side of the left side of the diagram. Furthermore, the component separation wall 310 near the charge storage portions 601a and 601b is provided with a side contact portion 620a. Additionally, the imaging element 100a includes components located along the... Figure 34 A grounding portion (GND) (not shown) is provided on the lower side of the component separation wall 310 at the left side of the left-hand view. Furthermore, a ground contact portion 620b is provided on the component separation wall 310 near this grounding portion. In this comparative example, each pixel 300a and 300b is provided with a charge storage portion 601a and 601b and a grounding portion. Furthermore, in the plan view of each pixel in pixels 300a and 300b, the charge storage portions 601a and 601b and the grounding portion are in a point-symmetrical position with respect to the transmission gate 400.

[0149] Furthermore, in the imaging element 100a according to this comparative example, with miniaturization, it is difficult to form the vertical gate portion 400c of the transmission gate 400 at a predetermined position with high precision. Moreover, if the position of the vertical gate portion 400c is slightly off, an unexpected charge transport path will occur, and charge will be generated that is not transferred to the charge accumulation portion 601. In other words, it can be said that in the comparative example, the transmission robustness against misalignment of the vertical gate portion 400c is poor.

[0150] Specifically, such as Figure 35 As shown in the left-hand diagram, when the vertical gate portion 400c is formed at a predetermined position directly above the pixel centroid 650, by applying a voltage to the transfer gate 400, an inversion channel is generated at the desired position, and thus the charge from the photoelectric conversion unit 302 is transferred to the charge storage unit 601 through the aforementioned channel. On the other hand, as Figure 35 As shown in the right-hand diagram, if the vertical gate portion 400c is not formed at a predetermined position directly above the pixel centroid 650, an inversion channel (the channel on the opposite side of the charge storage portion 601 in this diagram) may occur even in an unexpected position, and the charge from the photoelectric conversion portion 302 may not be transferred to the charge storage portion 601.

[0151] Therefore, in view of this situation, the inventors have created a fourth embodiment of the present invention as described below. The inventors envisioned controlling the impurity concentration in pixels 300a and 300b and shifting the position of the pixel centroid 650 by adjusting the pattern (range) of the diffusion region 306 diffused with a second conductivity type (e.g., P-type) impurity, thereby avoiding the degradation of transmission robustness due to unintended charge transport paths as described above. Furthermore, if the pixel centroid 650 can be shifted relative to the vertical gate portion 400c towards the charge accumulation portion 601, more charge can be stably transferred to the charge accumulation portion 601 through the inversion channel generated on the surface of the vertical gate portion 400c located at the center of pixel 300. Thus, the inventors created the fourth embodiment based on this idea. This fourth embodiment of the present invention will be described in detail below.

[0152] <6.2 Example> Next, we will refer to Figure 36A , Figure 36B and Figure 37 To illustrate a construction example of the camera element 100 according to this embodiment. Figure 36A This is an explanatory diagram showing an example of the planar structure of the camera element 100 according to this embodiment. Figure 36B This is an explanatory diagram showing an example of the cross-sectional structure of the imaging element 100 according to this embodiment, and specifically, it shows the cross-sectional structure of the imaging element 100 along... Figure 36A Example of cross-sectional structure obtained by cutting the imaging element 100 with lines X-X', Y-Y' and Z-Z' as shown. Figure 37 This is an explanatory diagram showing an example of the planar layout construction of the camera element 100 according to this embodiment.

[0153] In this embodiment, similarly to the comparative example, as... Figure 36A and Figure 36BAs shown, the pixels 300 of the imaging element 100 are surrounded by an element separation wall 310. The element separation wall 310 includes a trench (not shown) serving as a through-dTI (Diode Transmission Injection Layer) and an oxide film embedded in the trench, the trench being configured to penetrate the semiconductor substrate 10 along its film thickness direction. Furthermore, in this embodiment, similarly, the pixels 300 are separated from adjacent pixels 300 in the same imaging element 100 by a pixel separation wall 304 integrally formed with the element separation wall 310. The pixel separation wall 304 includes a trench (not shown) serving as a through-dTI and an oxide film embedded in the trench, the trench being configured to penetrate the semiconductor substrate 10 along its film thickness direction.

[0154] Furthermore, in this embodiment, each pixel 300 includes a photoelectric conversion unit 302. For example, the photoelectric conversion unit 302 has a first conductivity type (e.g., N-type) impurity in the second conductivity type (e.g., P-type) semiconductor substrate 10. The photoelectric conversion unit 302 can absorb incident light and generate charge.

[0155] Furthermore, in this embodiment, similarly, on the front side 10b of the semiconductor substrate 10, a transfer gate 400 for transferring charge is provided for each pixel 300. Specifically, the transfer gate 400 (in Figure 36A and Figure 36B In the diagram, only the vertical gate portion 400c is shown. Figure 36A In the plan view shown, it is placed at the center of pixel 300, and in Figure 36B The cross-sectional view shown includes a vertical gate portion 400c extending from the front side 10b along the depth direction of the semiconductor substrate 10.

[0156] Furthermore, in this embodiment, pixel 300 similarly has a charge accumulation section (floating diffusion section) 601 for accumulating charge, which is disposed along the element separation wall 310 located at the corner of pixel 300, specifically along the... Figure 36A A component separation wall 310 is provided on the upper side of the pixel 300. Specifically, the charge storage portion 601 is a semiconductor region having a first conductivity type (e.g., N-type) provided in the semiconductor substrate 10. Furthermore, a side contact portion 620a is provided on the component separation wall 310 near the charge storage portion 601. Additionally, the pixel 300 includes a ground portion (GND) 602 provided at another corner of the pixel 300; specifically, a ground portion 602 is provided at the upper side of the pixel 300. Figure 36A The component separation wall 310 on the lower side has a grounding portion (GND) 602. Furthermore, the component separation wall 310 near the grounding portion 602 is provided with a grounding contact portion 620b. Similarly, in this embodiment, the charge storage portion 601 and the grounding portion 602 are in a point-symmetrical position with respect to the transmission gate 400 (specifically, the vertical gate portion 400c of the transmission gate).

[0157] Furthermore, in this embodiment, the pixel separation wall 304 also has a slit 312 at the center of the imaging element 100. Specifically, as Figure 36A As shown, the pixel separation wall 304 includes a pair of wall portions (first wall portion and second wall portion) 304a and 304b facing each other across a slit 312. More specifically, wall portion 304a is located at... Figure 36A On the upper side of the charge storage section 601, the wall section 304b is located Figure 36A The grounding part 602 side on the lower side.

[0158] In this embodiment, similarly, a diffusion region (first diffusion region) 306, in which a second conductivity type (e.g., P-type) impurity has been diffused, is formed in the region within the slit 312 in the semiconductor substrate 10. Furthermore, unlike the comparative example, in this embodiment, the diffusion region 306 is formed to extend along the wall portion 304b (see [reference]). Figure 36A (The arrow in the image). In other words, in this embodiment, the camera element 100 has a diffusion region (first diffusion region) 306 provided in the slit 312, and a diffusion region (second diffusion region) 306 that is provided to extend along the wall portion 304b on the side of the ground portion 602.

[0159] In this embodiment, as described above, the diffusion region 306 is provided such that it extends from the slit 312 along the wall portion 304b on the side of the ground portion 602. Furthermore, in this embodiment, when... Figure 36B The concentration of the second conductivity type impurity in the region shown by the X-X' cross-section is related to Figure 36B When comparing the concentration of the second conductivity type impurity in the region shown in the Y-Y' cross-section, the concentration in the region shown in the X-X' cross-section is higher. That is, in this embodiment, by providing the diffusion region 306 extending from the slit 312 along the wall portion 304b on the ground portion 602 side, the concentration of P-type impurities in the region shown in the X-X' cross-section is increased. Furthermore, in this embodiment, by employing this impurity concentration distribution, although the volume of the photoelectric conversion unit 302 is slightly reduced and the saturated charge is slightly reduced, the pixel centroid 650 can be shifted towards the charge accumulation unit 601 side, such as... Figure 36B The Z-Z' cross-section is shown. Therefore, according to this embodiment, by generating an inversion channel on the surface of the vertical gate portion 400c located at the center of pixel 300, more charge can be stably transferred to the charge accumulation portion 601. As a result, according to this embodiment, the transfer robustness against positional misalignment of the vertical gate portion 400c can be improved. Furthermore, in this embodiment, since the above-described form can be easily formed without the need for additional new processes, the manufacturing cost of the imaging device 1 is not increased.

[0160] Note that this embodiment is not limited to Figure 36A , Figure 36B and Figure 37 The structure shown is as follows. For example, the imaging element 100 may also include an on-chip lens 200 disposed above the light-receiving surface 10a of the semiconductor substrate 10.

[0161] In addition, such as Figure 37 As shown, the camera elements 100 according to this embodiment can be arranged in a form of 2 vertical x 2 horizontal. Specifically, in Figure 37 In the example shown, each camera element 100 is arranged such that the ground portion 602 of each camera element 100 faces the ground plane. Figure 37 The grounding portion 602 of each adjacent imaging element 100 in the vertical direction. At this time, the diffusion region 306 can be configured to be connected to the grounding portion 602 of each imaging element 100 in the vertical direction. Figure 37 Another diffusion region 306 is adjacent to it in the vertical direction.

[0162] As described above, in this embodiment, the diffusion region 306 is provided such that it extends from the slit 312 along the wall portion 304b on the ground portion 602 side, thereby increasing the concentration of P-type impurities in the region on the ground portion 602 side. Therefore, in this embodiment, by employing this impurity concentration distribution, the pixel centroid 650 can be shifted towards the charge accumulation portion 601. Thus, according to this embodiment, by generating a reversal channel on the surface of the vertical gate portion 400c located at the center of the pixel 300, more charge can be stably transferred to the charge accumulation portion 601. As a result, according to this embodiment, the transfer robustness against positional misalignment of the vertical gate portion 400c can be improved. Furthermore, in this embodiment, since the above-described form can be easily formed without the need for additional new processes, the manufacturing cost of the imaging device 1 is not increased.

[0163] <6.3 Variations> Next, variations of this embodiment will be described.

[0164] (Variation Example 1) First, it will refer to Figure 38 Let's illustrate a variation of this embodiment, Example 1. Figure 38 This is an explanatory diagram showing an example of the planar layout construction of the imaging element 100 according to a modified example 1 of this embodiment, and specifically corresponding to... Figure 37 The planar layout shown.

[0165] like Figure 38 As shown, the camera elements 100 according to this modified example can be arranged in a form of 2 vertically × 1 horizontally. Specifically, in Figure 38 In the example shown, each camera element 100 is arranged such that the ground portion 602 of each camera element 100 faces the ground plane. Figure 38 The grounding portion 602 of each adjacent imaging element 100 in the vertical direction. However, with Figure 37 Unlike the previous example, in this modified example, each diffusion region 306 is configured to be separated from the other diffusion regions 306. By doing so, according to this modified example, compared to the previous embodiment, the pixel centroid 650 can be shifted towards the charge accumulation portion 601 side while suppressing the reduction of saturation charge. Therefore, according to this modified example, the transmission robustness against positional misalignment of the vertical gate portion 400c can be improved.

[0166] (Variation Example 2) Next, we will refer to Figure 39 Let's illustrate a variation of this embodiment, Example 2. Figure 39 This is an explanatory diagram showing an example of the planar layout of the imaging element 100 according to a modified example 2 of this embodiment, and specifically corresponding to... Figure 37 The floor plan shown is shown in the diagram.

[0167] like Figure 39 As shown, the camera element 100 according to this modified example can also be arranged in a form of 2 vertically × 1 horizontally. Specifically, in Figure 39 In the example shown, each camera element 100 is arranged such that the ground portion 602 of each camera element 100 faces the ground plane. Figure 38 The grounding portion 602 of each adjacent imaging element 100 in the vertical direction. Furthermore, in this modified example, similar to this embodiment, the diffusion region 306 is configured to connect to the grounding portion 602 of the imaging element 100 in the vertical direction. Figure 39 Another diffusion region 306 adjacent to it in the vertical direction. Furthermore, in this modified example, the imaging element 100 includes a diffusion region (third diffusion region) 306h, which in... Figure 39 The element separation wall 310, located on the grounding portion 602 side, is disposed along a portion of the plan view and contains a second conductivity type (e.g., P-type) impurity. By doing so, according to this Modification 2, although the saturation charge is less than that of Modification 1, the pixel centroid 650 can be shifted towards the charge accumulation portion 601 side. Therefore, according to this Modification 2, the transmission robustness against positional misalignment of the vertical gate portion 400c can be improved.

[0168] As described above, it can be seen from this embodiment and Modifications 1 and 2 that by adjusting the range of the diffusion region 306 (the length of the diffusion region 306 extending to the ground portion 602) to increase the P-type impurity concentration in the region on the ground portion 602 side, the volume of the photoelectric conversion unit 302 is slightly reduced, and the saturated charge is slightly reduced. However, due to the trade-off with the saturated charge, the pixel centroid 650 can shift towards the charge accumulation unit 601 side depending on the reduction in the saturated charge. Therefore, in this embodiment and Modifications 1 and 2, it is preferable to set the range of the diffusion region 306 considering the above-mentioned trade-off.

[0169] (Variation Example 3) Next, we will refer to Figure 40A and Figure 40B Let's illustrate a variation of this embodiment, Example 3. Figure 40A This is an explanatory diagram showing an example of the planar structure of the camera element 100 according to a modified example 3 of this embodiment. Figure 40B This is an explanatory diagram showing an example of the cross-sectional structure of the imaging element 100 according to a modified example 3 of this embodiment, and specifically showing the cross-sectional structure of the imaging element 100 along... Figure 40A Example of cross-sectional structure obtained by cutting the imaging element 100 with lines X-X', Y-Y' and Z-Z' as shown.

[0170] In this variation 3, similarly, as Figure 40A As shown, in the region within the slit 312 in the semiconductor substrate 10, a second conductivity type (e.g., P-type) impurity diffuses to form a diffusion region (first diffusion region) 306j. Furthermore, in this modified example 3, the diffusion region 306d is also configured to extend along the wall portion 304b (see [reference]). Figure 40A (The arrow in the image). However, in this modified example, the diffusion regions 306d and 306j are positioned differently from the front surface 10b of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. Specifically, as shown... Figure 40B As shown in the cross-section taken along line Z-Z', the diffusion region (first diffusion region) 306j is disposed at a deeper location, while the diffusion region (second diffusion region) 306d is disposed at a shallower location. In other words, the diffusion region 306j is disposed at a deeper location within the semiconductor substrate 10 than the diffusion region 306d.

[0171] By doing so, in this variation, the trade-off between the saturation charge and the offset of the pixel centroid 650, as described above, is eliminated. Specifically, in this variation, as... Figure 40BAs shown in the Z-Z' cross-section, at a relatively shallow location within the semiconductor substrate 10 related to charge transport, the pixel centroid 650 can be shifted towards the charge accumulation section 601. On the other hand, at a relatively deep location within the semiconductor substrate 10 where the photoelectric conversion section 302 related to charge generation is located, the diffusion of second conductivity type (e.g., P-type) impurities is suppressed, thus the volume of the photoelectric conversion section 302 does not decrease, and a reduction in the amount of saturated charge can be avoided. Therefore, according to this modification, while suppressing a reduction in the amount of saturated charge, the pixel centroid 650 can be shifted towards the charge accumulation section 601 at a relatively deep location within the semiconductor substrate 10. As a result, according to this modification, through the inversion channel generated on the surface of the vertical gate section 400c, more charge can be stably transferred to the charge accumulation section 601, and furthermore, the transport robustness against positional misalignment of the vertical gate section 400c can be improved.

[0172] Note that the imaging element 100 according to this modified example can be as follows: Figure 37 The layout shown in the example planar layout of this embodiment can be arranged as follows, or it can be arranged as follows: Figure 38 and Figure 39 The planar layout examples of Modified Example 1 and Modified Example 2 are shown. In this case, the diffusion region (first diffusion region) 306j within the slit 312 is formed at a deeper location in the semiconductor substrate 10, while other diffusion regions are formed at a shallower location in the semiconductor substrate 10.

[0173] (Variation Example 4) Next, we will refer to Figure 41A and Figure 41B Let's illustrate variation 4 of this embodiment. Figure 41A This is an explanatory diagram showing an example of the planar structure of the camera element 100 according to a modified example 4 of this embodiment. Figure 41B This is an explanatory diagram showing an example of the cross-sectional structure of the imaging element 100 according to a modified example 4 of this embodiment, and specifically showing the cross-sectional structure of the imaging element 100 along... Figure 41A Example of cross-sectional structure obtained by cutting the imaging element 100 with lines X-X', Y-Y' and Z-Z' as shown.

[0174] In this variation, such as Figure 41A As shown, instead of providing a diffusion region 306 extending from the slit 312 along the wall portion 304b on the ground portion 602 side, a diffusion region (second diffusion region) 306e containing a second conductivity type (e.g., P-type) impurity is provided on the ground portion 602 side of the pixel 300. In this modified example, by providing the diffusion region 306e on the ground portion 602 side, it is expected that holes can be supplied from the ground portion 602.

[0175] Furthermore, in this variant example, such as Figure 41B As shown in the Z-Z' section, the diffusion region (first diffusion region) 306 is set in a deeper position, while the diffusion region (second diffusion region) 306e is only set in a shallower position.

[0176] By doing so, in this variant, the trade-off between the saturation charge and the offset of the pixel centroid 650, as described above, is also eliminated. Specifically, in this variant, as... Figure 41B As shown in the Z-Z' cross-section, at a relatively shallow location within the semiconductor substrate 10 related to charge transport, the pixel centroid 650 can be shifted towards the charge accumulation section 601. On the other hand, at a relatively deep location within the semiconductor substrate 10 where the photoelectric conversion section 302 related to charge generation is located, the diffusion of second conductivity type (e.g., P-type) impurities is suppressed, thus the volume of the photoelectric conversion section 302 does not decrease, and a reduction in the amount of saturated charge can be avoided. Therefore, according to this modification, while suppressing a reduction in the amount of saturated charge, the pixel centroid 650 can be shifted towards the charge accumulation section 601 at a relatively deep location within the semiconductor substrate 10. As a result, according to this modification, through the inversion channel generated on the surface of the vertical gate section 400c, more charge can be stably transferred to the charge accumulation section 601, and the transport robustness against positional misalignment of the vertical gate section 400c can be improved.

[0177] (Modifications 5 to 7) Next, we will refer to Figures 42 to 44 The following describes variations 5 to 7 of this embodiment. Figure 42 This is an explanatory diagram showing an example of the planar layout structure of the imaging element 100 according to Modification 5 of this embodiment. Figure 43 This is an illustrative diagram showing an example of the planar layout structure of the imaging element 100 according to a modified example 6 of this embodiment. Figure 44 This is an explanatory diagram showing an example of the planar layout construction of the imaging element 100 according to a variation 7 of this embodiment. In these variations, such as... Figures 42 to 44 As shown, the slit 312 is not located at the center of the imaging element 100, but is located on the side of the grounding portion 602. Furthermore, in these modified examples, the diffusion region 306 is also located in the slit 312.

[0178] Specifically, such as Figure 42 As shown, the camera element 100 according to this modified example 5 can be arranged in a form of 2 vertically × 1 horizontally. Specifically, in Figure 42 In the example shown, each camera element 100 is arranged such that the ground portion 602 of each camera element 100 faces the ground plane. Figure 42The grounding portion 602 of each adjacent imaging element 400 in the vertical direction. Furthermore, in this modified example, the diffusion region 306 can be configured to connect to... Figure 42 Another diffusion region 306 is adjacent to it in the vertical direction. Thus, according to this modification, region Q can contain a higher concentration of the second conductivity type (e.g., P-type) impurities compared to region R. Therefore, according to this modification, the pixel centroid 650 can be shifted towards the charge accumulation section 601. As a result, according to this modification, more charge can be stably transferred to the charge accumulation section 601 through the inversion channel generated on the surface of the vertical gate section 400c, and the transfer robustness against positional misalignment of the vertical gate section 400c can be improved.

[0179] In addition, such as Figure 43 As shown, the camera element 100 according to this modified example 6 can also be arranged in a form of 2 vertically × 1 horizontally. Specifically, in Figure 43 In the example shown, each camera element 100 is arranged such that the ground portion 602 of each camera element 100 faces the ground plane. Figure 43 The grounding portion 602 of each adjacent imaging element 100 in the vertical direction. Furthermore, in this modified example, the diffusion region 306 is configured to connect to the grounding portion 602 of the image sensor 100. Figure 43 Another diffusion region 306 is adjacent to it in the vertical direction. Furthermore, in this modification, the imaging element 100 has a diffusion region (second diffusion region) 306k, which is disposed along a portion of the element separation wall 310 located on the grounding portion 602 side and contains a second conductivity type (e.g., P-type) impurity. With this arrangement, according to this modification 6, although the saturation charge is less than that of modification 5, the pixel centroid 650 can be shifted towards the charge accumulation portion 601 side. Therefore, according to this modification 2, the transmission robustness against positional misalignment of the vertical gate portion 400c can be further improved.

[0180] In addition, such as Figure 44 As shown, the camera element 100 according to this modified example 7 can also be arranged in a form of 2 vertically × 1 horizontally. Specifically, in Figure 44 In the example shown, each camera element 100 is arranged such that the ground portion 602 of each camera element 100 faces the ground plane. Figure 44 The grounding portion 602 of each adjacent imaging element 100 in the vertical direction. Furthermore, in this modified example, the diffusion region 306g is configured to connect to the grounding portion 602 of the image sensor 100. Figure 44Another diffusion region 306g is adjacent to it in the vertical direction. Furthermore, in this modified example, the imaging element 100 also has a diffusion region (second diffusion region) 306f, which is disposed along a portion of the element separation wall 310 located on the ground portion 602 side and contains a second conductivity type (e.g., P-type) impurity. Furthermore, in this modified example, the diffusion region 306g is disposed at a deeper location in the semiconductor substrate 10, while the diffusion region 306f is disposed only at a shallower location.

[0181] By doing so, in this modified example, at a relatively shallow location within the semiconductor substrate 10 related to charge transport, the pixel center of gravity 650 can be shifted towards the charge accumulation section 601. On the other hand, at a relatively deep location within the semiconductor substrate 10 where the photoelectric conversion section 302 related to charge generation is located, the diffusion of second conductivity type (e.g., P-type) impurities is suppressed, thus the volume of the photoelectric conversion section is not reduced, and a reduction in the amount of saturated charge can be avoided. Therefore, according to this modified example, while suppressing a reduction in the amount of saturated charge, the pixel center of gravity 650 can be shifted towards the charge accumulation section 601 at a relatively deep location within the semiconductor substrate 10. As a result, according to this modified example, through the inversion channel generated on the surface of the vertical gate section 400c, more charge can be stably transferred to the charge accumulation section 601, and the transport robustness against positional misalignment of the vertical gate section 400c can be improved.

[0182] Note that variations of this embodiment are not limited to... Figures 38 to 44 The structure shown.

[0183] [7. Summary] As described above, according to various embodiments of the present invention, even in scenarios of further miniaturization of the imaging element 100 or mass production of the imaging device 1, various characteristics of the imaging element can be further improved.

[0184] Note that the embodiments of the present invention described above have illustrated the application of the invention to a back-illuminated CMOS image sensor structure. However, the embodiments of the present invention are not limited thereto and can be applied to other structures.

[0185] Note that in the above embodiments of the present invention, an imaging element 100 with a first conductivity type of N-type, a second conductivity type of P-type, and electrons used as signal charges has been described, but the embodiments of the present invention are not limited to such examples. For example, this embodiment can be applied to an imaging element 100 with a first conductivity type of P-type, a second conductivity type of N-type, and holes used as signal charges.

[0186] Furthermore, in the embodiments of the present invention described above, the semiconductor substrate 10 is not necessarily a silicon substrate, but may be another substrate (e.g., silicon-on-insulator (SOI) substrate, SiGe substrate, etc.). In addition, the semiconductor substrate 10 may have semiconductor structures formed on such various substrates.

[0187] Furthermore, the imaging device 1 according to embodiments of the present invention is not limited to an imaging device that detects the distribution of incident visible light and captures that distribution as an image. For example, this embodiment can be applied to an imaging device that captures the distribution of incident infrared, X-ray, particle, etc., as an image, or to an imaging device (physical quantity distribution detection device) such as a fingerprint sensor that detects the distribution of other physical quantities such as pressure and electrostatic capacitance and captures them as an image.

[0188] Furthermore, the camera device 1 according to an embodiment of the present invention can be manufactured using methods, equipment, and conditions for manufacturing general semiconductor devices. That is, the camera device 1 according to this embodiment can be manufactured using existing semiconductor device manufacturing processes.

[0189] Note that examples of the methods mentioned above include physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). Examples of PVD methods include vacuum vapor deposition, electron beam (EB) vapor deposition, various sputtering methods (magnetron sputtering, RF-DC coupled bias sputtering, electron cyclotron resonance (ECR) sputtering, opposed target sputtering, high-frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE), and laser transfer. Furthermore, examples of CVD methods include plasma CVD, thermal CVD, metal-organic (MO) CVD, and photoCVD. In addition, other methods include: electroplating, electroless plating, and spin coating; immersion coating; casting; micro-contact printing; drip coating; various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing; stamping methods; spray coating; various coating methods such as blade coating, squeegee coating, bar coating, knife coating, extrusion coating, and reverse roller coating; transfer roller coating; gravure coating, kissing coating, cast coating, spray coating, slotted hole coating, and calendering coating. Furthermore, examples of patterning methods include: chemical etching methods such as shadow masks, laser transfer, and photolithography; and physical etching methods using ultraviolet light, lasers, etc. Additionally, examples of planarization techniques include chemical mechanical polishing (CMP), laser planarization, and reflow.

[0190] [8. Application Examples] <8.1 Examples of Camera Application> The technology according to the present invention (the technology) can be further applied to various products. For example, the technology according to the present invention can be applied to cameras, etc. Therefore, reference will be made to... Figure 45 Here is a construction example of a camera 700 that is an electronic device to which this technology is applied. Figure 45 This is an explanatory diagram illustrating an example of a schematic functional configuration of a camera 700 to which the technology (the present technology) can be applied.

[0191] like Figure 45 As shown, the camera 700 includes an imaging device 702, an optical lens 710, a shutter mechanism 712, a drive circuit section 714, and a signal processing circuit section 716. The optical lens 710 causes image light (incident light) from the subject to be imaged on the imaging surface of the imaging device 702. As a result, signal charge is accumulated in the imaging element 100 of the imaging device 702 for a period of time. The shutter mechanism 712 opens and closes to control the light illumination period and light blocking period of the imaging device 702. The drive circuit section 714 provides drive signals to these objects for controlling the signal transmission operation of the imaging device 702, the shutter operation of the shutter mechanism 712, etc. That is, the imaging device 702 performs signal transmission based on the drive signal (timing signal) provided from the drive circuit section 714. The signal processing circuit section 716 performs various signal processing operations. For example, the signal processing circuit section 716 outputs the processed video signal to a storage medium (not shown) such as a memory or a display unit (not shown).

[0192] <8.2 Examples of Application for Smartphones> For example, the technology according to the present invention can be applied to smartphones, etc. Therefore, reference will be made to... Figure 46 Here is a construction example of a smartphone 900, which is an electronic device that applies this technology. Figure 46 This is a block diagram illustrating an example of a schematic functional configuration of a smartphone 900 to which the technology (the present technology) can be applied.

[0193] like Figure 46 As shown, the smartphone 900 includes a central processing unit (CPU) 901, a read-only memory (ROM) 902, and a random access memory (RAM) 903. Furthermore, the smartphone 900 also includes a storage device 904, a communication module 905, and a sensor module 907. Additionally, the smartphone 900 includes a camera device 909, a display device 910, a speaker 911, a microphone 912, an input device 913, and a bus 914. Moreover, the smartphone 900 may include processing circuitry such as a digital signal processor (DSP) to replace the CPU 901 or as a supplement to the CPU 901.

[0194] The CPU 901 functions as a processing and control device, controlling all or part of the operation of the smartphone 900 according to various programs recorded in the ROM 902, RAM 903, and storage device 904. The ROM 902 stores programs used by the CPU 901, processing parameters, etc. The RAM 903 stores, once and for all, the programs used during the execution of the CPU 901, and parameters that change appropriately during that execution. The CPU 901, ROM 902, and RAM 903 are interconnected via a bus 914. Furthermore, the storage device 904 is a device for data storage, configured as an example of the storage unit of the smartphone 900. The storage device 904 includes, for example, magnetic storage devices such as hard disk drives (HDDs), semiconductor storage devices, optical storage devices, etc. The storage device 904 stores programs executed by the CPU 901, various data, and various data acquired from external sources.

[0195] The communication module 905 is a communication interface comprised of communication devices, such as those used to connect to the communication network 906. The communication module 905 can be, for example, a communication card for wired or wireless local area networks (LANs), Bluetooth (registered trademark), or Wireless USB (WUSB). Furthermore, the communication module 905 can be a router for optical communication, a router for asymmetric digital subscriber line (ADSL), or a modem for various communications. The communication module 905 uses predetermined protocols such as Transmission Control Protocol (TCP) / Internet Protocol (IP) to send and receive signals with the Internet and other communication devices. Furthermore, the communication network 906 connected to the communication module 905 is a network connected in a wired or wireless manner, and is, for example, the Internet, a home LAN, infrared communication, or satellite communication.

[0196] The sensor module 907 includes various sensors, such as motion sensors (e.g., accelerometers, gyroscopes, geomagnetic sensors, etc.), bio-information sensors (e.g., pulse sensors, blood pressure sensors, fingerprint sensors, etc.), or position sensors (e.g., Global Navigation Satellite System (GNSS) receivers, etc.).

[0197] A camera device 909 is disposed on the surface of a smartphone 900 and can capture images of target objects located on the back or front of the smartphone 900. Specifically, the camera device 909 may include: a camera element (not shown), such as a complementary MOS (CMOS) image sensor that can be applied according to the technology of the present invention (the present technology); and a signal processing circuit (not shown) that performs imaging signal processing on the signal obtained by photoelectric conversion of the camera element. Furthermore, the camera device 909 may also include an optical system mechanism (not shown) and a drive system mechanism (not shown). The optical system mechanism includes an imaging lens, a zoom lens, a focusing lens, etc., and the drive system mechanism controls the operation of the optical system mechanism. Moreover, the camera element converges incident light from the target object into an optical image, and the signal processing circuit performs photoelectric conversion on the imaged optical image pixel by pixel, reads signals corresponding to each pixel as imaging signals, and performs image processing to acquire the captured image.

[0198] The display device 910 is disposed on the surface of the smartphone 900, and may be a display device such as a liquid crystal display (LCD) or an organic electroluminescent display (EL). The display device 910 may display an operation screen, images captured by the camera device 909, etc.

[0199] The speaker 911 can output to the user, for example, voice messages for calls or voice messages associated with the video content displayed on the display device 910.

[0200] The microphone 912 can collect, for example, the user's voice during a call, including voice commands for activating functions of the smartphone 900, as well as voice from the environment surrounding the smartphone 900.

[0201] Input device 913 is a user-operated device, such as a button, keyboard, touch panel, or mouse. Input device 913 includes input control circuitry that generates input signals based on user input and outputs these signals to CPU 901. By operating input device 913, the user can input various data into smartphone 900 and provide instructions for processing operations.

[0202] The above has illustrated a structural example of the smartphone 900. Each of the aforementioned components can be configured using general-purpose components, or it can be configured using hardware specifically designed for the functions of each component. This configuration can be appropriately modified depending on the technological level available at the time of implementation.

[0203] <8.3 Examples of Application of Moving Bodies> For example, the technology according to the invention can be implemented as a device mounted on any type of mobile body, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal motor vehicles, airplanes, drones, ships, and robots.

[0204] Figure 47 This is a block diagram illustrating an example of a schematic construction of a vehicle control system, which serves as an example of a mobile body control system to which the technology according to the present invention can be applied.

[0205] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 47 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as part of the functional configuration of the comprehensive control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0206] The drive system control unit 12010 controls the operation of equipment related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for devices such as: a drive force generating device for generating vehicle driving force, such as an internal combustion engine or drive motor; a drive force transmission mechanism for transmitting driving force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating vehicle braking force.

[0207] The body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for devices such as: keyless entry system; smart key system; power windows; or various lights such as headlights, reversing lights, brake lights, turn signals, fog lights, etc. In this case, radio waves transmitted from a portable device that replaces the key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0208] The exterior information detection unit 12030 detects external information about the vehicle equipped with the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to the camera unit 12031. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform processing for detecting objects such as people, vehicles, obstacles, signs, and text on the road surface, or it can perform processing for detecting the distance of the object.

[0209] The camera unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image, or it can output the electrical signal as ranging information. Furthermore, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0210] The in-vehicle information detection unit 12040 detects internal information about the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. For example, the driver state detection unit 12041 includes a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's level of concentration, or determine whether the driver is dozing off.

[0211] The microcomputer 12051 can calculate control target values ​​for the drive force generating device, steering mechanism, or braking device based on information obtained from the external vehicle information detection unit 12030 or the internal vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation, following distance-based driving, speed maintenance driving, collision warning, lane departure warning, etc.

[0212] Furthermore, the microcomputer 12051 can control the drive force generating device, steering mechanism, braking device, etc., based on the external or internal information of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, to perform cooperative control for autonomous driving, which enables the vehicle to drive automatically without relying on the driver's operation.

[0213] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control aimed at preventing glare by controlling the headlights to switch from high beams to low beams, based on the position of the vehicle ahead or oncoming vehicle detected by the exterior information detection unit 12030.

[0214] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or audibly notifying vehicle passengers or the outside of the vehicle. Figure 21 In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0215] Figure 48 This is a diagram showing an example of the mounting position of the camera unit 12031.

[0216] exist Figure 48 In the vehicle 12100, camera units 12101, 12102, 12103, 12104 and 12105 are used as camera unit 12031.

[0217] Cameras 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, and trunk lid of vehicle 12100, as well as on the upper part of the windshield inside the passenger compartment. Camera 12101 on the front nose and camera 12105 on the upper part of the windshield inside the passenger compartment primarily acquire images of the front of vehicle 12100. Cameras 12102 and 12103 on the side mirrors primarily acquire images of the sides of vehicle 12100. Camera 12104 on the rear bumper or trunk lid primarily acquires images of the rear of vehicle 12100. The front images acquired by cameras 12101 and 12105 are mainly used to detect vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0218] Incidentally, Figure 48Examples of the shooting ranges of camera units 12101 to 12104 are shown. Camera range 12111 represents the shooting range of camera unit 12101 located on the front nose. Camera ranges 12112 and 12113 represent the shooting ranges of camera units 12102 and 12103 located on the side mirrors, respectively. Camera range 12114 represents the shooting range of camera unit 12104 located on the rear bumper or trunk lid. For example, by superimposing the image data captured by camera units 12101 to 12104, a bird's-eye view of the vehicle 12100 viewed from above can be obtained.

[0219] At least one of the camera units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera composed of multiple camera elements, or may be a camera element having pixels for phase difference detection.

[0220] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the camera range 12111 to 12114 and the change of that distance over time (relative speed to the vehicle 12100) based on distance information obtained from camera units 12101 to 12104. This allows it to extract the nearest three-dimensional object as the one in front of the vehicle, particularly the nearest three-dimensional object existing on the vehicle 12100's travel path and traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in substantially the same direction as the vehicle 12100. Furthermore, the microcomputer 12051 can pre-set a following distance that must be pre-ensuring for the vehicle ahead and execute automatic braking control (including stop-and-go control), automatic acceleration control (including start-and-go control), etc. Therefore, cooperative control for autonomous driving can be executed, enabling the vehicle to drive automatically without relying on driver operation.

[0221] For example, the microcomputer 12051 can classify three-dimensional object data based on distance information obtained from cameras 12101 to 12104 into three-dimensional object data for two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects. It then extracts the classified three-dimensional object data and uses the extracted data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually perceive and obstacles that the driver of vehicle 12100 cannot visually perceive. Furthermore, the microcomputer 12051 determines the collision risk, which represents the degree of danger of colliding with each obstacle. If the collision risk is equal to or higher than a set value and therefore a collision is possible, the microcomputer 12051 outputs a warning to the driver via an audio speaker 12061 or a display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. Therefore, the microcomputer 12051 can provide driving assistance for collision avoidance.

[0222] At least one of the camera units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the camera units 12101 to 12104. For example, this identification of a pedestrian is performed by: extracting feature points from the images captured by the camera units 12101 to 12104, which are infrared cameras; and performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the camera units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display a square outline for emphasis overlaid on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 to display an icon or the like representing a pedestrian at a desired location.

[0223] Examples of vehicle control systems to which the technology according to the present invention can be applied have been described above. The technology according to the present invention can be applied, for example, to the camera unit 12031 in the above-described configuration.

[0224] [9. Supplement] Although preferred embodiments of the invention have been described in detail above with reference to the accompanying drawings, the scope of the invention is not limited to these examples. It is obvious that those skilled in the art will conceive of various combinations of variations or modifications within the scope of the technical concept set forth in the claims, and it is naturally understood that these variations or modifications also fall within the scope of the invention.

[0225] Furthermore, the effects described in this specification are illustrative or exemplary only, and not limiting. That is, in conjunction with or instead of the effects described above, the technology according to the present invention can exhibit other effects that are obvious to those skilled in the art from the description in this specification.

[0226] Note that this technology can also have the following technical solutions. (1) An imaging element that performs photoelectric conversion on incident light and generates an electric charge. The camera element includes: Component separation wall, which divides the component area of ​​the semiconductor substrate where the camera element is arranged; Multiple pixels are arranged adjacent to each other within the element region surrounded by the element separation wall, and each pixel contains a first conductivity type impurity; Pixel separation walls are configured to extend along the depth direction of the semiconductor substrate and space the plurality of pixels apart from each other; and An on-chip lens is disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels. The pixel separation wall has a slit extending along the depth direction of the semiconductor substrate. The width of the slit is set to: In the depth direction of the semiconductor substrate, It has its maximum width at the depth located between the light-receiving surface and the front surface of the semiconductor substrate opposite to the light-receiving surface; and It has a minimum width at the depth of the light-receiving surface or the front surface. A diffusion region is provided within the slit, the diffusion region containing impurities of a second conductivity type having a conductivity type opposite to the first conductivity type, and The diffusion region has a first overflow path at the location where the slit has the maximum width, and the first overflow path contains the first conductive impurity. (2) According to the imaging element described in (1), wherein, The width of the slit is set to: It gradually narrows from the position of maximum width toward the light-receiving surface, and It gradually narrows from the position of maximum width toward the front. (3) The imaging element according to (1) or (2), wherein, The diffusion region also includes one or more second overflow paths at locations other than where the slit has the maximum width, the second overflow paths containing the first conductive impurity. (4) The imaging element according to any one of (1) to (3), wherein, The pixel separation wall includes a first wall portion and a second wall portion facing each other across the slit, and The surfaces of the first wall portion facing the second wall portion and the surfaces of the second wall portion facing the first wall portion are linearly symmetrical about the central axis of the slit. (5) The imaging element according to any one of (1) to (3), wherein, The pixel separation wall includes a first wall portion and a second wall portion facing each other across the slit, and The surfaces of the first wall portion facing the second wall portion and the surfaces of the second wall portion facing the first wall portion are not linearly symmetrical about the central axis of the slit. (6) The imaging element according to (4) or (5), wherein, The surface of the first wall portion facing the second wall portion, or the surface of the second wall portion facing the first wall portion, has an inclined surface that intersects the vertical line of the front face at an incline. (7) The imaging element according to (4) or (5), wherein, The surface of the first wall portion facing the second wall portion, or the surface of the second wall portion facing the first wall portion, has a step. (8) The imaging element according to (5), wherein, The surface of the first wall portion facing the second wall portion, or the surface of the second wall portion facing the first wall portion, is perpendicular to the front side. (9) An imaging element that performs photoelectric conversion on incident light and generates an electric charge. The camera element includes: Component separation wall, which divides the component area of ​​the semiconductor substrate where the camera element is arranged; Multiple pixels are arranged adjacent to each other within the element region surrounded by the element separation wall, and each pixel contains a first conductivity type impurity; Pixel separation walls are configured to extend along the depth direction of the semiconductor substrate and separate the plurality of pixels from each other; An on-chip lens, which is disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels; and Multiple charge storage portions are provided on the front side of the semiconductor substrate opposite to the light-receiving surface, corresponding to each pixel, and each charge storage portion contains the first type of conductivity impurity. The pixel separation wall has a slit extending along the depth direction of the semiconductor substrate. A diffusion region is provided within the slit, the diffusion region containing impurities of a second conductivity type having a conductivity type opposite to the first conductivity type, and When viewed from above the front The charge accumulation section is separated from the diffusion region by a diffusion region separation wall, which is configured to extend from the front side in the depth direction of the semiconductor substrate. (10) The imaging element according to (9), wherein, The diffusion region separation wall extends deeper in the depth direction of the semiconductor substrate than the charge accumulation portion. (11) The imaging element according to (9) or (10) further includes A transfer gate, disposed adjacent to the charge accumulation portion on the front side, transfers the charge generated in the pixel to the charge accumulation portion. The transmission gate includes a vertical gate portion extending from the front side along the depth direction of the semiconductor substrate. (12) The imaging element according to (11), wherein, When viewed from above the front The transmission gate is separated from the diffusion region by the diffusion region separation wall. (13) The imaging element according to (11), wherein, When viewed from above the front The transmission gate is not separated from the diffusion region by the diffusion region separation wall. (14) The imaging element according to any one of (11) to (13), wherein, When viewed from above the front The transmission gate has a generally triangular shape. (15) The imaging element according to any one of (9) to (14), wherein, The diffusion region separation wall has an extension that extends from the front side into a portion of the slit, and The extended portion and the diffused region overlap each other in the depth direction of the semiconductor substrate. (16) An imaging element that performs photoelectric conversion on incident light and generates an electric charge. The camera element includes: Component separation wall, which divides the component area of ​​the semiconductor substrate where the camera element is arranged; Multiple pixels are arranged adjacent to each other within the element region surrounded by the element separation wall, and each pixel contains a first conductivity type impurity; Pixel separation walls are configured to extend along the depth direction of the semiconductor substrate and separate the plurality of pixels from each other; An on-chip lens is disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels; A plurality of charge storage portions are provided on the front side of the semiconductor substrate opposite to the light-receiving surface, corresponding to each pixel, and each charge storage portion contains the first conductivity type impurity; and A transfer gate is disposed on the front side in such a manner that it surrounds the charge accumulation portion. And the charge generated in the pixel is transferred to the charge storage unit. The pixel separation wall has a slit extending along the depth direction of the semiconductor substrate. A diffusion region is provided within the slit, the diffusion region containing impurities of a second conductivity type having a conductivity type opposite to the first conductivity type, and When viewed from above the front The charge storage section is located at the center of the imaging element. (17) The imaging element according to (16), wherein, The transmission gate includes one or more vertical gate portions that extend from the front side along the depth direction of the semiconductor substrate. (18) The imaging element according to (17), wherein, The vertical gate portion is in contact with the charge storage portion. (19) The imaging element according to any one of (16) to (18), wherein, The pixel separation wall includes a plurality of the slits. (20) The imaging element according to any one of (16) to (19), wherein, The diffusion region has an overflow path containing the first type of conductivity impurity, and The charge accumulation section does not overlap with the overflow path. (21) The imaging element according to any one of (16) to (18), wherein, The charge storage section is configured such that: It is disposed on the front side within the slit, and The depth direction of the semiconductor substrate overlaps with the overflow path containing the first type of conductive impurity. (22) An imaging element that performs photoelectric conversion on incident light and generates an electric charge. The camera element includes: Component separation wall, which divides the component area of ​​the semiconductor substrate where the camera element is arranged; Multiple pixels are arranged adjacent to each other within the element region surrounded by the element separation wall, and each pixel contains a first conductivity type impurity; Pixel separation walls are configured to extend along the depth direction of the semiconductor substrate and separate the plurality of pixels from each other; An on-chip lens is disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels; Multiple charge storage portions are provided at the corner of each pixel on the front side of the semiconductor substrate opposite to the light-receiving surface, and each charge storage portion contains the first conductive impurity. Multiple grounding portions, each of which is disposed on the front side at a corner of each pixel on the side opposite to the charge accumulation portion; and A transmission gate is disposed at the center of each of the pixels on the front side, and The charge generated in the pixel is transferred to the charge storage unit. The pixel separation wall has a slit extending along the depth direction of the semiconductor substrate. A first diffusion region is provided within the slit, the first diffusion region containing impurities having a second conductivity type opposite to the first conductivity type, and When viewed from above the front A second diffusion region containing the second type of conductive impurity is provided on the grounding side. (23) The imaging element according to (22), wherein, When viewed from above the front The charge storage section and the grounding section are in a point-symmetrical position with the transmission gate as the center. (24) The imaging element according to (22) or (23), wherein, When viewed from above the front The slit is located on the grounding side, and The second diffusion region is provided along a portion of the element separation wall located on the grounding side. (25) The imaging element according to (22) or (23), wherein, The pixel separation wall includes a first wall portion and a second wall portion that face each other across the slit. When viewed from above the front The slit is located at the center of the camera element. The first wall portion is located on the side of the charge storage portion. The second wall portion is located on the grounding portion side. The second diffusion region is disposed along the second wall portion. (26) The imaging element according to any one of (22) to (25), wherein, The first diffusion region is positioned to extend from the front side along the depth direction of the semiconductor substrate to a location deeper than the second diffusion region. (27) The imaging element according to (25) or (26) further includes: The third diffusion region contains the second type of conductive impurity. When viewed from above the front, the third diffusion region is positioned along a portion of the element separation wall located on the grounding side. (28) A camera device, comprising: Semiconductor substrates; and Multiple camera elements are arranged in a matrix along the row and column directions on the semiconductor substrate. Each camera element performs photoelectric conversion on incident light and generates electrical charge. Each of the aforementioned camera elements includes: Component separation wall, which divides the component area of ​​the semiconductor substrate in which the imaging element is arranged; Multiple pixels are arranged adjacent to each other within the element region surrounded by the element separation wall, and each pixel contains a first conductivity type impurity; Pixel separation walls are configured to extend along the depth direction of the semiconductor substrate and space the plurality of pixels apart from each other; and An on-chip lens is disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels. The pixel separation wall has a slit extending along the depth direction of the semiconductor substrate. The width of the slit is set to: In the depth direction of the semiconductor substrate, It has its maximum width at the depth located between the light-receiving surface and the front surface of the semiconductor substrate opposite to the light-receiving surface; and It has a minimum width at the depth of the light-receiving surface or the front surface. A diffusion region is provided within the slit, the diffusion region containing impurities of a second conductivity type having a conductivity type opposite to the first conductivity type, and The diffusion region has a first overflow path at the location where the slit has the maximum width, and the first overflow path contains the first conductive impurity. (29) A camera device, comprising: Semiconductor substrates; and Multiple camera elements are arranged in a matrix along the row and column directions on the semiconductor substrate. Each camera element performs photoelectric conversion on incident light and generates electrical charge. Each of the aforementioned camera elements includes: Component separation wall, which divides the component area of ​​the semiconductor substrate in which the imaging element is arranged; Multiple pixels are arranged adjacent to each other within the element region surrounded by the element separation wall, and each pixel contains a first conductivity type impurity; Pixel separation walls are configured to extend along the depth direction of the semiconductor substrate and separate the plurality of pixels from each other; An on-chip lens, which is disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels; and Multiple charge storage portions are provided on the front side of the semiconductor substrate opposite to the light-receiving surface, corresponding to each pixel, and each charge storage portion contains the first type of conductivity impurity. The pixel separation wall has a slit extending along the depth direction of the semiconductor substrate. A diffusion region is provided within the slit, the diffusion region containing impurities of a second conductivity type having a conductivity type opposite to the first conductivity type, and When viewed from above the front The charge accumulation section is separated from the diffusion region by a diffusion region separation wall, which is configured to extend from the front side in the depth direction of the semiconductor substrate. (30) A camera device, comprising: Semiconductor substrates; and Multiple camera elements are arranged in a matrix along the row and column directions on the semiconductor substrate. Each camera element performs photoelectric conversion on incident light and generates electrical charge. Each of the aforementioned camera elements includes: Component separation wall, which divides the component area of ​​the semiconductor substrate in which the imaging element is arranged; Multiple pixels are arranged adjacent to each other within the element region surrounded by the element separation wall, and each pixel contains a first conductivity type impurity; Pixel separation walls are configured to extend along the depth direction of the semiconductor substrate and separate the plurality of pixels from each other; An on-chip lens is disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels; A plurality of charge storage portions are provided on the front side of the semiconductor substrate opposite to the light-receiving surface, corresponding to each pixel, and each charge storage portion contains the first conductivity type impurity; and A transfer gate is disposed on the front side in such a manner that it surrounds the charge accumulation portion. And the charge generated in the pixel is transferred to the charge storage unit. The pixel separation wall has a slit extending along the depth direction of the semiconductor substrate. A diffusion region is provided within the slit, the diffusion region containing impurities of a second conductivity type having a conductivity type opposite to the first conductivity type, and When viewed from above the front The charge storage section is located at the center of the imaging element. (31) A camera device, comprising: Semiconductor substrates; and Multiple camera elements are arranged in a matrix along the row and column directions on the semiconductor substrate. Each camera element performs photoelectric conversion on incident light and generates electrical charge. Each of the aforementioned camera elements includes: Component separation wall, which divides the component area of ​​the semiconductor substrate in which the imaging element is arranged; Multiple pixels are arranged adjacent to each other within the element region surrounded by the element separation wall, and each pixel contains a first conductivity type impurity; Pixel separation walls are configured to extend along the depth direction of the semiconductor substrate and separate the plurality of pixels from each other; An on-chip lens is disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels; Multiple charge storage portions are provided at the corner of each pixel on the front side of the semiconductor substrate opposite to the light-receiving surface, and each charge storage portion contains the first conductive impurity. Multiple grounding contact portions, each of which is disposed on the front side at a corner of each pixel on the side opposite to the charge accumulation portion; and A transmission gate is disposed at the center of each of the pixels on the front side, and The charge generated in the pixel is transferred to the charge storage unit. The pixel separation wall has a slit extending along the depth direction of the semiconductor substrate. A first diffusion region is provided within the slit, the first diffusion region containing impurities having a second conductivity type opposite to the first conductivity type, and When viewed from above the front A second diffusion region containing the second type of conductive impurity is provided on the grounding contact side. List of reference numerals

[0227] 1, 702, 909: Camera devices 10: Semiconductor substrate 10a: Light-receiving surface 10b: Front 30: Pixel array section 32: Vertical drive circuit section 34: Signal Processing Circuit Section 36; Horizontal drive circuit section 38: Output Circuit Section 40: Control Circuit Section 42: Pixel driver wiring 44: Vertical signal line 46: Horizontal signal line 48: Input / Output Terminals 100, 100a: Camera element 200: On-chip lens 202: Color Filter 204: Shading part 300, 300a, 300b: pixels 302: Photoelectric Conversion Unit 304: Pixel Separation Wall 304a, 304b: Wall portion 306, 306a, 306b, 306c, 306d, 306e, 306f, 306g, 306h, 306j, 306k, 320, 322, 326, 509: Diffusion regions 310: Component separation wall 312: Slit 314: Overflow path 324: Backside DTI (Deep Trench Isolation) 330: STI (Shallow Trench Isolation) 330a: Extension Section 340: Wiring 390: Contact pad 400, 400a, 400b: Transfer gates 400c: Vertical gate portion 501, 503: Silicon nitride films 502, 508: TEOS-based oxide films 504: membrane 506, 511: Polycrystalline silicon film 507, 510: Silicon oxide films 512: Mask 513: Insulating film 601, 601a, 601b: Charge storage section 602: GND (Ground) 620a, 620b: Contact parts 650: Pixel center of gravity 700: Camera 710: Optical Lens 712: Shutter mechanism 714: Drive Circuit Section 716: Signal Processing Circuits Section 900: Smartphone 901: CPU (Central Processing Unit) 902: ROM (Read-Only Memory) 903: RAM (Random Access Memory) 904: Storage device 905: Communication Module 906: Communication Network 907: Sensor Module 910: Display device 911: Speaker 912: Microphone 913: Input device 914: Bus

Claims

1. An imaging element that performs photoelectric conversion on incident light and generates electrical charge. The camera element includes: Component separation wall, which divides the component area of ​​the semiconductor substrate where the camera element is arranged; Multiple pixels are arranged adjacent to each other within the element region surrounded by the element separation wall, and each pixel contains a first conductivity type impurity; Pixel separation walls are configured to extend along the depth direction of the semiconductor substrate and separate the plurality of pixels from each other; and An on-chip lens is disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels. The pixel separation wall has a slit extending along the depth direction of the semiconductor substrate. The width of the slit is set to: In the depth direction of the semiconductor substrate, It has the maximum width at the depth between the light-receiving surface and the front side of the semiconductor substrate opposite to the light-receiving surface; and It has a minimum width at the depth of the light-receiving surface or the front surface. A diffusion region is provided within the slit, the diffusion region containing impurities of a second conductivity type having a conductivity type opposite to the first conductivity type, and The diffusion region has a first overflow path at the location where the slit has the maximum width, and the first overflow path contains the first conductive impurity.

2. The imaging element according to claim 1, wherein, The width of the slit is set to: It gradually narrows from the position of maximum width toward the light-receiving surface, and It gradually narrows from the position of maximum width toward the front.

3. The imaging element according to claim 1, wherein, The diffusion region also includes one or more second overflow paths at locations other than where the slit has the maximum width, the second overflow paths containing the first conductive impurity.

4. The imaging element according to claim 1, wherein, The pixel separation wall includes a first wall portion and a second wall portion facing each other across the slit, and The surfaces of the first wall portion facing the second wall portion and the surfaces of the second wall portion facing the first wall portion are linearly symmetrical about the central axis of the slit.

5. The imaging element according to claim 1, wherein, The pixel separation wall includes a first wall portion and a second wall portion facing each other across the slit, and The surfaces of the first wall portion facing the second wall portion and the surfaces of the second wall portion facing the first wall portion are not linearly symmetrical about the central axis of the slit.

6. The imaging element according to claim 4, wherein, The surface of the first wall portion facing the second wall portion, or the surface of the second wall portion facing the first wall portion, has an inclined surface that intersects the vertical line of the front face at an incline.

7. The imaging element according to claim 4, wherein, The surface of the first wall portion facing the second wall portion, or the surface of the second wall portion facing the first wall portion, has a step.

8. The imaging element according to claim 5, wherein, The surface of the first wall portion facing the second wall portion, or the surface of the second wall portion facing the first wall portion, is perpendicular to the front side.

9. An imaging element that performs photoelectric conversion on incident light and generates electrical charge. The camera element includes: Component separation wall, which divides the component area of ​​the semiconductor substrate where the camera element is arranged; Multiple pixels are arranged adjacent to each other within the element region surrounded by the element separation wall, and each pixel contains a first conductivity type impurity; Pixel separation walls are configured to extend along the depth direction of the semiconductor substrate and separate the plurality of pixels from each other; An on-chip lens is disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels; and Multiple charge storage portions are provided on the front side of the semiconductor substrate opposite to the light-receiving surface, corresponding to each pixel, and each charge storage portion contains the first type of conductivity impurity. The pixel separation wall has a slit extending along the depth direction of the semiconductor substrate. A diffusion region is provided within the slit, the diffusion region containing impurities of a second conductivity type having a conductivity type opposite to the first conductivity type, and When viewed from above the front The charge accumulation section is separated from the diffusion region by a diffusion region separation wall, which is configured to extend from the front side in the depth direction of the semiconductor substrate.

10. The imaging element according to claim 9, wherein, The diffusion region separation wall extends deeper in the depth direction of the semiconductor substrate than the charge accumulation portion.

11. The imaging element according to claim 9, further comprising: A transfer gate, disposed adjacent to the charge accumulation portion on the front side, transfers the charge generated in the pixel to the charge accumulation portion. The transmission gate includes a vertical gate portion extending from the front side along the depth direction of the semiconductor substrate.

12. The imaging element according to claim 11, wherein, When viewed from above the front The transmission gate is separated from the diffusion region by the diffusion region separation wall.

13. The imaging element according to claim 11, wherein, When viewed from above the front The transmission gate is not separated from the diffusion region by the diffusion region separation wall.

14. The imaging element according to claim 11, wherein, When viewed from above the front The transmission gate has a generally triangular shape.

15. The imaging element according to claim 9, wherein, The diffusion region separation wall has an extension that extends from the front side into a portion of the slit, and The extended portion and the diffused region overlap each other in the depth direction of the semiconductor substrate.

16. An imaging element that performs photoelectric conversion on incident light and generates electrical charge. The camera element includes: Component separation wall, which divides the component area of ​​the semiconductor substrate where the camera element is arranged; Multiple pixels are arranged adjacent to each other within the element region surrounded by the element separation wall, and each pixel contains a first conductivity type impurity; Pixel separation walls are configured to extend along the depth direction of the semiconductor substrate and separate the plurality of pixels from each other; An on-chip lens is disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels; Multiple charge storage sections are provided on the front side of the semiconductor substrate opposite to the light-receiving surface, corresponding to each pixel, and each charge storage section contains the first conductive impurity. and A transfer gate, disposed on the front side surrounding the charge accumulation portion, transfers the charge generated in the pixel to the charge accumulation portion, wherein the pixel separation wall has a slit extending along the depth direction of the semiconductor substrate. A diffusion region is provided within the slit, the diffusion region containing impurities of a second conductivity type having a conductivity type opposite to the first conductivity type, and When viewed from above the front The charge storage section is located at the center of the imaging element.

17. The imaging element according to claim 16, wherein, The transmission gate includes one or more vertical gate portions that extend from the front side along the depth direction of the semiconductor substrate.

18. The imaging element according to claim 17, wherein, The vertical gate portion is in contact with the charge storage portion.

19. The imaging element according to claim 16, wherein, The pixel separation wall includes a plurality of the slits.

20. The imaging element according to claim 16, wherein, The diffusion region has an overflow path containing the first type of conductivity impurity, and The charge accumulation section does not overlap with the overflow path.

21. The imaging element according to claim 16, wherein, The charge storage section is configured such that: It is disposed on the front side within the slit, and The depth direction of the semiconductor substrate overlaps with the overflow path containing the first type of conductive impurity.

22. A camera device, comprising: Semiconductor substrate; as well as Multiple camera elements are arranged in a matrix along the row and column directions on the semiconductor substrate. Each camera element performs photoelectric conversion on incident light and generates electrical charge. Each of the aforementioned camera elements includes: Component separation wall, which divides the component area of ​​the semiconductor substrate in which the imaging element is arranged; Multiple pixels are arranged adjacent to each other within the element region surrounded by the element separation wall, and each pixel contains a first conductivity type impurity; Pixel separation walls are configured to extend along the depth direction of the semiconductor substrate and space the plurality of pixels apart from each other; and An on-chip lens is disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels. The pixel separation wall has a slit extending along the depth direction of the semiconductor substrate, and the width of the slit is set as follows: In the depth direction of the semiconductor substrate, It has its maximum width at the depth located between the light-receiving surface and the front surface of the semiconductor substrate opposite to the light-receiving surface; and It has a minimum width at the depth of the light-receiving surface or the front surface. A diffusion region is provided within the slit, the diffusion region containing impurities of a second conductivity type having a conductivity type opposite to the first conductivity type, and The diffusion region has a first overflow path at the location where the slit has the maximum width, and the first overflow path contains the first conductive impurity.

23. A camera device, comprising: Semiconductor substrate; as well as Multiple camera elements are arranged in a matrix along the row and column directions on the semiconductor substrate. Each camera element performs photoelectric conversion on incident light and generates electrical charge. Each of the aforementioned camera elements includes: Component separation wall, which divides the component area of ​​the semiconductor substrate in which the imaging element is arranged; Multiple pixels are arranged adjacent to each other within the element region surrounded by the element separation wall, and each pixel contains a first conductivity type impurity; Pixel separation walls are configured to extend along the depth direction of the semiconductor substrate and separate the plurality of pixels from each other; An on-chip lens, which is disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels; and Multiple charge storage portions are provided on the front side of the semiconductor substrate opposite to the light-receiving surface, corresponding to each pixel, and each charge storage portion contains the first type of conductivity impurity. The pixel separation wall has a slit extending along the depth direction of the semiconductor substrate, and a diffusion region is provided within the slit. The diffusion region contains impurities having a second conductivity type having a conductivity type opposite to the first conductivity type. When viewed from above the front The charge accumulation section is separated from the diffusion region by a diffusion region separation wall, which is configured to extend from the front side in the depth direction of the semiconductor substrate.

24. A camera device, comprising: Semiconductor substrate; as well as Multiple camera elements are arranged in a matrix along the row and column directions on the semiconductor substrate. Each camera element performs photoelectric conversion on incident light and generates electrical charge. Each of the aforementioned camera elements includes: Component separation wall, which divides the component area of ​​the semiconductor substrate in which the imaging element is arranged; Multiple pixels are arranged adjacent to each other within the element region surrounded by the element separation wall, and each pixel contains a first conductivity type impurity; Pixel separation walls are configured to extend along the depth direction of the semiconductor substrate and separate the plurality of pixels from each other; An on-chip lens is disposed above the light-receiving surface of the semiconductor substrate in a manner shared by the plurality of pixels; A plurality of charge storage portions are provided on the front side of the semiconductor substrate opposite to the light-receiving surface, corresponding to each pixel, and each charge storage portion contains the first conductivity type impurity; and A transfer gate, disposed on the front side surrounding the charge accumulation portion, transfers the charge generated in the pixel to the charge accumulation portion. The pixel separation wall has a slit extending along the depth direction of the semiconductor substrate, and a diffusion region is disposed within the slit. The diffusion region contains impurities of a second conductivity type having a conductivity type opposite to the first conductivity type. When viewed from above the front The charge storage section is located at the center of the imaging element.

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