Water pump state detection circuit

Abstract

The invention discloses a water pump state detection circuit which comprises a control circuit, a gating circuit and a reset circuit, the control circuit is connected with the gating circuit and the reset circuit, and the gating circuit is used for relieving or limiting the parameter set establishment authority of the control circuit when a parameter set is initially established and after the parameter set is established. The control circuit is used for enabling the water pump to automatically operate at each working condition point in the parameter set establishment period, and the reset circuit is used for resetting the control module after the parameter set of the water pump is established. According to the method, the operation parameters of the water pump under different working condition points can be collected, the parameter set is established based on the operation parameters, the performance attenuation degree of the water pump is quantified more visually by combining the accumulated operation time of the water pump and comparing the operation parameters collected in real time with the parameter set, early recognition and early warning of the aging state of the water pump are achieved, and the working efficiency is improved. And the possibility of predictive maintenance is provided.

Description

Technical Field

[0001] This invention relates to the field of water pump testing technology, and in particular to a water pump status detection circuit. Background Technology

[0002] Current pump condition monitoring circuits typically only monitor pump conditions related to safe operation, such as no-load, stall, or overload. They struggle to capture the gradual performance changes caused by internal mechanical wear during long-term operation. This performance degradation is often gradual and does not manifest as a sudden failure in the short term. Therefore, this paper proposes a pump condition monitoring circuit that can collect pump operating parameters at different operating points and establish a parameter set based on these parameters. In practical applications, by combining the pump's cumulative operating time with the real-time collected operating parameters and comparing them with the parameter set, the circuit can more intuitively quantify the degree of performance degradation, enabling early identification and warning of pump aging and providing the possibility of predictive maintenance. Summary of the Invention

[0003] To address the aforementioned technical problems, the present invention aims to provide a water pump status detection circuit, comprising a control circuit, a gating circuit, and a reset circuit. The control circuit, gating circuit, and reset circuit are connected. The gating circuit is used to release or restrict the parameter set establishment permission of the control circuit during the initial establishment of the parameter set and after the parameter set establishment is completed. The control circuit is used to enable the water pump to automatically operate at each operating point during the parameter set establishment period. The reset circuit is used to reset the control module after the water pump parameter set establishment is completed.

[0004] Furthermore, the control circuit includes a first setting unit, a second setting unit, triggers U1, U2, U3, U4, U5, and U6, resistors R1, R2, R3, R4, R5, and R6, and diodes D1, D2, D3, and D4. The control terminal of trigger U1 is connected to one end of resistor R1, the cathode of diode D1, the first setting unit, and the cathode of diode D2. Its input terminal is connected to the inverting output terminal and the input terminal of trigger U2. The set terminal is connected to the power supply. The clear terminal is connected to one end of resistor R2, the clear terminal of trigger U2, and the first setting unit. The other end of resistor R1 is grounded. The other end of resistor R2 is connected to the power supply. The first setting unit is connected to the anode of diode D1 and one end of resistor R3. The output, control, and reset terminals of triggers U2 and U3 are connected; the other end of resistor R3 is grounded; the output terminal of trigger U3 is connected to the anode of diode D2, and the set terminal is connected to the power supply; the control terminal of trigger U4 is connected to one end of resistor R4, the cathode of diode D3, the second setting unit, and the cathode of diode D4; the input terminal is connected to the inverting output terminal and the input terminal of trigger U5; the set terminal is connected to the power supply; the reset terminal is connected to one end of resistor R5, the reset terminal of trigger U5, and the second setting unit; the other end of resistor R4 is grounded; the other end of resistor R5 is connected to the power supply; the second setting unit is connected to the anode of diode D3, one end of resistor R6, the output, control, and reset terminals of triggers U5 and U6; the other end of resistor R6 is grounded; the output terminal of trigger U6 is connected to the anode of diode D4, and the set terminal is connected to the power supply.

[0005] Furthermore, the first setting unit sets the valve opening adjustment step number by setting a number of triggers (numbered triggers Ua1 to triggers Uax). The number of triggers is equal to the number of steps. Triggers Ua1 to triggers Uax are cascaded in sequence, that is, the output terminal of the previous stage is connected to the input terminal of the next stage. The control terminal of all triggers in the first setting unit is connected in parallel to one end of resistor R3, the clear terminal is connected in parallel to one end of resistor R2, the set terminal is connected to the power supply, the input terminal of trigger Ua1 is connected to the output terminal of trigger U2, and the output terminal of trigger Uax is connected to the input terminal of trigger U3.

[0006] Furthermore, the second setting unit sets the adjustment step number of the frequency converter by setting a number of triggers (numbered triggers Uy1 to triggers Uyx). The number of triggers is equal to the number of steps. Triggers Uy1 to triggers Uyx are cascaded in sequence, that is, the output terminal of the previous stage is connected to the input terminal of the next stage. The control terminals of all triggers in the second setting unit are connected in parallel to one end of resistor R6, the clear terminal is connected in parallel to one end of resistor R5, the set terminal is connected to the power supply, the input terminal of trigger Uy1 is connected to the output terminal of trigger U5, and the output terminal of trigger Uyx is connected to the input terminal of trigger U6.

[0007] Furthermore, the gate circuit includes a trigger U7, a transistor Q3, a diode D5, a resistor R7, and a resistor R8. The input terminal of the trigger U7 is connected to the inverting output terminal and the anode of the diode D5, the control terminal is connected to one end of the resistor R8, and the set and clear terminals are connected to the power supply. The base of the transistor Q3 is connected to the cathode of the diode D5 and one end of the resistor R7, and the collector is connected to one end of the resistor R3. The other ends of the resistors R7 and R8 are grounded.

[0008] Furthermore, the reset circuit includes an AND gate U8, a diode D6, a transistor Q1, and a transistor Q2. The cathode of the diode D6 is connected to one end of the resistor R8, and the anode of the diode D6 is connected to the second input terminal of the AND gate U8 and the output terminal of the flip-flop U6. The first input terminal of the AND gate U8 is connected to the output terminal of the flip-flop U3, and the output terminal is connected to the base of the transistors Q1 and Q2. The collector of the transistor Q1 is connected to the reset terminal of the flip-flop U3, and the emitter is grounded. The collector of the transistor Q2 is connected to the reset terminal of the flip-flop U6, and the emitter is grounded.

[0009] Furthermore, it also includes a data acquisition circuit and a comparison circuit. The data acquisition circuit is connected to the gate control circuit and the comparison circuit. The data acquisition circuit is used to acquire and record the operating parameters of the water pump at each operating point during the establishment of the water pump's parameter set, and to feed back the acquisition completion signal through the gate control circuit after the acquisition and recording are completed. The data acquisition circuit is used to feed back the real-time operating parameters of the water pump and the parameters of the corresponding parameter set to the comparison circuit after the parameter set is established.

[0010] Furthermore, the comparison circuit is used to compare the real-time acquired operating parameters with the parameters in the parameter set.

[0011] The advantages of this invention compared to the prior art are: This invention can collect the operating parameters of a water pump under different operating conditions and establish a parameter set based on this. By combining the cumulative operating time of the water pump with the real-time collected operating parameters and comparing them with the parameter set, the degree of performance degradation can be quantified more intuitively, enabling early identification and warning of the aging state of the water pump and providing the possibility of predictive maintenance. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the overall structure of the present invention.

[0014] Figure 2The diagram shows the circuit connections of the control circuit, gate circuit, and reset circuit provided by this invention.

[0015] Figure 3 This is a schematic diagram of the circuit connection of the first setting unit provided by the present invention.

[0016] Figure 4 This is a schematic diagram of the circuit connection of the second setting unit provided by the present invention.

[0017] Figure 5 A schematic diagram of the gate control circuit provided by the present invention.

[0018] Figure 6 A schematic diagram of the reset circuit provided by the present invention. Detailed Implementation

[0019] To make the objectives and advantages of the present invention clearer, the present invention will be specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or more specific embodiments of the present invention and does not strictly limit the scope of protection specifically claimed by the present invention.

[0020] This invention discloses a water pump status detection circuit, including a control circuit, a gating circuit, and a reset circuit. The control circuit, the gating circuit, and the reset circuit are connected. The gating circuit is used to release or restrict the parameter set establishment permission of the control circuit when the parameter set is initially established and after the parameter set is established. The control circuit is used to enable the water pump to automatically run at each operating point during the parameter set establishment. The reset circuit is used to reset the control module after the water pump parameter set is established.

[0021] Specifically, the control circuit includes a first setting unit, a second setting unit, triggers U1, U2, U3, U4, U5, and U6, resistors R1, R2, R3, R4, R5, and R6, and diodes D1, D2, D3, and D4. The control terminal of trigger U1 is connected to one end of resistor R1, the cathode of diode D1, the first setting unit, and the cathode of diode D2. Its input terminal is connected to the inverting output terminal and the input terminal of trigger U2. The set terminal is connected to the power supply. The clear terminal is connected to one end of resistor R2, the clear terminal of trigger U2, and the first setting unit. The other end of resistor R1 is grounded. The other end of resistor R2 is connected to the power supply. The first setting unit is connected to the anode of diode D1 and one end of resistor R3. The output, control, and reset terminals of triggers U2 and U3 are connected; the other end of resistor R3 is grounded; the output terminal of trigger U3 is connected to the anode of diode D2, and the set terminal is connected to the power supply; the control terminal of trigger U4 is connected to one end of resistor R4, the cathode of diode D3, the second setting unit, and the cathode of diode D4; the input terminal is connected to the inverting output terminal and the input terminal of trigger U5; the set terminal is connected to the power supply; the reset terminal is connected to one end of resistor R5, the reset terminal of trigger U5, and the second setting unit; the other end of resistor R4 is grounded; the other end of resistor R5 is connected to the power supply; the second setting unit is connected to the anode of diode D3, one end of resistor R6, the output, control, and reset terminals of triggers U5 and U6; the other end of resistor R6 is grounded; the output terminal of trigger U6 is connected to the anode of diode D4, and the set terminal is connected to the power supply.

[0022] Specifically, the first setting unit sets the adjustment step number of the valve opening by setting a number of triggers (numbered triggers Ua1 to triggers Uax). The number of triggers is equal to the number of steps. Triggers Ua1 to triggers Uax are cascaded in sequence, that is, the output terminal of the previous stage is connected to the input terminal of the next stage. The control terminal of all triggers in the first setting unit is connected in parallel to one end of resistor R3, the clear terminal is connected in parallel to one end of resistor R2, the set terminal is connected to the power supply, the input terminal of trigger Ua1 is connected to the output terminal of trigger U2, and the output terminal of trigger Uax is connected to the input terminal of trigger U3.

[0023] Specifically, the second setting unit sets the adjustment step number of the frequency converter by setting a number of triggers (numbered triggers Uy1 to triggers Uyx). The number of triggers is equal to the number of steps. Triggers Uy1 to triggers Uyx are cascaded in sequence, that is, the output terminal of the previous stage is connected to the input terminal of the next stage. The control terminals of all triggers in the second setting unit are connected in parallel to one end of resistor R6, the clear terminal is connected in parallel to one end of resistor R5, the set terminal is connected to the power supply, the input terminal of trigger Uy1 is connected to the output terminal of trigger U5, and the output terminal of trigger Uyx is connected to the input terminal of trigger U6.

[0024] Specifically, the gate circuit includes a trigger U7, a transistor Q3, a diode D5, a resistor R7, and a resistor R8. The input terminal of the trigger U7 is connected to the inverting output terminal and the anode of the diode D5, the control terminal is connected to one end of the resistor R8, and the set and clear terminals are connected to the power supply. The base of the transistor Q3 is connected to the cathode of the diode D5 and one end of the resistor R7, and the collector is connected to one end of the resistor R3. The other ends of the resistors R7 and R8 are grounded.

[0025] Specifically, the reset circuit includes an AND gate U8, a diode D6, a transistor Q1, and a transistor Q2. The cathode of the diode D6 is connected to one end of the resistor R8, and the anode of the diode D6 is connected to the second input terminal of the AND gate U8 and the output terminal of the flip-flop U6. The first input terminal of the AND gate U8 is connected to the output terminal of the flip-flop U3, and the output terminal is connected to the base of the transistors Q1 and Q2. The collector of the transistor Q1 is connected to the reset terminal of the flip-flop U3, and the emitter is grounded. The collector of the transistor Q2 is connected to the reset terminal of the flip-flop U6, and the emitter is grounded.

[0026] Specifically, it also includes a data acquisition circuit and a comparison circuit. The data acquisition circuit is connected to the gate control circuit and the comparison circuit. The data acquisition circuit is used to acquire and record the operating parameters of the water pump at each operating point during the establishment of the water pump's parameter set, and to feed back the acquisition completion signal through the gate control circuit after the acquisition and recording are completed. The data acquisition circuit is used to feed back the real-time operating parameters of the water pump and the parameters of the corresponding parameter set to the comparison circuit after the parameter set is established.

[0027] Specifically, the comparison circuit is used to compare the real-time acquired operating parameters with the parameters in the parameter set.

[0028] See appendix Figure 2 Appendix Figure 5The flip-flop's R terminal is the clear terminal, S terminal is the set terminal, D terminal is the input terminal, CLK terminal is the control terminal, Q terminal is the output terminal, and / Q terminal is the inverting output terminal. When establishing the parameter set, the acquisition circuit outputs a parameter set establishment signal to the control module. This signal is input to the control terminal of flip-flop U7 via IN1 and is at a high level. Simultaneously, the acquisition circuit acquires and records the pump's operating parameters at the current operating point when the pump is running stably, including pump speed, outlet pressure, flow rate, and operating current. After each acquisition and recording of all parameters at the current operating point, a acquisition completion signal is output to the control module. This acquisition completion signal is input to the emitter of transistor Q3 via IN2. When the circuit is initially powered on, the inverting output of trigger U7 outputs a high level. This signal, through diode D5 and resistor R7, keeps the base of transistor Q3 at a high level to prevent Q3 from conducting. Simultaneously, the inverting output of trigger U1, also initially powered on, outputs a high level, making the input of trigger U2 high. When I... When N1 is input at a high level, the high-level signal is input to the control terminal of flip-flop U7, and the inverting output terminal of flip-flop U7 outputs a low level. When IN2 is input at a high level, the signal passes through the emitter and base of transistor Q3 and resistor R7, turning on transistor Q3. Diode D5 provides reverse protection, and the conduction of transistor Q3 allows the IN2 signal to be fed back to the first control unit and the first setting unit through the gating circuit. Flip-flops U2 and U3, as well as all the flip-flop control terminals in the first setting unit, synchronously receive the high level fed back from IN2 through the gating circuit. When the control terminal of trigger U2 receives a high level feedback from the IN2 terminal, the output terminal of trigger U2 outputs a high level. The high level signal of the output terminal of trigger U2 is input to the control terminal of trigger U1 through diode D1, making the inverting output terminal of trigger U1 and the input terminal of trigger U2 low level. At the same time, the high level signal of the output terminal of trigger U2 is synchronously output to the first setting unit and the outlet valve. When the outlet valve receives the high level signal of the output terminal of trigger U2, it resets its opening degree and opens the valve to the maximum or minimum opening degree according to its own signal characteristics.

[0029] See appendix Figure 2 Appendix Figure 3The first setting unit sets the valve opening adjustment step number by setting several triggers (numbered triggers Ua1 to Uax). The number of triggers is equal to the number of steps. Triggers Ua1 to Uax are cascaded sequentially, meaning the output of the previous stage is connected to the input of the next stage. The control terminals of all triggers in the first setting unit are connected in parallel to one end of resistor R3, the reset terminals are connected in parallel to one end of resistor R2, and the set terminals are connected to the power supply. The input terminal of trigger Ua1 is connected to the output terminal of trigger U2, and the output terminal of trigger Uax is connected to the input terminal of trigger U3. When IN2 receives a high-level signal again through the gating circuit, the output terminal of trigger U2 outputs a low level, and the output terminal of trigger Ua1 outputs a high level. Subsequently, each time IN2 receives a high-level signal through the gating circuit, the output terminals of triggers Ua1 to Uax sequentially shift to output a high level. All trigger output terminals are connected in parallel to a voltage divider network. The voltage is divided by the voltage divider resistors in the voltage divider network and then output to the outlet valve to adjust the valve opening. The voltage divider resistors in the voltage divider network set the step size during stepping. When the high-level signal shifts to the output of trigger Uax and IN2 feeds back a high-level signal again through the gating circuit, the high-level signal at the output of trigger Uax shifts to the output of trigger U3. The high-level signal at the output of trigger U3 is synchronously input to the second control unit. At the same time, the high-level signal at the output of trigger U3 is input to the control terminal of trigger U1 through diode D2. The inverting output of trigger U1 outputs a high level, trigger U1 is reset, and the high-level signal at the inverting output of trigger U1 makes the input of trigger U2 high. When the IN2 terminal feeds back a high-level signal again through the gating circuit, the control terminal of trigger U2 receives the high-level feedback from the IN2 terminal, and the output of trigger U2 outputs a high level. When the outlet valve receives the high-level signal at the output of trigger U2, the opening degree is reset. In this way, during the parameter set establishment period, the opening degree of the outlet valve can be automatically adjusted by increasing or decreasing the set step size and number of steps to complete its step change between fully closed and fully open.

[0030] See appendix Figure 2 Appendix Figure 4 Appendix Figure 6The high-level signal at the output of trigger U3 is synchronously fed back to the first input of AND gate U8. When the circuit is initially powered on, the inverting output of trigger U4 outputs a high level, making the input of trigger U5 high. Triggers U5, U6, and all trigger control terminals in the second setting unit synchronously receive the high-level signal fed back from the first control unit (the output of trigger U3). When the control terminal of trigger U5 receives the high level fed back from the output of trigger U3 of the first control unit, the output of trigger U5 outputs a high level. The high-level signal at the output of trigger U5 is input to the control terminal of trigger U4 through diode D3, making the inverting output of trigger U4 and the input of trigger U5 low. At the same time, the high-level signal at the output of trigger U5 is synchronously output to the second setting unit and the frequency converter. When the frequency converter receives the signal at the output of trigger U5, it performs a frequency reset and adjusts the frequency to the maximum or minimum frequency according to its own signal characteristics.

[0031] See appendix Figure 4 Appendix Figure 5 Appendix Figure 6The second setting unit sets the adjustment step number of the frequency converter by setting several triggers (numbered triggers Uy1 to Uyx). The number of triggers is equal to the number of steps. Triggers Uy1 to Uyx are cascaded sequentially, meaning the output of the previous stage is connected to the input of the next stage. The control terminals of all triggers in the second setting unit are connected in parallel to one end of resistor R6, the reset terminals are connected in parallel to one end of resistor R5, and the set terminals are connected to the power supply. The input terminal of trigger Uy1 is connected to the output terminal of trigger U5, and the output terminal of trigger Uyx is connected to the input terminal of trigger U6. When the first control unit feeds back a high-level signal again, the output terminal of trigger U5 outputs a low level, and the output terminal of trigger Uy1 outputs a high level. Subsequently, each time the first control unit feeds back a high-level signal, the output terminals of triggers Uy1 to Uyx are sequentially shifted to output a high level. All trigger output terminals are connected in parallel to a voltage divider network, and the voltage is divided by the voltage divider resistors in the voltage divider network before being output to the frequency converter. The frequency is adjusted to change the pump speed. The step size is set by adjusting the voltage divider resistor in the voltage divider network. When the high-level signal is shifted to the output of trigger Uyx and the first control unit feeds back a high-level signal, the high-level signal at the output of trigger Uyx is shifted to the output of trigger U6. The high-level signal at the output of trigger U6 is input to the control terminal of trigger U4 through diode D4. The inverting output of trigger U4 outputs a high level, trigger U4 is reset, and the high-level signal at the output of trigger U6 is synchronously fed back to the second input of AND gate U8. The signal at the second input of AND gate U8 is output to the control terminal of trigger U7 through diode D6. The inverting output of trigger U7 outputs a high level to limit the conduction of transistor Q3, trigger U7 is reset. In this way, during the parameter set establishment period, the frequency of the inverter can be automatically adjusted by increasing or decreasing the set step size and step number to change the pump speed. This allows the acquisition circuit to collect the operating parameters of the pump under different operating conditions and establish a parameter set based on this.

[0032] See appendix Figure 2 Appendix Figure 6When the first and second input terminals of AND gate U8 are high, AND gate U8 outputs. The signal from the output terminal of AND gate U8 passes through the base and emitter of transistor Q1 to the ground terminal, turning on transistor Q1. The conduction of transistor Q1 causes the clear terminals of flip-flops U1, U2, U3, and all flip-flops in the first setting unit to be low, resetting the first control unit and the first setting unit. Simultaneously, the signal from the output terminal of AND gate U8 passes through the base and emitter of transistor Q2 to the ground terminal, turning on transistor Q2. The conduction of transistor Q2 causes the clear terminals of flip-flops U4, U5, U6, and all flip-flops in the second setting unit to be low, resetting the second control unit and the second setting unit. After the parameter set of the acquisition circuit is established, the real-time operating parameters of the water pump and the parameters of the corresponding parameter set are fed back to the comparison circuit. The comparison circuit compares the real-time operating parameters with the parameters of the parameter set to obtain a more intuitive understanding of the performance degradation.

[0033] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No markings in the claims should be construed as limiting the scope of the claims.

Claims

1. A water pump status detection circuit, characterized in that, It includes a control circuit, a gating circuit, and a reset circuit, which are connected together. The gating circuit is used to release or restrict the parameter set establishment permission of the control circuit when the parameter set is initially established and after the parameter set is established. The control circuit is used to enable the water pump to automatically run at each operating point during the parameter set establishment. The reset circuit is used to reset the control module after the water pump parameter set is established.

2. The water pump status detection circuit according to claim 1, characterized in that, The control circuit includes a first setting unit, a second setting unit, triggers U1, U2, U3, U4, U5, and U6, resistors R1, R2, R3, R4, R5, and R6, and diodes D1, D2, D3, and D4. The control terminal of trigger U1 is connected to one end of resistor R1, the cathode of diode D1, the first setting unit, and the cathode of diode D2. Its input terminal is connected to the inverting output terminal and the input terminal of trigger U2. The set terminal is connected to the power supply, and the clear terminal is connected to one end of resistor R2, the clear terminal of trigger U2, and the first setting unit. The other end of resistor R1 is grounded. The other end of resistor R2 is connected to the power supply. The first setting unit is connected to the anode of diode D1, one end of resistor R3, and the trigger... The output, control, and reset terminals of triggers U2 and U3 are connected; the other end of resistor R3 is grounded; the output terminal of trigger U3 is connected to the anode of diode D2, and the set terminal is connected to the power supply; the control terminal of trigger U4 is connected to one end of resistor R4, the cathode of diode D3, the second setting unit, and the cathode of diode D4; the input terminal is connected to the inverting output terminal and the input terminal of trigger U5; the set terminal is connected to the power supply; the reset terminal is connected to one end of resistor R5, the reset terminal of trigger U5, and the second setting unit; the other end of resistor R4 is grounded; the other end of resistor R5 is connected to the power supply; the second setting unit is connected to the anode of diode D3, one end of resistor R6, the output, control, and reset terminals of triggers U5 and U6; the other end of resistor R6 is grounded; the output terminal of trigger U6 is connected to the anode of diode D4, and the set terminal is connected to the power supply.

3. The water pump status detection circuit according to claim 2, characterized in that, The first setting unit sets the valve opening adjustment step number by setting a number of triggers (numbered triggers Ua1 to triggers Uax). The number of triggers is equal to the number of steps. Triggers Ua1 to triggers Uax are cascaded in sequence, that is, the output terminal of the previous stage is connected to the input terminal of the next stage. The control terminal of all triggers in the first setting unit is connected in parallel to one end of resistor R3, the clear terminal is connected in parallel to one end of resistor R2, the set terminal is connected to the power supply, the input terminal of trigger Ua1 is connected to the output terminal of trigger U2, and the output terminal of trigger Uax is connected to the input terminal of trigger U3.

4. The water pump status detection circuit according to claim 2, characterized in that, The second setting unit sets the adjustment step number of the frequency converter by setting a number of triggers (numbered triggers Uy1 to triggers Uyx). The number of triggers is equal to the number of steps. Triggers Uy1 to triggers Uyx are cascaded in sequence, that is, the output terminal of the previous stage is connected to the input terminal of the next stage. The control terminals of all triggers in the second setting unit are connected in parallel to one end of resistor R6, the clear terminal is connected in parallel to one end of resistor R5, the set terminal is connected to the power supply, the input terminal of trigger Uy1 is connected to the output terminal of trigger U5, and the output terminal of trigger Uyx is connected to the input terminal of trigger U6.

5. The water pump status detection circuit according to claim 2, characterized in that, The gated circuit includes a trigger U7, a transistor Q3, a diode D5, a resistor R7, and a resistor R8. The input terminal of the trigger U7 is connected to the inverting output terminal and the anode of the diode D5, the control terminal is connected to one end of the resistor R8, and the set and clear terminals are connected to the power supply. The base of the transistor Q3 is connected to the cathode of the diode D5 and one end of the resistor R7, and the collector is connected to one end of the resistor R3. The other ends of the resistors R7 and R8 are grounded.

6. The water pump status detection circuit according to claim 5, characterized in that, The reset circuit includes an AND gate U8, a diode D6, a transistor Q1, and a transistor Q2. The cathode of diode D6 is connected to one end of resistor R8, and the anode of diode D6 is connected to the second input terminal of AND gate U8 and the output terminal of trigger U6. The first input terminal of AND gate U8 is connected to the output terminal of trigger U3, and the output terminal is connected to the base of transistor Q1 and the base of transistor Q2. The collector of transistor Q1 is connected to the reset terminal of trigger U3, and the emitter is grounded. The collector of transistor Q2 is connected to the reset terminal of trigger U6, and the emitter is grounded.

7. The water pump status detection circuit according to claim 5, characterized in that, It also includes a data acquisition circuit and a comparison circuit. The data acquisition circuit is connected to the gate control circuit and the comparison circuit. The data acquisition circuit is used to acquire and record the operating parameters of the water pump at each operating point during the parameter set establishment of the water pump, and to feed back the acquisition completion signal through the gate control circuit after the acquisition and recording are completed. The data acquisition circuit is used to feed back the real-time operating parameters of the water pump and the parameters of the corresponding parameter set to the comparison circuit after the parameter set is established.

8. The water pump status detection circuit according to claim 7, characterized in that, The comparison circuit is used to compare the real-time acquired operating parameters with the parameters in the parameter set.

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