Multi-range calibration for single pin parameter measurement unit

Abstract

The invention relates to multi-range calibration for a single pin parameter measurement unit. A test equipment system may provide a signal to a device under test (DUT), or receive a signal from the device under test (DUT). The test system may include an output stage having an output buffer circuit, which may be controlled locally or externally. An external controller may be used to provide a precision input signal, and in response, to measure current at a DUT interface node of the system, or to measure voltage characteristics of different components within the system. Using the input signal from an external controller, one or more aspects of the test system may be calibrated. For example, a current signal received from an external controller may be used to calibrate the resistance of a sense resistor in the output stage. In another example, a signal from an external controller may be used to determine a buffer offset characteristic to control a local drive circuit of the system.

Description

Background Technology

[0001] Test systems for electronic devices may include pin driver circuitry that provides voltage test pulses to a device under test (DUT). In response, the test system may be configured to measure the response from the DUT, such as determining whether the DUT meets one or more specified operating parameters. The test system may optionally include multiple different types of driver circuitry to provide circuit test signals with different amplitude or timing characteristics. In one example, the test system is configured to use an active load and comparator circuitry to measure the response from the DUT to detect transitions at DUT pins.

[0002] Systems used for testing digital integrated circuits (ICs) may include a single-pin parameter measurement unit (PPMU or PMU). The PMU can be configured to operate in different modes to provide or force current or voltage signals and to receive or measure the corresponding response from the DUT. Operating modes may include, for example, applied voltage-current measurement (FVMI) mode, applied voltage-current measurement (FIMV) mode, applied voltage-current measurement (FIMI) mode, applied voltage-current measurement (FVMV) mode, or unexcited voltage-current measurement (FNMV) mode. The PMU may have various force and sense operating ranges, which can be modified using, for example, external amplifiers or resistors.

[0003] In one example, the test system may include driver circuitry configured to provide multiple voltage levels (e.g., Vhigh, Vlow, and Vterminal) to the DUT. The DUT may exhibit bidirectional (I / O) capability, meaning it can both source and receive stimuli. The Vhigh and Vlow levels of the driver circuitry are used to stimulate the DUT in their "input" state, and the Vterminal is used to terminate the DUT in its "output" state. The switching process between Vhigh, Vlow, and Vterminal can be conceptualized as a set of three switches, each with one terminal connected to Vhigh, Vlow, or Vterminal, and another terminal connected to a 50-ohm resistor, which is then connected to a node on the DUT. Transitions between the three levels can be achieved by turning appropriate switches on and off, such as a switch being off at any given time. The test system may include other functionalities such as active loads and high-speed comparators. Active loads can provide bidirectional current source loads to the DUT, and comparators can act as DUT waveform digitizers. Summary of the Invention

[0004] Furthermore, the inventors recognize that the problem to be solved includes providing a packaged automated test system configured to provide driver, comparator, active load, and single-pin parameter measurement capabilities. The inventors recognize that this problem involves minimizing load effects at the interface with the device under test (DUT) and maximizing the functional test range of the system while using an integrated device structure occupying minimal die area to accommodate, for example, the speed and accuracy requirements of driver, comparator, and active load circuitry. This problem may include providing a relatively small, low-cost system that consumes less power than conventional systems, or providing higher fidelity performance compared to conventional systems.

[0005] The inventors also recognize that the problem may include providing a test system that can be calibrated by the user. For example, automated test systems may be provided as single-channel or multi-channel (dual-channel, quad-channel, eight-channel, etc.) solutions, such as on the same chip. Users typically calibrate each channel using a reference source or reference-driven measurement device. In some examples, users may apply external switches to the DUT pins on each channel. However, such switches can present various problems, including switch size, resistance, load on the DUT pins, and calibration range.

[0006] In one example, solutions to these and other problems may include, or utilize, a drive-sensor system with integrated switches to selectively allow auxiliary control of one or more parts of the drive-sensor system and allow DUT access. The drive-sensor system may include interface nodes for system-level calibration, and these interface nodes may be configured to provide current or voltage information from the DUT to external calibration circuitry. The interface node information may be configured to receive auxiliary current and voltage signals, such as those that can be used to calibrate one or more resistors within the drive-sensor system or to control the output of the drive-sensor system. In one example, the solution may include diode-protected, externally accessible nodes to receive current signals at the DUT interface nodes.

[0007] In one example, furthermore, solutions to the various problems described above may include or utilize a partitioned driver-detection system. The solution may include, for example, a first portion of a driver-detection system implemented using a first integrated circuit, a second portion of a driver-detection system implemented using a different second integrated circuit, and a first interface coupling the first and second portions of the driver-detection system. In one example, the first interface includes a conductive dual-purpose signal path coupling the first and second portions of the driver-detection system. The second portion of the driver-detection system may be coupled to a DUT interface. In one example, one or more switches enabling auxiliary control of the system may be implemented in the first portion of the driver-detection system, such as on the first integrated circuit, and one or more other switches enabling auxiliary control of the system may be implemented in the second portion of the driver-detection system, such as on the second integrated circuit.

[0008] In one example, the solution may also include implementing or constructing different first and second parts of the drive-detection system using different semiconductor substrates or different manufacturing processes. For example, the solution may include using different first and second semiconductor materials for the first and second parts of the drive-detection system. In one example, the first part of the drive-detection system may include a complementary metal-oxide-semiconductor (CMOS) wafer, and the second part of the drive-detection system may include different types of wafers, such as bipolar device-based wafers. In one example, the solution may include PMU circuitry constructed using CMOS and bipolar processes, as well as high-current driver and active load circuitry constructed using different processes, such as bipolar processes. In one example, portions of the PMU circuitry may be distributed across dies, with dies constructed using different processes through interfaces disposed between dies.

[0009] The content of this patent application is intended to provide an overview of the subject matter. It is not intended to provide an exclusive or exhaustive interpretation of the invention. Detailed descriptions are included to provide further information regarding this patent application. Attached Figure Description

[0010] To facilitate identification of any particular element or action being discussed, one or more of the most significant digits in the reference numerals refer to the drawing number in which the element is first introduced.

[0011] Figure 1 An example of a drive-detection test system topology, including multiple driver circuits, is shown in general.

[0012] Figure 2 The diagram shows a schematic example of a test system that includes controller circuitry, bypass circuitry that engages with external calibration circuitry, and output buffer circuitry.

[0013] Figure 3 An example of a partitioned test system with external calibration circuitry is shown in general.

[0014] Figure 4 The present invention provides an example of a first method that may be included as part of a calibration test system.

[0015] Figure 5 The present invention provides an example of a second method that may include determining the resistance of one or more sense resistors or output resistors in the output stage of a drive-detection test system. Detailed Implementation

[0016] Test systems, such as drive-detection test systems used with automated test equipment (ATE), can be configured to provide voltage or current excitation to a device under test (DUT) at specified times and optionally measure the response from the DUT. Test systems can be configured to provide high-fidelity output signal pulses over a relatively large range of output signal amplitudes to accommodate different tests and different types of DUTs.

[0017] In one example, a drive-detection system or drive-detection measurement device may include a pin driver architecture that can provide a high-fidelity excitation signal with minimal overshoot or spikes of a high-frequency current signal and improve pulse edge placement accuracy at high or low power operating levels. The test system may include a single-package ATE solution, which may further include driver circuitry, comparator circuitry, and active load circuitry, as well as a single-pin parameter measurement unit (PPMU or PMU), sometimes referred to herein as a PMU circuit. The driver, comparator, and active load circuitry are also collectively referred to herein as a DCL or DCL circuit. In one example, the PMU circuitry may be configured for high-precision, relatively low-frequency, low-bandwidth, and high-amplitude excitation testing, and the DCL circuitry may be configured for relatively high-frequency and high-bandwidth excitation testing. Control circuitry may be configured to select a specific drive excitation, such as from the PMU circuitry or the DCL circuitry, for a specific test depending on the test parameters or requirements. In some examples, the operation of the PMU circuitry and the DCL circuitry may be mutually exclusive, such that only one of the circuits engages with the DUT at any given time. Various other control circuits can be configured, such as digital-to-analog converters with on-chip calibration registers, enabling them to operate at different DC operating levels.

[0018] In one example, the drive-detection system may include a single-channel or multi-channel system, with each channel capable of individual calibration. The system may include integrated, user-accessible terminals or nodes to receive auxiliary control signals from external systems or user devices. The system may be configured to provide information about the test system itself or about detection from the DUT using the system or portions thereof. Systems with integrated terminals can help reduce adverse loads and improve the test range of calibration signals on conventional test systems (e.g., in terms of signal amplitude or signal bandwidth).

[0019] Figure 1 A first example 100 of a drive-detection test system, including PMU circuitry and DCL circuitry, is generally shown. In the first example 100, the PMU circuitry includes a PMU drive circuitry 110 and a PMU detection circuitry 112 coupled to a DUT pin 128, and the DUT pin 128 may be coupled to a DUT 130. In the first example 100, the DCL circuitry includes a first driver AB 102 that may include class AB driver circuitry and a first driver A 104 that may include class A driver circuitry. The DCL circuitry may include a comparator circuitry 106 and a first load circuitry 114, such as an active load and other load devices. The first example 100 may also include output elements, such as a first resistor 108, which may be configured to provide a specified output or load impedance. In one example, the test system is configured to provide or absorb a first current signal 122, i_test, at the DUT pin 128 coupled to the DUT 130. The drive-detection test system can be configured to simultaneously measure voltage and current on signals received from or supplied to the DUT 130, such as when voltage or current excitation stimulation is applied to the DUT 130.

[0020] In one example, PMU driver circuit 110 can be configured to provide excitation using digitally configurable amplifier circuitry and one or more output buffers. PMU driver circuit 110 can receive digital control signals, such as PMU control signal 134V control, and in response, PMU driver circuit 110 can provide a drive signal at DUT pin 128. PMU detection circuit 112 can be configured to receive voltage or current information from DUT 130, such as using a resistor network. The PMU circuitry may include a feedback network to receive test control signals and voltage or current information from DUT 130, thereby controlling the operation of PMU driver circuit 110. In one example, PMU detection circuit 112 can be configured to, for example, provide PMU output signal 132OP_PMU to an external system controller.

[0021] In one example, the first driver AB 102 can be configured to generate a voltage excitation signal by selecting between parallel diode bridges, where each bridge is driven by a unique, dedicated DC voltage level. Figure 1 In the first example 100, DC voltages Vih 116 and Vil 118 drive a diode bridge in the first driver AB 102. Following the switching stage can be a voltage buffer stage, which can provide power gain, such as being used to generate large currents to serve a 50-ohm DUT environment.

[0022] Compared to the first driver AB 102, the first driver A 104 can be configured to generate transitions at DUT 130 using a relatively high-current switching stage that can be directly coupled to DUT 130. In response to a control signal swing 120, the current switching stage in the first driver A 104 can alternately switch current into / out of DUT 130, such as for a voltage control signal. For example, the first driver A 104 can provide high-speed operation because it may not be burdened by the Class AB voltage buffer stage, which has its associated bandwidth limitations and other performance constraints.

[0023] In one example, the first driver A 104 can be configured to provide a relatively low amplitude signal at DUT 130. For example, the first driver A 104 can provide a signal with a swing of approximately 2 volts. The first driver AB 102 can be configured to provide a relatively high amplitude signal at DUT 130, for example, -1.5 volts to +7 volts. The first driver A 104 typically operates at a higher switching speed or bandwidth compared to the first driver AB 102. In one example, the first driver AB 102 can be configured to absorb switching current from the first driver A 104. That is, the first driver AB 102 can act as a buffer to which the first driver A 104 can provide current, such as through the first resistor 108.

[0024] One or more of the PMU drive circuit 110, the first driver AB 102, and the first driver A 104 can be selected to meet different DUT test requirements that may not be met by a single driver. For example, while each of the driver circuits can provide a DUT signal or waveform, the first driver AB 102 can be configured to provide a large-amplitude, low-bandwidth excitation signal, and the first driver A 104 can be configured to provide a low-amplitude, high-bandwidth excitation signal. For example, the PMU drive circuit 110 can be configured to provide high-amplitude current and voltage signals, such as at DC or low-bandwidth levels.

[0025] In one example, the PMU circuitry and the DCL circuitry include corresponding independent enable control pins. Independent enable control can help facilitate the independent operation of different circuits. For example, depending on the state of the control signal at the enable control pin of the first driver AB 102, the first driver AB 102 can act as a low-speed, high-voltage excitation source, or it can act as a static, non-transient buffer to absorb switching current from the first driver A 104. In one example, when the PMU circuitry is active, both the first driver AB 102 and the first driver A 104 can be disabled, and when either the first driver A 102 or the first driver A 104 is active, the PMU circuitry can be disabled.

[0026] Figure 1 The system includes comparator circuitry 106. Comparator circuitry 106 may include a multi-stage comparator configured to receive signals from DUT 130, such as via DUT pin 128. Comparator circuitry 106 may compare the received signals with comparator reference signal 124 and, in response, provide a differential comparator output signal 126. For example, comparator circuitry 106 may receive a voltage response signal from DUT 130 and compare the amplitude of the voltage response signal with the amplitude of comparator reference signal 124. Comparator circuitry 106 may use differential comparator output signal 126 to provide information about amplitude relationships, such as including digital signals or logic output signals.

[0027] Figure 2 A schematic example of a test system is shown, comprising controller circuitry, bypass circuitry that engages with external calibration circuitry, and output buffer circuitry. For example, Figure 2 The system includes a first drive-detection test system 200, which includes a drive-detection device 202 coupled to an auxiliary control circuit 206 configured as an external calibration circuit. The drive-detection device 202 includes components including a single-pin parameter measurement unit or PMU circuitry and components including a DCL circuit 230, which includes other drivers, comparators, and active load circuitry. The PMU circuitry can be selectively controlled by a local controller or controller circuitry 210, which includes a portion of the drive-detection device 202, or the PMU circuitry can be controlled using the auxiliary control circuitry 206.

[0028] Figure 2 Examples may include or use from Figure 1 Examples include various circuits, components, or functional blocks. For instance, the drive-detection device 202 may include PMU circuitry coupled to the same DUT pin 128 as the DCL circuitry 230, such as... Figure 1Similar to the example described above. The PMU circuit can be configured to support high-precision, low-bandwidth, or DC drive-detection interaction with the DUT 130, and the DCL circuit 230 can be configured to support relatively high-speed drive-detection interaction with the DUT 130. Figure 2 In the example, the DCL circuit 230 and the PMU circuit are coupled at DUT pin 128. The DCL circuit 230 may include a first driver AB 102, a first driver A 104, a first comparator circuit 106, a first load circuit 114, a first resistor 108, or other circuitry or components configured to support relatively high-speed drive-detection interaction with the DUT 130.

[0029] In addition to the circuitry and components including DCL circuitry 230, the circuitry and components in drive-detection device 202 may include PMU drive circuitry 110 and PMU detection circuitry 112. Figure 2 In the example, the PMU circuitry includes controller circuitry 210, bypass circuitry 218, and output buffer circuitry 222. The PMU circuitry can be selectively coupled to auxiliary control circuitry 206 using bypass circuitry 218 or one or more switches elsewhere. Drive-detection device 202 may include a first calibration input node 228, auxiliary control input node 204, auxiliary driver input node 232, and DUT information output node 208 to engage with auxiliary control circuitry 206. Output buffer circuitry 222 may be coupled to DUT pin 128 via an output node, and output buffer circuitry 222 may be coupled to auxiliary control circuitry 206 via first calibration node 228.

[0030] exist Figure 2 In this example, bypass circuit 218 may be coupled to auxiliary control circuit 206 via auxiliary control input node 204 and via DUT information output node 208. Auxiliary control circuit 206 may be configured to receive information from bypass circuit 218 or information about the DUT from the bypass circuit, and auxiliary control circuit 206 may provide auxiliary control over one or more portions of drive-detection device 202, such as control over output buffer circuit 222. In one example, auxiliary control circuit 206 may be configured to drive or load DUT pin 128 directly via first calibration input node 228.

[0031] In one example, controller circuitry 210 may receive a test control signal at test control input node 214 and may receive information from or about the DUT, such as via local DUT information node 212. In response to the DUT information and the test control signal, controller circuitry 210 may provide a signal at drive control output node 224. For example, controller circuitry 210 may provide a drive control signal or a DUT drive signal at drive control output node 224. Control circuitry 210, such as a local controller that can be understood as for PMU circuitry, may provide a drive control signal to buffer control node 226 at output buffer circuitry 222, and in response, may activate one or more output buffers in output buffer circuitry 222 and provide a signal at DUT pin 128. In one example, controller circuitry 210 includes a feedback network configured to receive the test control signal and DUT information from local DUT information node 212. The feedback network may be used to update the characteristics of the drive control signal or drive signal provided by controller circuitry 210.

[0032] In one example, bypass circuit 218 may include circuitry configured to selectively enable auxiliary control of output buffer circuit 222. That is, bypass circuit 218 can select which of several different control signals is provided to output buffer circuit 222 at buffer control node 226. For example, a switching circuit in bypass circuit 218 can activate direct communication between controller circuit 210 and output buffer circuit 222, or the switching circuit can interrupt communication from controller circuit 210, causing output buffer circuit 222 to be in auxiliary control mode. Figure 2 In the example, bypass circuit 218 includes a first switching circuit 216, which can be configured to receive two signals and provide an output buffer circuit 222 with one of the received signals selected from the signals. For example, the first switching circuit 216 can be configured to receive a local control signal from controller circuit 210 via drive control output node 224 and an auxiliary control signal from auxiliary control circuit 206 via auxiliary control input node 204. In one example, the auxiliary control signal includes a voltage signal provided by auxiliary control circuit 206. The first switching circuit 216 can select either the local or auxiliary control signal based on the operating mode of the first drive-detection test system 200. For example, when the PMU circuit is under local control, the first switching circuit 216 can select the local control signal from controller circuit 210. When the PMU circuit is under local control, such as during calibration, the first switching circuit 216 can select the auxiliary control signal from auxiliary control circuit 206.

[0033] The bypass circuit 218 may also include circuitry configured to control the communication of various DUT information to or from the auxiliary control circuitry 206. For example, the bypass circuit 218 may use the DUT information output node 208 to transmit current and / or voltage information received from the DUT regarding signals to an external system or device, or to the auxiliary control circuitry 206. In one example, the bypass circuit 218 may include a second switching circuit 220 configured to receive a corresponding DUT information signal representing or indicating DUT voltage or DUT current. Depending on the operating mode of the first drive-detection test system 200, the second switching circuit 220 may route one or more of the DUT information signals to the controller circuitry 210 or the auxiliary control circuitry 206.

[0034] In one example, one or more additional switching circuits may be disposed in the output buffer circuit 222. One or more additional buffer circuits may be coupled to the auxiliary driver input node 232. In one example, the auxiliary control circuit 206 may be configured to provide an auxiliary current signal to one or more of the switching circuits in the output buffer circuit 222. The auxiliary current signal may include a high-precision current signal generated by the auxiliary control circuit 206 and may be provided to one or more resistors in the output buffer circuit 222. In response to the auxiliary current signal, voltage information can be read from the resistors and used to determine the resistance value of the corresponding resistor with high accuracy.

[0035] The driver-detector 202 may include an integrated circuit, such as one constructed using a specific semiconductor die of a specific semiconductor type. In one example, the driver-detector 202 may include multiple different integrated circuits (ICs), such as those constructed using similar or different dies or processes. That is, different integrated circuits, such as those corresponding to different portions of the driver-detector 202, may include different types of different semiconductors. For example, the front end portion of the PMU circuit may include CMOS-type semiconductors, while other portions of the PMU circuit and / or DCL circuit 230 may include different types of semiconductors. Figure 3 An example is shown that includes a portion of a drive-detection device 202 constructed using different semiconductors.

[0036] Figure 3 The diagram illustrates a schematic example of a test system comprising a first section with a parameter measurement unit and a second section with a driver, comparator, and active load. For example, Figure 3The system includes a multi-die drive-detection test system 300, comprising a drive-detection device 202, a device under test (DUT) 130, and auxiliary control circuitry 206. The drive-detection device 202 includes components including a single-pin parameter measurement unit or PMU circuitry and a DCL circuitry 230, which includes other drivers, comparators, and active load circuitry. The drive-detection device 202 can operate in several different modes, including test modes such as local control mode and auxiliary control mode. The auxiliary control circuitry 206 can be used to operate the drive-detection device 202 in auxiliary control mode. In one example, the auxiliary control mode can be used to calibrate various aspects of the test system and may include a drive calibration mode to calibrate output drive or buffer components in the drive-detection device 202, and a detection calibration mode to calibrate detection circuitry or detection components (e.g., resistors) in the drive-detection device 202.

[0037] Figure 3 The examples illustrate that various aspects of the driver-detection device 202 may include multiple different semiconductor devices connected via an interface. For example, the multi-die driver-detection test system 300 may include a first semiconductor device 304 coupled to a second semiconductor device 308 via a device interface 314. The second semiconductor device 308 may be coupled to the DUT 130. Different portions of the driver-detection device 202 may be constructed using different semiconductor devices of different semiconductor device types, discussed in more detail below.

[0038] Figure 3 Examples may include or use from Figure 1 and / or Figure 2Examples include various circuits, components, or functional blocks. For instance, the drive-detection device 202 may include PMU circuitry coupled to the same DUT pin 128 as the DCL circuit 230, as described above. The drive-detection device 202 may communicate with the auxiliary control circuitry 206 using one or more user-accessible nodes. In one example, the drive-detection device 202 may include a first calibration input node 228 configured to receive calibration test signals from the auxiliary control circuitry 206. The drive-detection device 202 may include a DUT current detection node 378 configured to provide information about the DUT current signal to the auxiliary control circuitry 206, and a DUT voltage detection node 380 configured to provide information about the DUT voltage signal to the auxiliary control circuitry 206. The drive-detection device 202 may include a first auxiliary input node 376 configured to receive auxiliary control signals from the auxiliary control circuitry 206. For example, the auxiliary control signal may include a voltage signal configured to control a buffer circuit in the output stage of the drive-detection device 202. In one example, the drive-detection device 202 may include a second auxiliary input node 382 and / or a third auxiliary input node 384 configured to receive an auxiliary drive signal from the auxiliary control circuit 206. For example, the auxiliary drive signal may include a current signal configured to generate a voltage when a current signal is provided to detect resistance in the output stage of the drive-detection device 202.

[0039] In addition to the circuitry and components including DCL circuitry 230, the circuitry and components in drive-detection device 202 may include PMU drive circuitry 110 and PMU detection circuitry 112 of the PMU in drive-detection device 202. For example, the PMU circuitry may include controller circuitry 210, such as having a digital-to-analog converter circuitry or a first DAC 302 and a first drive amplifier 310 in the front-end portion of the PMU circuitry. The first drive amplifier 310 may be configured to provide a buffer drive signal.

[0040] The PMU circuitry may include a drive control feedback network with switches configured to allow control information to flow from the DUT 130 to the differential input of the first drive amplifier 310. For example, the drive control feedback network may include a sense amplifier output switch 348 configured to selectively couple the output of a sense amplifier circuit 366 to the first drive amplifier 310; an instrumentation amplifier output switch 336 configured to selectively couple the output of an instrumentation amplifier circuit 358 to the first drive amplifier 310; and a feedback switch 330 configured to selectively couple the output of the first drive amplifier 310 to its input. The sense amplifier circuit 366 and the instrumentation amplifier circuit 358 may be configured to receive DUT voltage or DUT current information from the DUT 130, which, in turn, can be used to generate feedback signals for the drive control feedback network.

[0041] In one example, the DUT circuitry includes a DUT sensing section configured to receive or measure signals received from the DUT 130 via DUT pin 128, such as through a DUT sensing resistor 370 and / or using different drive-sensor resistors R1-R6. When the value of the DUT sensing resistor 370 or other drive-sensor resistors is known, information about the current signal from the DUT 130 can be determined based on the voltage across a particular resistor. In one example, an instrumentation amplifier circuit 358 can be used to measure the current signal information. The instrumentation amplifier circuit 358 may include a differential amplifier circuit configured to compare the current signal information from the DUT 130, such as the current signal information received via the DUT sensing resistor 370, with current information at a specific sensing node in the output buffer circuitry of the PMU circuitry.

[0042] In one example, the first DAC 302 may include a test control input node 214 to receive control signals from an external test controller. The signals at the test control input node 214 may be specified by a user or program, such as defining one or more parameters. In response to the signals at the test control input node 214, the first DAC 302 may provide a test control signal 340 to the first drive amplifier 310. The first drive amplifier 310 may receive the test control signal 340 and the DUT information signal 344, and, for example, provide either a DUT drive signal or a buffer control signal for communication to the DUT 130 via bypass circuitry 218 to control one or more buffer circuits in the output buffer circuitry 222.

[0043] In one example, the drive-detection device 202 may include a first selector circuit 322 configured to receive signals from the controller circuit 210. Figure 3 (As shown in the example) and information from the auxiliary control circuit 206. Figure 3 In the example, the first selector circuit 322 can correspond to the circuit from... Figure 2 Example of a first switching circuit 216. A first selector circuit 322 can be used to receive one or more control signals and output node 346 to a first device (e.g., corresponding to signals from...). Figure 2 The first selector circuit 322 can be configured to select one of the control signals from the control signals of the example buffer control node 226, thereby controlling the output signal or DUT drive signal provided by one or more output buffers. For example, in drive calibration mode, the first selector circuit 322 can be configured to transmit a signal from the first auxiliary input node 376 to the second device input node 354 via the first device output node 346 to enable auxiliary control of the buffer on the second semiconductor device 308. That is, in drive calibration mode, the buffers in the output buffer circuit 222 can be under the auxiliary control provided by the auxiliary control circuit 206. In non-calibration mode or test mode, the first selector circuit 322 can be configured to transmit a signal from the local controller, such as the first drive amplifier 310, to the second device input node 354 via the first device input node 346. The first selector circuit 322 may optionally include multiplexer circuitry or various switching devices that work together in coordination, or may include transmission gates or bootstrap switches.

[0044] In one example, a buffer on the second semiconductor device 308, such as one from... Figure 2 The example output buffer circuit 222 can be configured to provide multiple different signal paths between the first selector circuit 322 and the DUT pin 128. Different buffers or buffer instances on the second semiconductor device 308 can be configured to operate mutually exclusively, such that only one of the buffer instances operates at a given time. In other examples, multiple buffer instances can be used together. Figure 3 In the example, the buffer may include a first buffer circuit 306, a second buffer circuit 312, and a third buffer circuit 316, and each of the buffer circuits may be configured to provide a voltage or current signal respectively within different voltage or current amplitude ranges. The corresponding outputs of the different buffer circuits may be coupled to corresponding detection nodes, and in turn, to corresponding portions of the resistive output network. Figure 3In the example, the output of the first buffer circuit 306 can be coupled to the DUT node or DUT 130 via the first sense resistor R1. The output of the second buffer circuit 312 can be coupled to the DUT node or DUT 130 via a combination of the second sense resistor R2 and the first sense resistor R1, and the output of the third buffer circuit 316 can be coupled to the DUT node or DUT 130 via a series combination of the third sense resistor R3, the second sense resistor R2, and the first sense resistor R1. Current amplitude information about the signal provided to the DUT node can be calculated based on the resistance of a resistor network comprising a resistor output network and one or more measured voltage information at sense nodes within the resistor output network. The same sense nodes in the resistor network can be used to read amplitude information about the current signal received from DUT 130.

[0045] In some examples, the impedance or resistance of one or more of the sense resistors or the offset of various buffer circuits may be known, but can be determined using the calibration procedures discussed herein. Figure 3 In the example, the driving circuit and the detection circuit of the drive-detection device 202 can be calibrated using the auxiliary control circuit 206. For example, the auxiliary control circuit 206 may include a device or system located outside the drive-detection device 202 and including a high-precision voltage or current source.

[0046] The auxiliary control circuit 206 may include a calibration input 364 to receive a user-specified calibration input 364 from an external source. The auxiliary control circuit 206 may include a calibration amplifier 362 configured to receive either the calibration input 364 or feedback information from the DUT 130 or calibration information from various components within the drive-detection device 202. In one example, the calibration signal V input may be provided by a DAC circuit in response to a digital calibration signal. For example, feedback information from the DUT 130 may be selectively provided to the auxiliary control circuit 206 by the drive-detection device 202 using a first detection switch 372 and a second detection switch 374. The calibration amplifier 362 may be coupled to the drive-detection device 202 via a first auxiliary input node 376 and may provide a known signal (e.g., based on the V input) to the DUT 130 and one or more other parts of the drive-detection device 202. In response to a known drive signal, the response information or other behavior of the DUT or the drive-detection device 202 may be monitored or measured, thereby enabling user calibration of the multi-grain drive-detection test system 300.

[0047] In one example, in drive calibration mode, the first selector circuit 322 can be configured to transmit a signal from the auxiliary control circuit 206 to the first device output node 346, the feedback switch 330 can be turned off, and the first detection switch 372 and the second detection switch 374 can be turned off. In drive calibration mode, the first drive amplifier 310 can be placed in feedback mode to help prevent internal damage, such as to various parts of the PMU circuitry. That is, in drive calibration mode, the calibration amplifier 362 in the auxiliary control circuit 206 provides a signal to control one or more buffers on the second semiconductor device 308, and the controller circuit 210 may not be used.

[0048] In the detection and calibration mode, the DUT detection circuit can be calibrated, including various precision resistors (e.g., in the drive-sensor device 202). Figure 3 (R1-R6 in the example; referred to herein as sense resistors or output resistors). In one example, the current calibration signal may be received by the drive-sensor device 202 at the first calibration input node 228. The first diode 368 may be coupled between the first calibration input node 228 of the first drive-sensor device 202 and other circuitry, such as to help prevent potential damage to the external calibration signal from other circuitry in the drive-sensor device 202. For example, the first diode 368 may be coupled between the first calibration input node 228 and the resistor network in the second semiconductor device 308. Other switches may optionally be positioned at the first calibration input node 228 or between the first diode 368 and one or more of the DUT pin 128 of the output buffer circuit, the DCL circuit 230, the DUT sense resistor 370, or other portions thereof.

[0049] Based on information about the current calibration signal and information received via the input from the second selector circuit 326, the accurate resistance values ​​of various sensing resistors (e.g., R1-R6) can be determined. Therefore, calibration of the drive-sensor device 202 in each of multiple different current sensing and drive ranges can be facilitated by providing a known current calibration signal and then measuring the corresponding response from each input of the second selector circuit 326.

[0050] In one example, the resistance information for the first sensing resistor R1 can be measured using a known auxiliary current signal provided by the auxiliary control circuit 206. In one example, the auxiliary control circuit 206 can provide the auxiliary current signal to the first sensing resistor via a first range switch 386. The first range switch 386 may include the output coupled to the first buffer circuit 306 and the first node of the first sensing resistor R1 (e.g., ...). Figure 3The first node in the node detection (A) is a first node, and the first range switch 386 may include a second node coupled to the second auxiliary input node 382. When the first range switch 386 is closed, the signal path is provided from the auxiliary control circuit 206 to the DUT node via the first sensing resistor R1. The DCL circuit 230 can be enabled, thereby representing a low impedance that can absorb the auxiliary current signal. The voltage across the first sensing resistor R1 can be used by the auxiliary control circuit 206, for example, to measure signal information received via the first sensing switch 372 and the second sensing switch 374. Correspondingly, the resistance of the first sensing resistor R1 can be determined based on known information about the voltage across R1 and known information about the auxiliary current signal.

[0051] Similarly, the resistance information for the second sensing resistor R2 can be measured using the auxiliary control circuit 206 via an auxiliary drive signal provided by the second range switch 388. The second range switch 388 may include the output coupled to the second buffer circuit 312 and the first node of the second sensing resistor R2 (e.g., ...). Figure 3 The first node of the node detection (B) in the second range switch 388 may include a second node coupled to the third auxiliary input node 384. When the second range switch 388 is closed, the signal path is provided from the auxiliary control circuit 206 to the DUT node 130 via a series combination of the first detection resistor R1 and the second detection resistor R2. The voltage across the series combination of the first and second detection resistors can be measured by the auxiliary control circuit 206, for example, by signal information received via the first detection switch 372 and the second detection switch 374. Since the voltage across the series combination of the first and second detection resistors is known, the auxiliary current signal is known, and the resistance of the first detection resistor R1 is known (e.g., from a previous calibration step, as described above), the resistance of the series combination of the first and second detection resistors can be calculated, and correspondingly, the resistance of the second detection resistor R2 can be calculated.

[0052] In one example, the range switches discussed herein (e.g., including a first range switch 386 and a second range switch 388) may comprise small, high-impedance switching devices. The switching devices can be fabricated using known processes via CMOS or analog die. A relatively small reference current is used to measure or characterize the resistance of the range switch, and therefore, the range switch can be small in physical size. After measuring the resistance value of the sense resistor, a larger current can be generated (e.g., using circuitry within the drive-sensor device 202). When the larger current is used, the relatively smaller range switch can be turned off, and correspondingly, the signal path corresponding to the smaller range switch does not carry the larger current signal.

[0053] In one example, in test mode, the first selector circuit 322 can be configured to transmit a signal from the first driver amplifier 310 to the first device output node 346, turn on the feedback switch 330, and turn on the first detection switch 372 and the second detection switch 374. In test mode, when other driver circuitry, such as the calibration amplifier 362 in the auxiliary control circuitry 206, is unavailable, the first driver amplifier 310 can provide a signal to control the output buffer circuitry.

[0054] In one example, the drive-sensor 202 can be configured to clamp at pin 128 of the DUT to help avoid or prevent damage to the drive-sensor 202, such as when the device is in calibration mode. The clamping circuit can be configured to clamp the output of the first drive amplifier 310 if the voltage or current applied to the DUT 130 exceeds a specified upper or lower clamping level. The clamping circuit also functions in the event of a short-circuit or open-circuit event. The clamping circuit can also protect the DUT 130 if transient voltage or current spikes occur when switching to a different operating mode or programming the device to a different current range. In one example, if the voltage at pin 128 of the DUT exceeds a specified threshold voltage during a calibration routine, the first selector circuit 322 can decouple the auxiliary control circuit 206 and restore system control to the controller circuit 210.

[0055] Although Figure 3 The example shows the first diode 368 as a component of the drive-detection device 202, but the first diode 368 can also be located outside the drive-detection device 202. For example, the first diode 368 can be coupled to a first calibration input node 228 outside the drive-detection device 202, or the first diode 368 can be located in the auxiliary control circuit 206.

[0056] Figure 3 The example generally illustrates a device interface 314 coupling a first semiconductor device 304 and a second semiconductor device 308. Device interface 314 may include one or more signal paths configured to transmit information between different semiconductor devices. One or more electrical conductors may be configured for unidirectional or bidirectional communication. The number of signal paths or conductors in device interface 314 can be minimized to simplify interconnection between different semiconductor devices.

[0057] In one example, the first semiconductor device 304, such as including a portion of PMU circuitry, can be a low-cost, low-speed semiconductor device on which an integrated device can be built or through which an integrated device can be built. For example, the first semiconductor device 304 may include a CMOS die through which a CMOS switching device can be built. The second semiconductor device 308, such as including another portion of PMU circuitry, DCL circuitry 230, or other circuitry, can be a high-cost, high-speed semiconductor device on which an integrated device can be built or through which an integrated device can be built. For example, the second semiconductor device 308 may include a bipolar die through which a bipolar switching device can be built. The first semiconductor device 304 and its accompanying manufacturing processes may include or use fewer masks, larger-size lithography techniques, larger tolerances, and may have a higher overall yield compared to the second semiconductor device 308.

[0058] exist Figure 3 In the example, the first semiconductor device 304 and the second semiconductor device 308 include various interface nodes that communicate with the auxiliary control circuit 206. For example, the first semiconductor device 304 includes a first auxiliary input node 376, a DUT current detection node 378, and a DUT voltage detection node 380. The second semiconductor device 308 includes a first calibration input node 228, a second auxiliary input node 382, ​​and a third auxiliary input node 384.

[0059] The first semiconductor device 304 may also include various switching devices, including a detection amplifier output switch 348, an instrumentation amplifier output switch 336, a first detection switch 372, a second detection switch 374, and a feedback switch 330. In one example, the first semiconductor device 304 may include a first selector circuit 322, such as an integrated multiplexer device or a discrete switch configured to perform multiplexer functions. Various switches and multiplexers can generally be implemented more easily and inexpensively using the first semiconductor device 304 compared to similar devices implemented using the second semiconductor device 308.

[0060] Integrating the switching device with the first semiconductor device 304 of the multi-die drive-detection test system 300 offers various benefits for system calibration. For example, by providing an integrated switch, the load issues associated with external switches can be avoided, and a larger current signal amplitude range can be used in the calibration procedure. In an example where no integrated switch is provided to intervene in the drive circuitry of the test system, a relatively large external switch can be used to receive a large calibration current signal from the test system, and this large switch can reverse-load the DUT pin 128. Conversely, by providing calibration signal access points located within the multi-die drive-detection test system 300, such as via various integrated switches, external calibration circuitry can be used to control the integrated drive signal circuitry of the system, such as the output buffer circuitry of the multi-die drive-detection test system 300.

[0061] exist Figure 3 In the example, the first semiconductor device 304 includes various device interface nodes for communicating with the second semiconductor device 308, such as using device interface 314. The second semiconductor device 308 includes various device interface nodes for communicating with the first semiconductor device 304, such as using device interface 314. For example, the first semiconductor device 304 includes a first device output node 346, a first device feedback node 350, and a first device dual-purpose node 352. The second semiconductor device 308 includes a second device input node 354, a second device feedback node 360, and a second device dual-purpose node 356. Various signal paths extending between the device interface nodes may include device interface 314. For example, device interface 314 may include a first signal path 324, a second signal path 328, and a bidirectional signal path 332. Typically, the first signal path 324 is a unidirectional signal path for transmitting signals from the first semiconductor device 304 to the second semiconductor device 308, and the second signal path 328 is a unidirectional signal path for transmitting signals from the second semiconductor device 308 to the first semiconductor device 304.

[0062] In one example, a first signal path 324 can transmit a drive control signal 334 from a first semiconductor device 304 to a second semiconductor device 308. A first selector circuit 322 can be configured to provide the drive control signal 334 at a first device output node 346, such as based on auxiliary control circuitry 206 or a first drive amplifier 310. The first signal path 324 in the device interface 314 can be used to transmit the drive control signal 334 to a second device input node 354 at the second semiconductor device 308. In one example, the second device input node 354 is coupled to a buffer circuit network in the second semiconductor device 308. The buffer circuit network can include various buffer circuit instances that can be configured independently or selectively to provide an output signal to the DUT 130 in response to the drive control signal 334.

[0063] The second signal path 328 can transmit the first DUT detection signal 342 from the second semiconductor device 308 to the first semiconductor device 304. The first DUT detection signal 342 may include, for example, a current or voltage signal received from the DUT 130 via the DUT detection resistor 370. The second semiconductor device 308 may provide the first DUT detection signal 342 at the second device feedback node 360, and the first semiconductor device 304 may receive the first DUT detection signal 342 at the first device feedback node 350.

[0064] The bidirectional signal path 332 can be configured to transmit a drive-detection signal 338 between a first dual-purpose node 352 at the first semiconductor device 304 and a second dual-purpose node 356 at the second semiconductor device 308. The characteristics of the drive-detection signal 338 can depend on the operating mode of the multi-die drive-detection test system 300. For example, in test mode, the drive-detection signal 338 may include an unbuffered, small-amplitude DUT drive signal transmitted from the first semiconductor device 304 to the DUT 130 via the second semiconductor device 308. In auxiliary control mode or calibration mode, the drive-detection signal 338 may include a second DUT detection signal received by and transmitted from the second semiconductor device 308 to the first semiconductor device 304.

[0065] In one example, a signal source on the first semiconductor device 304 can be used to generate a small-amplitude DUT drive signal. Figure 3In this configuration, at least one of the fourth range switch 318 and the fifth range switch 320 can be used to provide a small-amplitude DUT drive signal. At least one of the fourth range switch 318 and the fifth range switch 320 can be configured to transmit an output signal, such as from one of the first drive amplifiers 310 or from the auxiliary control circuit 206, to the first device dual-purpose node 352, and the fourth range switch 318 and the fifth range switch 320 can be controlled independently. The corresponding signals provided via the fourth range switch 318 and the fifth range switch 320 can have different amplitude characteristics.

[0066] In one example, the bidirectional signal path 332 can be configured to transmit a drive-detection signal 338 between a first dual-purpose node 352 at the first semiconductor device 304 and a second dual-purpose node 356 at the second semiconductor device 308 for detecting the calibration of resistors R1-R3. For example, in calibration mode, the drive-detection signal 338 may include a calibration current signal transmitted from the first semiconductor device 304 to the DUT node of the second semiconductor device 308 via a third range switch 390. In one example, the third range switch 390 may be coupled to the first dual-purpose node 352 and to nodes coupled to the first selector circuit 322, the fourth range switch 318, and the fifth range switch 320. The calibration current signal can be generated using a signal source on the first semiconductor device 304 or using auxiliary control circuitry 206. When the third range switch 390 is closed, the signal path is provided from the calibration current signal source via a series combination of resistors R1-R3. The voltage across the series combination of resistors R1-R3 can be measured using the auxiliary control circuit 206, for example, by signal information received via the first detection switch 372 and the second detection switch 374. If the resistances of the first detection resistor R1 and the second detection resistor R2 are known, the resistance of the detection resistor R3 can be calculated.

[0067] In another test mode of the multi-die driven-detection test system 300, the bidirectional signal path 332 can be configured to transmit a second DUT detection signal from the second semiconductor device 308 to the first semiconductor device 304. That is, the second semiconductor device 308 can receive DUT information from the DUT 130 and provide the second DUT detection signal to the first dual-purpose node 352 of the first semiconductor device 304 at the second dual-purpose node 356. In one example, the second DUT detection signal can be reported to a control system or received by the second selector circuit 326. In one example, the second dual-purpose node 356 can provide the second DUT detection signal, and the second device feedback node 360 ​​can simultaneously provide the first DUT detection signal 342.

[0068] Examples of the multi-die drive-detection test system 300 include various switches, sources, signal paths, and other devices that can be configured independently or collectively to provide small-amplitude DUT current drive signals. However, fewer or additional switches, sources, signal paths, and / or other devices can also be used. Examples of the multi-die drive-detection test system 300 include three buffer circuits: a first buffer circuit 306, a second buffer circuit 312, and a third buffer circuit 316, each with its own corresponding sense resistor. However, fewer or additional buffer circuits or resistors can also be used.

[0069] Figure 4 An example of a first method 400 that may be included as part of a calibration test system is generally shown. In one example, the first method 400 may include or use one or more of a first drive-detection test system 200 or a multi-grain drive-detection test system 300. While the exemplary first method 400 describes a particular sequence of operations, this sequence may be changed without departing from the scope of this disclosure.

[0070] At operation 402, the first method 400 may include preparing a test system for calibration by loading a low-impedance voltage source onto the DUT node of the system, such as by enabling an active load or driver (e.g., DCL circuit 230) coupled to the DUT node.

[0071] At operation 404, the first method 400 includes providing a first current signal using an external auxiliary controller at operation 404.

[0072] At operation 406, the first method 400 includes using a first current signal to determine the resistance of a first sense resistor in the output stage of the test system. Since the resistance is known, the first method 400 can continue with other operations to (1) calibrate or determine the accuracy of one or more buffers in the output stage of the test system, or (2) calibrate or determine the accuracy of a local (e.g., on-chip) controller used for the test system.

[0073] To calibrate or determine the accuracy of one or more buffers in the output stage, the first method 400 may continue at operation 408. At the start of operation 408, the DUT or other measurement device may be coupled to a DUT node. Operation 408 includes providing a first voltage signal using an external auxiliary controller. The first voltage signal may include external control signals for testing one or more buffers in the output stage of the system. (Reference) Figure 3 For example, operation 408 may include controlling the first selector circuit 322 to provide external control signals from the auxiliary control circuit 206 to the second device input node 354.

[0074] At operation 410, in response to the first voltage signal, one or more buffers in the output stage can provide output current at the DUT node of the test system. In one example, the one or more buffers use a signal path including a first sense resistor to provide output current. In one example, operation 410 includes determining the DUT voltage. (Reference) Figure 3 For example, operation 410 may include turning off the first detection switch 372 and the second detection switch 374 to receive DUT voltage information at the auxiliary control circuit 206.

[0075] At operation 412, the first method 400 includes measuring the output current at a node of the DUT. In one example, operation 412 includes using an external calibration system or device, such as auxiliary control circuitry 206, to measure the output current. If the amplitude of the measured output current conforms to a specified relationship with a first voltage signal provided at operation 408, the system can be considered calibrated or within tolerance. If the measured output current amplitude conforms to a specified relationship with the first voltage signal, the first method 400 may include iteratively updating the characteristics of the first voltage signal at operation 408 to change the operating characteristics of one or more buffers in the output stage, and correspondingly, changing the output current measured at operation 412.

[0076] In one example, a specified relationship between the output current and the first voltage signal indicates the offset characteristics of one or more components of the test system. For example, the relationship could indicate the offset of one or more buffers in the output stage. At operation 414, the first method 400 could include providing or updating offset information for one or more buffers based on the measured output current, thereby calibrating the operation of the system.

[0077] Returning to operation 406, after determining the resistance of the first sense resistor, the first method 400 can continue to calibrate or determine the accuracy of the local (e.g., on-chip) controller used to test the system. In one example, calibrating the local controller includes calibrating one or more aspects of the first drive amplifier 310 or the first DAC 302 of the drive-sensor device 202.

[0078] For example, at operation 416, the first method 400 may include generating a drive control signal using a local controller of the test system. In one example, operation 416 includes using a first DAC 302 to provide a test stimulus control signal to a first drive amplifier 310, and in response, the first drive amplifier 310 providing a drive control signal. (See reference...) Figure 3For example, operation 416 may include controlling the first selector circuit 322 to receive a local control signal from the first drive amplifier 310 at the drive control output node 224 and to provide a local control signal from the first drive amplifier 310 to the second device input node 354.

[0079] At operation 418, in response to the drive control signal, one or more buffers in the output stage of the test system can provide output current at the DUT node of the test system. In one example, one or more buffers use a signal path that includes a first sense resistor to provide output current.

[0080] At operation 420, the first method 400 includes measuring the voltage across the first sense resistor. In one example, operation 420 includes using an external calibration system or device, such as auxiliary control circuitry 206, to measure the voltage. In another example, operation 420 includes using circuitry for a drive-sensor device 202 to measure the voltage.

[0081] At operation 422, the first method 400 includes determining the magnitude of the output current based on the measured voltage and determined resistance of the first sense resistor. If the determined magnitude of the output current is consistent with a specified relationship of the test stimulus control signal of the local controller, the system can be considered calibrated or within tolerance. If the determined output current magnitude is consistent with the specified relationship of the test stimulus control signal, the first method 400 may include iteratively updating the characteristics of the test stimulus control signal at operation 416, thereby changing the operating characteristics of one or more buffers in the output stage, and correspondingly changing the output current determined at operation 422.

[0082] In one example, a specified relationship between the output current and the test excitation control signal indicates the offset characteristics of one or more components of the test system. For example, this relationship could indicate the offset of a local controller, such as the offset of the first DAC 302 and / or the first drive amplifier 310. At operation 424, the first method 400 could include providing or updating offset information for the local controller.

[0083] Figure 5The general illustration shows an example of a second method 500 that may include determining the resistance of one or more sense resistors or output resistors in the output stage of a test system. In one example, the second method 500 may include or use one or more of a first drive-detection test system 200 or a multi-die drive-detection test system 300. While the exemplary second method 500 describes a particular sequence of operations, this sequence may be varied without departing from the scope of this disclosure. In one example, the second method 500 may include preparing a test system for calibration by loading a low-impedance voltage source, such as by enabling an active load or driver (e.g., DCL circuit 230) coupled to the DUT node.

[0084] At operation 502, the second method 500 includes preparing a test system for calibration by loading a low-impedance voltage source onto the DUT node of the system, such as by enabling an active load or driver (e.g., DCL circuit 230) coupled to the DUT node.

[0085] In operation 504, the second method 500 includes closing the first range switch and opening the second range switch to electrically couple an external current source to the first sense resistor. In one example, referring to the multi-die drive-detection test system 300, operation 504 may include closing the first range switch 386 to electrically couple the first sense resistor R1 to the auxiliary control circuit 206, and operation 504 may further include opening the second range switch 388 to decouple the second sense resistor R2 from the auxiliary control circuit 206.

[0086] At operation 506, the second method 500 includes providing a first current signal from an external current source to the first sensing resistor. The first current signal may flow through the first sensing resistor. At operation 508, the second method 500 includes measuring a first voltage across the first sensing resistor, for example, when the first sensing resistor receives the first current signal from the external current source.

[0087] At operation 510, the second method 500 includes turning on a first range switch and turning off a second range switch to electrically couple an external current source to a second sense resistor. In one example, referring to a multi-die drive-detection test system 300, operation 510 may include turning off the second range switch 388 to electrically couple the second sense resistor R2 to auxiliary control circuitry 206, and operation 510 may also include turning on the first range switch 386 to decouple the first sense resistor R1 from auxiliary control circuitry 206.

[0088] At operation 512, the second method 500 includes providing a second current signal from an external current source to the second sensing resistor. The second current signal may, for example, flow through a series circuit including the first and second sensing resistors. At operation 514, the second method 500 includes measuring a second voltage across the series combination of the first and second sensing resistors, for example, when the resistors receive the second current signal from the external current source.

[0089] At operation 516, the second method 500 may include determining the resistance of the first and second sense resistors. For example, the first sense resistor and its resistance can be determined using Ohm's law with the measured first voltage information from operation 508 and information about the amplitude of a first current signal provided by an external current source. Similarly, the resistance of the series combination of the first and second sense resistors can be determined using the measured second voltage information from operation 514 and information about the amplitude of a second current signal provided by an external current source. The resistance of the second output resistor can be determined by subtracting the determined resistance of the first sense resistor from the determined resistance of the series combination of the first and second sense resistors. Examples of the second method 500 can also be used to determine the resistance of one or more other sense resistors in the polycrystalline drive-detection test system 300.

[0090] Various aspects of this disclosure can help provide solutions to the test system-related issues identified herein, as illustrated in the following examples.

[0091] Example 1 is a test apparatus system for providing or receiving signals to or from a device under test (DUT), the system comprising: an output buffer circuit configured to provide a DUT signal to a DUT at a DUT interface node in response to a drive control signal at a buffer control node; a first sense resistor coupled to the DUT interface node and the output buffer circuit; a first range switch coupled to the first sense resistor and an auxiliary driver input node; a controller circuit configured to provide a drive control signal at the buffer control node; and an auxiliary control circuit configured to bypass the controller circuit and selectively provide an auxiliary control signal at one of the buffer control node and the auxiliary driver input node.

[0092] In Example 2, the subject of Example 1 optionally includes an auxiliary control circuit configured to provide an auxiliary control signal as a current signal at the input node of the auxiliary driver.

[0093] In Example 3, the subject of Example 2 optionally includes a voltage detection circuit configured to measure a voltage signal across a first sensing resistor in response to a current signal.

[0094] In Example 4, the subject matter of any one or more of Examples 1 to 3 optionally includes an auxiliary control circuit configured to provide an auxiliary control signal as a voltage signal at the buffer control node.

[0095] In Example 5, the subject matter of any one or more of Examples 1 to 4 optionally includes a bypass circuit configured to selectively couple a buffer control node to a controller circuit or an auxiliary control circuit.

[0096] In Example 6, the subject matter of any one or more of Examples 1 to 5 optionally includes an output buffer circuit that includes multiple buffers coupled to the DUT using corresponding sense resistors, and selects one or more of the multiple buffers to provide DUT signals to the DUT interface node based on the characteristics of the drive control signal at the buffer control node.

[0097] In Example 7, the subject of Example 6 optionally includes multiple buffers, including a first buffer coupled to the DUT interface node using a first sense resistor, and a second buffer coupled to the DUT interface node using a first sense resistor and a second sense resistor.

[0098] In Example 8, the subject of Example 7 optionally includes a second range switch configured to selectively couple a second driver input node to a second sense resistor.

[0099] In Example 9, the subject matter of Example 8 optionally includes a third buffer and a third range switch, the third buffer being coupled to the DUT interface node using a first sense resistor, a second sense resistor, and a third sense resistor, the third range switch being configured to selectively couple the third sense resistor to receive auxiliary control signals.

[0100] In Example 10, the subject matter of Example 9 optionally includes a third range switch that includes a portion of a first semiconductor die of a first semiconductor type, and a first range switch and a second range switch that include portions of a second semiconductor die of a second semiconductor type.

[0101] Example 11 is a system for providing or receiving signals to or from a device under test (DUT) node, the system comprising: a first integrated circuit (IC) including a portion of a first semiconductor die of a first semiconductor type, the first IC including: a local controller configured to generate a local drive control signal for a drive-detection test system; and a bypass circuit configured to provide a buffer control signal to an output buffer circuit based on a local drive control signal from the local controller or an auxiliary control signal from an external auxiliary controller for the same drive-detection test system; and a second IC including a portion of a second semiconductor die of a second semiconductor type, the second IC including: the output buffer circuit; a first sense resistor coupled to the first buffer and the DUT node; and a first range switch coupled to the first sense resistor and an auxiliary driver input node, wherein the auxiliary driver input node is configured to receive an auxiliary drive signal from an external auxiliary controller.

[0102] In Example 12, the subject matter of Example 11 optionally includes a second IC comprising: a second sensing resistor coupled to a second buffer and a first sensing resistor; and a second range switch coupled to the second sensing resistor and a second driver input node, wherein the second driver input node is configured to receive an auxiliary drive signal from an external auxiliary controller.

[0103] In Example 13, the subject matter of any one or more of Examples 11 to 12 optionally includes a second IC that includes a third sensing resistor; and a first IC that includes a third range switch coupled to the third sensing resistor and configured to receive an auxiliary drive signal from an external auxiliary controller.

[0104] In Example 14, the subject matter of Example 13 optionally includes a first IC that includes a fourth sensing resistor and a fourth range switch, the fourth sensing resistor being coupled between the third range switch and the fourth range switch, and the fourth range switch being configured to receive an auxiliary drive signal from an external auxiliary controller.

[0105] In Example 15, the subject matter of any one or more of Examples 11 to 14 optionally includes an external auxiliary controller, and the external auxiliary controller includes a calibration signal source configured to provide a calibration signal to calibrate the first sense resistor and the first buffer.

[0106] Example 16 is a method for calibrating an automated test equipment (ATE) system, the method comprising: determining the resistance of a first sense resistor using a first current signal from an external auxiliary controller, wherein the first sense resistor is coupled to a device under test (DUT) node of the system; providing an output current at the DUT node using one or more buffers in the output stage of the system via the first sense resistor in response to a first voltage control signal from the external auxiliary controller; measuring the output current at the DUT node; and providing offset information about one or more buffers in the output stage based on the measured output current.

[0107] In Example 17, the subject matter of Example 16 optionally includes determining the resistance of a first sensing resistor, comprising: providing a first current signal to the first sensing resistor using a first range switch; measuring a first voltage across the first sensing resistor using second and third switches; and determining the resistance of the first sensing resistor based on the amplitude of the first current signal and the measured first voltage. In Example 17, the second and third switches comprise portions of a first semiconductor die of a first semiconductor type, and the first range switch comprises a portion of a second semiconductor die of a second semiconductor type.

[0108] In Example 18, the subject matter of any one or more of Examples 16 to 17 optionally includes determining the resistance of a first sense resistor, including: closing a first range switch to provide a signal path from an external auxiliary controller to the first sense resistor, wherein the first range switch is coupled to a first buffer output of one or more buffers in the output stage; measuring a first voltage across the first sense resistor; and using the amplitude of a first current signal and the measured first voltage to determine the resistance.

[0109] In Example 19, the subject matter of Example 18 optionally includes using a second current signal from an external auxiliary controller to determine the resistance of a second sense resistor, and the second sense resistor being coupled between a first sense resistor and a second buffer output of one or more buffers in the output stage.

[0110] In Example 20, the subject matter of Example 19 optionally includes determining the resistance of a second sensing resistor, comprising: turning on a first range switch and turning off a second range switch to provide a signal path from an external auxiliary controller to the second sensing resistor; using the second range switch to provide a second current signal to the series combination of the first and second sensing resistors; measuring a second voltage across the series combination of the first and second sensing resistors; and using the amplitude of the second current signal and the measured second voltage to determine the resistance.

[0111] Example 21 is a method for calibrating an automated test equipment (ATE) system, the method comprising: determining the resistance of a first sense resistor using a first current signal from an external auxiliary controller, wherein the first sense resistor is coupled to a device under test (DUT) node of the system; generating a first drive control signal using a local controller for a parameter measurement unit of the system; receiving the drive control signal at an output buffer circuit and, in response, providing a first DUT signal to the DUT at the DUT node and measuring the voltage across the first sense resistor; determining a current at the DUT node based on the measured voltage of the first sense resistor and the determined resistance; and updating characteristics of the local controller based on the determined current at the DUT node.

[0112] In Example 22, the subject matter of Example 21 optionally includes updating the characteristics of the local controller, including updating the offset for the digital-to-analog converter (DAC) circuitry configured to control the operation of the local controller.

[0113] Example 23 is at least one non-transitory machine-readable medium containing instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any one of Examples 1 to 22.

[0114] Example 24 is an apparatus that includes means for implementing any one of Examples 1 to 22.

[0115] Example 25 is a system for implementing any one of Examples 1 through 22.

[0116] Each of these non-restrictive examples may exist independently, or may be combined in various permutations or combinations with one or more of the other examples or features discussed elsewhere in this document.

[0117] The detailed description includes accompanying drawings, which form a part of the detailed description. The drawings illustrate, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate that only examples of those elements shown or described are provided herein. The inventors consider examples of any combination or substitution of those elements (or one or more aspects thereof) with respect to specific examples (or one or more aspects thereof), or to other examples shown or described herein (or one or more aspects thereof).

[0118] In this document, as is common in patent documents, the term “a / an” is used to include one or more, regardless of any other example or use of “at least one” or “one or more”. In this document, the term “or” is used to refer to a non-exclusive “or”, therefore, unless otherwise stated, “A or B” includes “A but not B”, “B but not A”, and “A and B”. In this document, the terms “including” and “in which” are used as concise English equivalents to the corresponding terms “comprising” and “wherein”.

[0119] In the following claims, the terms "comprising" and "including" are open-ended, meaning that systems, apparatuses, articles, compositions, formulations, or processes that include other elements besides those listed following such terms in the claims are still considered to be within the scope of the claims. Furthermore, in the following claims, the terms "first," "second," "third," etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0120] The method examples described herein can be implemented at least in part by a machine or computer. Some examples may include a computer-readable medium or a readable medium thereof encoded with instructions that can be operated to configure an electronic device to perform the methods or circuit operations or circuit configuration instructions in the examples described above. Implementations of this method may include code, such as microcode, assembly language code, higher-level language code, etc. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, in one example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as at the execution device or at other times. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical discs (e.g., optical discs and digital video discs), magnetic tape cartridges, memory cards or memory sticks, random access memory (RAM), read-only memory (ROM), etc.

[0121] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used by those skilled in the art upon review of the above description. An abstract is provided to allow the reader to quickly determine the nature of the technical disclosure. This abstract is submitted under the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be combined to simplify this disclosure. This should not be construed as an intention that unclaimed features are essential to any claim. Rather, the subject matter of the invention may lie in fewer than all features of a particular disclosed embodiment. Therefore, the following claims are incorporated into the detailed description as examples or embodiments, each claim existing independently as a separate embodiment, and such embodiments are contemplated to be combined with each other in various combinations or substitutions. The scope of the invention should be determined by reference to the appended claims and the full scope of the equivalents granted by such claims.

Claims

1. A test equipment system for providing signals to or receiving signals from a device under test (DUT), the system comprising: An output buffer circuit is configured to provide a DUT signal to the DUT at the DUT interface node in response to a drive control signal at the buffer control node. A first sensing resistor is coupled to the DUT interface node and the output buffer circuit; A first range switch is coupled to the first sensing resistor and the auxiliary driver input node; A controller circuit configured to provide the drive control signal at the buffer control node; as well as An auxiliary control circuit is configured to bypass the controller circuit and selectively provide auxiliary control signals at one of the buffer control node and the auxiliary driver input node.

2. The test equipment system according to claim 1, wherein the auxiliary control circuit is configured to provide the auxiliary control signal as a current signal at the input node of the auxiliary driver.

3. The test equipment system of claim 2, further comprising a voltage detection circuit configured to measure a voltage signal across the first detection resistor in response to the current signal.

4. The test equipment system according to claim 1, wherein the auxiliary control circuit is configured to provide the auxiliary control signal as a voltage signal at the buffer control node.

5. The test equipment system according to claim 1, further comprising a bypass circuit configured to selectively couple the buffer control node to the controller circuit or the auxiliary control circuit.

6. The test equipment system of claim 1, wherein the output buffer circuit comprises a plurality of buffers coupled to the DUT using corresponding sense resistors, and wherein one or more of the plurality of buffers are selected to provide the DUT signal to the DUT interface node based on the characteristics of the drive control signal at the buffer control node.

7. The test equipment system according to claim 6, wherein the plurality of buffers comprises: A first buffer, the first buffer being coupled to the DUT interface node using the first sensing resistor; and The second buffer is coupled to the DUT interface node using the first and second sensing resistors.

8. The test equipment system of claim 7, further comprising a second range switch configured to selectively couple a second driver input node to the second sense resistor.

9. The testing equipment system according to claim 8, comprising: A third buffer, wherein the third buffer is coupled to the DUT interface node using the first sense resistor, the second sense resistor, and the third sense resistor; and A third range switch is configured to selectively couple the third sensing resistor to receive the auxiliary control signal.

10. The test equipment system of claim 9, wherein the third range switch comprises a portion of a first semiconductor die of a first semiconductor type, and wherein the first range switch and the second range switch comprise portions of a second semiconductor die of a second semiconductor type.

11. A system for providing a signal to or receiving a signal from a device under test (DUT) at a node, the system comprising: A first integrated circuit (IC), the first integrated circuit (IC) comprising a portion of a first semiconductor die of a first semiconductor type, the first IC comprising: A local controller, configured to generate local drive control signals for a drive-detection test system; and A bypass circuit, configured to provide a buffer control signal to an output buffer circuit based on a local drive control signal from the local controller or an auxiliary control signal from an external auxiliary controller for the same drive-detection test system; and The second IC, the second IC comprising a portion of a second semiconductor die of a second semiconductor type, the second IC comprising: The output buffer circuit; A first sensing resistor, coupled to a first buffer and the DUT node; and A first range switch is coupled to the first sensing resistor and an auxiliary driver input node, wherein the auxiliary driver input node is configured to receive an auxiliary drive signal from the external auxiliary controller.

12. The system of claim 11, wherein the second IC comprises: A second sensing resistor is coupled to a second buffer and a first sensing resistor; and A second range switch is coupled to the second sensing resistor and the second driver input node, wherein the second driver input node is configured to receive an auxiliary drive signal from the external auxiliary controller.

13. The system of claim 11, wherein the second IC includes a third sensing resistor; and The first IC includes a third range switch coupled to the third sensing resistor and configured to receive the auxiliary drive signal from the external auxiliary controller.

14. The system of claim 13, wherein the first IC includes a fourth sensing resistor and a fourth range switch; The fourth sensing resistor is coupled between the third range switch and the fourth range switch; and The fourth range switch is configured to receive the auxiliary drive signal from the external auxiliary controller.

15. The system of claim 11, further comprising the external auxiliary controller, wherein the external auxiliary controller includes a calibration signal source configured to provide a calibration signal to calibrate the first sensing resistor and the first buffer.

16. A method for calibrating an automated test equipment (ATE) system, the method comprising: The resistance of the first sense resistor is determined using a first current signal from an external auxiliary controller, wherein the first sense resistor is coupled to the device under test (DUT) node of the system. In response to a first voltage control signal from the external auxiliary controller, one or more buffers in the output stage of the system provide the output current at the DUT node via the first sense resistor; Measure the output current at the DUT node; as well as The offset information about the one or more buffers in the output stage is provided based on the measured output current.

17. The method of claim 16, wherein determining the resistance of the first detection resistor comprises: The first current signal is provided to the first sensing resistor using the first range switch; The first voltage across the first sensing resistor is measured using the second and third switches; as well as The resistance of the first detection resistor is determined based on the amplitude of the first current signal and the measured first voltage; The second and third switches include a portion of a first semiconductor die of a first semiconductor type, and the first range switch includes a portion of a second semiconductor die of a second semiconductor type.

18. The method of claim 16, wherein determining the resistance of the first detection resistor comprises: The first range switch is closed to provide a signal path from the external auxiliary controller to the first sensing resistor, wherein the first range switch is coupled to a first buffer output of the one or more buffers in the output stage; Measure the first voltage across the first sensing resistor; as well as The resistance is determined using information about the amplitude of the first current signal and the measured first voltage.

19. The method of claim 18, further comprising using a second current signal from the external auxiliary controller to determine the resistance of a second sense resistor, wherein the second sense resistor is coupled between the first sense resistor and a second buffer output of the one or more buffers in the output stage.

20. The method of claim 19, wherein determining the resistance of the second detection resistor comprises: Turn on the first range switch and turn off the second range switch to provide a signal path from the external auxiliary controller to the second sensing resistor; The second range switch is used to provide a second current signal to the series combination of the first and second detection resistors; Measure the second voltage across the series combination of the first and second sensing resistors; as well as The resistance is determined using information about the amplitude of the second current signal and the measured second voltage.

21. A method for calibrating an automated test equipment (ATE) system, the method comprising: The resistance of the first sense resistor is determined using a first current signal from an external auxiliary controller, wherein the first sense resistor is coupled to the device under test (DUT) node of the system. The first drive control signal is generated using a local controller of the parameter measurement unit for the system. The drive control signal is received at the output buffer circuit, and in response, a first DUT signal is provided to the DUT at the DUT node, and the voltage across the first sense resistor is measured; The current at the DUT node is determined based on the measured voltage and determined resistance of the first detection resistor; as well as The characteristics of the local controller are updated based on the current determined at the DUT node.

22. The method of claim 21, wherein updating the characteristics of the local controller includes updating the offset for a digital-to-analog converter (DAC) circuit configured to control the operation of the local controller.

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