A scheduling circuit and apparatus

Abstract

The application relates to the technical field of processor scheduling, and discloses a scheduling circuit and equipment, the scheduling circuit comprising a scheduling tree control unit and a scheduling tree; the scheduling tree comprises scheduling nodes; the scheduling nodes comprise tree root nodes located at the bottom layer, intermediate nodes located at the middle layer, and leaf nodes located at the highest layer; the scheduling nodes are cascaded through the scheduling tree control unit; the tree root nodes, the intermediate nodes, and the leaf nodes each comprise at least one authorized scheduler; the leaf nodes are used for receiving requests from request sources; and the scheduling tree control unit is used for selecting an authorized result from the requests received by the leaf nodes from the request sources according to authorized requests of the scheduling nodes. The above scheme greatly shortens the task waiting scheduling time and improves the scheduling efficiency of the scheduling circuit.

Description

Technical Field

[0001] This application relates to the field of processor scheduling technology, specifically to a scheduling circuit and device. Background Technology

[0002] In the field of computer processor scheduling, scheduling circuits have extremely wide and crucial applications. As computing demands become increasingly complex, multi-core processors, heterogeneous computing architectures, and high-concurrency scenarios (such as cloud computing and real-time systems) place higher demands on task scheduling.

[0003] Hardware scheduling circuits directly manage resource allocation through dedicated logic units, significantly reducing scheduling latency. However, their performance largely depends on the coordinated optimization of algorithm execution efficiency and hardware cycle time. The scheduling circuit bears the core responsibility of task scheduling. Based on various complex scheduling algorithms, such as priority-based scheduling algorithms, it assigns higher priority to critical tasks with high real-time requirements and significant impact on overall system performance. This ensures that these tasks receive processor time slices first, allowing tasks related to the operating system kernel and critical data processing to execute promptly, thus guaranteeing stable and efficient system operation.

[0004] Cascaded schedulers, formed by connecting multiple schedulers in series, suffer from significant latency between requests and authorizations, as well as prolonged authorization times between rounds. This severely impacts the efficiency of the scheduling circuit and consumes substantial amounts of cache. The execution speed of the scheduling algorithm directly affects the device's instruction cycle efficiency, hardware cycle utilization, and energy efficiency. Therefore, a highly efficient cascaded scheduling circuit is urgently needed. Summary of the Invention

[0005] In view of this, this application provides a scheduling circuit and device that improves the scheduling efficiency of the scheduling circuit.

[0006] In a first aspect, this application provides a scheduling circuit, which includes a scheduling tree control unit and a scheduling tree;

[0007] The scheduling tree includes scheduling nodes; each scheduling node includes a root node at the bottom layer, intermediate nodes in the middle layer, and leaf nodes at the top layer; each of the root node, intermediate nodes, and leaf nodes includes at least one authorized scheduler; the scheduling nodes are cascaded through scheduling tree control units; the leaf nodes are used to receive requests from request sources.

[0008] The scheduling tree control unit is used to enable the scheduling node to generate a request based on the request from the request source or after receiving a request from the upper-level node of the scheduling node; the authorization scheduler in the scheduling node is used to determine the authorization request from the requests received by the scheduling node.

[0009] The scheduling tree control unit is used to select an authorization result from the requests received by the request source in the leaf node according to the authorization request of the scheduling node.

[0010] In one alternative implementation, the root node of the scheduling tree manages requests from intermediate nodes cascaded with the root node through a scheduling tree control unit; the intermediate nodes are used to manage requests from leaf nodes cascaded with the intermediate nodes through the scheduling tree control unit.

[0011] In one alternative implementation, an authorization scheduler in each scheduling node is used to select authorization requests from the requests received by the scheduling node;

[0012] The scheduling tree control unit is also used to merge all the nodes corresponding to the authorization requests into a target path from the bottom layer to the top layer after receiving the authorization request from the scheduling node, and select the authorization result from the requests received by the leaf nodes in the target path.

[0013] In one optional implementation, each scheduling node includes a dual-authorization computation scheduler; the dual-authorization computation scheduler is used to generate a first authorization request and a second authorization request based on the input request; the second authorization request is generated after excluding the first authorization request.

[0014] In one optional implementation, the dual-authorization computing scheduler includes a first authorized computing core, a second authorized computing core, and an authorization status control module;

[0015] The first authorization calculation core is used to perform authorization calculation on the received request according to the authorization algorithm to determine the first authorization request;

[0016] The second authorization calculation core is used to confirm the first authorization request in the received request, and then perform authorization calculation through the authorization algorithm to determine the second authorization request;

[0017] The authorization status control module is used to record the first authorization request and the second authorization request, and send the recording results to the scheduling tree control unit.

[0018] In one optional implementation, the dual-authorization computing scheduler includes a first authorized computing core, a second authorized computing core, and an authorization status control module;

[0019] The first authorization calculation core is used to perform authorization calculation on the received request according to the authorization algorithm to determine the first authorization request;

[0020] The second authorization calculation core is used to confirm the first authorization request in the received request, and then perform authorization calculation through the authorization algorithm to determine the second authorization request;

[0021] The authorization status control module is used to record the first authorization request and the second authorization request, and send the recording results to the scheduling tree control unit.

[0022] In one optional implementation, the dual-authorization computing scheduler further includes a request control module and a status register;

[0023] The request control module is used to process the currently accessed requests, close requests without permission, and obtain valid requests.

[0024] The first authorization calculation core is used to perform authorization calculation based on the valid request processed by the authorization algorithm, so as to determine the first authorization request;

[0025] The status register is used to store the first authorization request.

[0026] In one optional implementation, the dual-authorization computation scheduler further includes a mask computation module and a second request computation module;

[0027] The mask calculation module is used to generate an upper mask and a lower mask based on the first authorization request; the upper mask is located above the previous authorization position in the authorization schedule, and its high-level bits are high, which is the part to be masked; the lower mask is the inverse of the upper mask;

[0028] The second request calculation module is used to perform an AND operation between the received request and the upper or lower mask to generate a request that masks the first authorization request.

[0029] The second authorization calculation core is used to perform authorization calculation on the request generated by the second request calculation module to determine the second authorization request.

[0030] In one optional implementation, the scheduling tree control unit includes a tree node request unit; the tree node request unit is used to determine whether a scheduling node has a request based on the node and level of the scheduling node in the scheduling tree, and whether the scheduling node has received a request from a request source or whether the upper-level node of the scheduling node has a request.

[0031] In one optional implementation, the scheduling tree control unit further includes a tree path calculation unit, which is used to: select the scheduling node if the scheduling node sends an authorization request;

[0032] Based on the target path formed by the selected scheduling nodes, the authorization result is selected from the requests received by the leaf nodes in the target path.

[0033] In a second aspect, a computer device is provided, wherein a processor and a memory are provided, and the aforementioned scheduling circuit is deployed in the processor.

[0034] The technical solution provided in this application may include the following beneficial effects:

[0035] The scheduling circuit of this application includes a scheduling tree control unit and a scheduling tree; the nodes in the scheduling tree are used to generate corresponding authorization results according to the received requests; the scheduling tree includes scheduling nodes; the scheduling nodes include a root node at the bottom layer, intermediate nodes at the middle layer, and leaf nodes at the top layer; the root node, intermediate nodes, and leaf nodes each include at least one authorization scheduler; the scheduling nodes are cascaded through the scheduling tree control unit; the leaf nodes are used to receive requests from request sources; the scheduling tree control unit is also used to enable the scheduling nodes to generate requests based on the requests from request sources or after receiving requests from upper-level nodes of the scheduling nodes; the authorization schedulers in the scheduling nodes are used to determine authorization requests from the requests received by the scheduling nodes; and then the scheduling tree control unit is used to select authorization results from the requests from request sources received by the leaf nodes according to the authorization requests of the scheduling nodes. In the above scheme, the scheduling nodes authorize a selected next-level scheduling node containing the request in parallel based on the received request. After receiving the authorization results from all nodes, the scheduling tree control unit merges the authorization results layer by layer from the highest tree root layer to the lowest leaf layer to select a unique source of authorization request, directly filter out the requests to be processed, greatly shorten the task waiting scheduling time, and improve the scheduling efficiency of the scheduling circuit. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0037] Figure 1 A schematic diagram of a typical scheduler is shown.

[0038] Figure 2 A schematic diagram of a traditional cascaded scheduler is shown.

[0039] Figure 3 This is a schematic diagram of a scheduling circuit according to an embodiment of this application.

[0040] Figure 4 A scheduling tree working logic diagram according to an embodiment of this application is shown.

[0041] Figure 5 A logical diagram illustrating a branch selection method according to an embodiment of this application is shown.

[0042] Figure 6 A schematic diagram of a dual-authorization scheduler according to an embodiment of this application is shown.

[0043] Figure 7 The diagram illustrates the execution logic of a dual-authorization scheduler according to an embodiment of this application.

[0044] Figure 8 A logical schematic diagram of a scheduling tree control unit according to an embodiment of this application is shown.

[0045] Figure 9 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of this application. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0047] In the description of the embodiments of this application, the term "correspondence" may indicate that there is a direct or indirect correspondence between two things, or that there is an association between two things, or that there is a relationship of instruction and being instructed, configuration and being configured, etc.

[0048] Figure 1 A schematic diagram of a typical scheduler is shown. Figure 1 As shown, a typical scheduler generally consists of the following four units:

[0049] The scheduling algorithm unit's main responsibility is to perform a series of post-processing operations on the input requests based on the selected scheduling algorithm. Through processes such as filtering, organizing, and transforming requests, it accurately identifies the valid requests that can truly participate in the actual scheduling process, thereby providing a reliable and accurate source of request data for subsequent scheduling operations.

[0050] Request control: Its main responsibility is to perform a series of post-processing operations on the input requests based on the selected scheduling algorithm. Through processes such as filtering, sorting, and transforming requests, it accurately identifies the valid requests that can actually participate in the actual scheduling process, thereby providing a reliable and accurate source of request data for subsequent scheduling operations.

[0051] Authorization Algorithm Core: This unit focuses on performing detailed calculations on requests requiring authorization. Based on the valid requests determined by the preceding units and the corresponding scheduling algorithm rules, it uses a complex calculation process to determine which requests should be authorized, ensuring that tasks are allocated to the appropriate resources in an orderly manner according to the established scheduling strategy, thus guaranteeing the efficient operation of the entire system.

[0052] Authorization Status Control: Its main functions include comprehensive recording and management of the results generated by the internal authorization algorithm core, as well as receiving control commands from external sources. Recording the results provides historical data for subsequent authorization operations, enabling better adjustment and optimization of scheduling strategies. Receiving external control commands allows this unit to flexibly adjust the operating parameters of the authorization algorithm and obtain current authorization status information within a more macroscopic system control framework, thereby achieving precise control and real-time monitoring of the entire authorization scheduling process.

[0053] However, since a single scheduler can only schedule requests in one dimension, in more complex application scenarios, multi-level scheduler cascading is usually used to schedule requests in multiple dimensions. Figure 2 A schematic diagram of a traditional cascaded scheduler is shown. Figure 2 As shown, the scheduler is divided into multiple layers. The bottom-level scheduler directly receives the request source. Then, each scheduler performs authorization calculations on the received request source using an authorization algorithm. Each scheduler selects a potentially authorizable request source and uploads it to the upper-level scheduler connected to it. Similarly, the upper-level scheduler also performs authorization calculations on the received request source using an authorization algorithm, and so on. Finally, the top-level scheduler obtains a final authorization result and authorizes the request corresponding to that result.

[0054] Because multiple schedulers are cascaded, the complexity of the circuit is affected by the number of cascaded stages and the number of request sources. Therefore, when summarizing the responsible authorization circuits, it is often necessary to use registers to cache the intermediate budget states. As a result, it takes multiple processing clock cycles to obtain the authorization value, which leads to a large computational delay and a significant consumption of register storage resources.

[0055] To address the aforementioned issues, this application provides a scheduling circuit. Figure 3 This is a schematic diagram of a scheduling circuit according to an embodiment of this application, such as... Figure 3 As shown, the scheduling circuit includes a scheduling tree control unit and a scheduling tree;

[0056] The scheduling tree includes scheduling nodes; each scheduling node includes a root node at the bottom layer, intermediate nodes in the middle layer, and leaf nodes at the top layer; each of the root node, intermediate nodes, and leaf nodes includes at least one authorized scheduler; the scheduling nodes are cascaded through scheduling tree control units; the leaf nodes are used to receive requests from request sources.

[0057] The scheduling tree control unit is used to enable the scheduling node to generate a request based on the request from the request source or after receiving a request from the upper-level node of the scheduling node; the authorizing scheduler in the scheduling node is used to determine the authorizing request from the requests received by the scheduling node; the scheduling node is one of the scheduling nodes.

[0058] The scheduling tree control unit is used to select an authorization result from the requests received by the request source in the leaf node, based on the authorization request of the scheduling node.

[0059] like Figure 3 As shown, the root node of the scheduling tree manages the requests of the intermediate nodes cascaded with the root node through the scheduling tree control unit; the intermediate nodes are used to manage the requests of the leaf nodes cascaded with the intermediate node through the scheduling tree control unit.

[0060] For the highest-level leaf nodes, each node is an authorization scheduler (in this embodiment, the authorization scheduler can be a single authorization scheduler; preferably, in this embodiment, the authorization scheduler can also be a dual authorization calculation scheduler to further improve authorization calculation efficiency). Each leaf node at the highest level can receive multiple request sources and calculate the authorization result for each request source according to the authorization algorithm, selecting one of the multiple request sources received as the authorization result calculated by the leaf node.

[0061] Unlike traditional serial authorization scheduling schemes, the authorization results in this embodiment are not directly transmitted through the scheduling tree. Instead, each scheduling node sends its authorization result to the scheduling tree control unit after obtaining its own. In other words, the authorization calculation of lower-level scheduling nodes does not depend on the authorization results of upper-level nodes. In this embodiment, the scheduling nodes at both the left and right levels use parallel computation to simultaneously determine whether a requesting branch can be authorized. For a requesting scheduling node, it can always authorize one of the request sources. Finally, all request authorization results are processed in parallel by the scheduling tree control unit, which uses a unique root node to a leaf node to obtain a unique request authorization from the bottom to the top level.

[0062] Optionally, the authorization scheduler in each scheduling node is used to select authorization requests from the requests received by that scheduling node; the scheduling tree control unit is also used to merge the nodes corresponding to all authorization requests into a target path from the bottom layer to the top layer after receiving authorization requests from each scheduling node, and select authorization results from the requests received by the leaf nodes in the target path.

[0063] In this embodiment, each layer of the authorization scheduler is used to authorize a node containing a request that is managed by the layer above the authorization scheduler. After the scheduling tree control unit receives the authorization results from all layers of the authorization scheduler, it merges all authorization branches from the bottom layer to the top layer to obtain a unique authorization request source.

[0064] In other words, when the scheduling tree control unit receives the authorization result from each scheduling node, it determines the selected upper-level scheduling node based on the authorization result from the root node, i.e., the bottom level; and searches for authorization layer by layer to the next higher level, finally finding the unique authorized request source in the highest-level leaf node.

[0065] To further illustrate the technical solution of this application, Figure 4 A scheduling tree working logic diagram according to an embodiment of this application is shown. Figure 4 Each box in the table below represents a scheduling node. A number of 1 in the box indicates that the scheduling node has received a request. (If the scheduling node is a leaf node at the top level, it receives an external request. A leaf node receives an external request and its value is 1. If the scheduling node is an intermediate node at the middle level or the root node at the bottom level, it receives a request from a higher-level node. For example, if any of the nodes under the intermediate node receives a request, its value is 1. The request is then generated and uploaded to the higher-level node.)

[0066] After determining whether each scheduling node has received a request, since there is an authorization scheduler in the scheduling node, the authorization scheduler can perform authorization scheduling (that is, select one of the multiple received requests). For example, 1 in the first column on the right in the table below means that the node has received a request. The authorization scheduler can be used to determine the authorization of the requests generated by the two nodes below it. At this time, the authorization scheduler can determine the authorization of the request of the node above, and thus record the authorization request, resulting in 1 in the second column on the right in the table above.

[0067] Then, following the logic above, the requests received by each node were judged in turn, resulting in the table above. Based on the authorization result, the nodes with a value of 1 were selected from the bottom nodes to the top nodes in turn. Finally, the external requests received by the leaf nodes were obtained, which is the authorization result.

[0068] Furthermore, in this embodiment of the application, each node in the scheduling tree is a dual-authorization computation scheduler; the dual-authorization computation scheduler is used to generate a first authorization request and a second authorization request based on the input request; the second authorization request is generated after excluding the first authorization request.

[0069] Figure 5 A logical diagram illustrating a branch selection method according to an embodiment of this application is shown. Figure 5 The scenario of multiple schedulers cascading is abstracted into a tree structure. The dual-authorization computing unit of this invention is equivalent to... Figure 5 The circular nodes at different levels of the tree network can derive two gating branches based on the current input and historical state of the tree network: the 'current gating branch' and the 'next gating branch'. The scheduling tree control unit is equivalent to the control unit that controls the tree's state updates and gating. It can complete the construction of a unique path from the root node to the leaf node. When the path is requested and selected, the tree state can be updated. It can also update the tree state when the path is not selected.

[0070] Furthermore, in this embodiment, each node completes its own state calculation using a feedback path. This transforms the process of solving path branches through serial computation into a parallel process of finding a unique solution for all paths. This reduces the number of implementation stages in the combinational circuit. Moreover, when the input request is in a stable state, the time required for parallel computation between nodes is not needed; the result can be quickly solved and output using the next gating branch.

[0071] Furthermore, in this embodiment, the dual-authorization computation scheduler can also generate two authorization results based on the received request. The dual-authorization computation scheduler includes a first authorization computation core, a second authorization computation core, and an authorization status control module. The first authorization computation core is used to perform authorization computation on the received request according to the authorization algorithm to determine the first authorization request. The second authorization computation core is used to confirm the first authorization request in the received request and then perform authorization computation according to the authorization algorithm to determine the second authorization request. The authorization status control module is used to record the first authorization request and the second authorization request and send the recording result to the scheduling tree control unit.

[0072] Figure 6 A schematic diagram of a dual-authorization scheduler according to an embodiment of this application is shown. This dual-authorization scheduler is the aforementioned dual-authorization scheduling calculation unit. Figure 6As shown, the dual-authorization scheduler still performs dual-authorization calculations based on the traditional scheduler. In this dual-authorization scheduler, the dual-authorization calculation cores (i.e., the first authorization calculation core and the second authorization calculation core) operate based on the single authorization algorithm core. The specific process is as follows: first, the result of the first authorization is masked; then, the processed result and the request are entered together into the second authorization calculation stage. After these two rounds of calculation, the authorization status information of the first authorization and the authorization status information of the second authorization can be obtained, thus providing richer data for subsequent scheduling decisions.

[0073] The authorization status control module functions similarly to the authorization status control in traditional schedulers. It records the results generated by the internal authorization algorithm cores during the two rounds and also receives control commands from external sources. Recording the results allows for the accumulation of scheduling data from multiple rounds, providing a reference for optimizing scheduling strategies. Receiving external control commands enables this unit to flexibly adjust the relevant parameters of the authorization algorithm based on the overall system operation and requirements, and accurately obtain the current authorization status, ensuring the stability and efficiency of the entire dual-authorization scheduling process.

[0074] Furthermore, unlike traditional schedulers that only obtain a single authorization request after authorizing the computational core, the dual-authorization scheduler obtains two authorization states. These two states are then further transmitted to the scheduling tree control unit. Based on these two authorization states, and combined with its own state control and feedback mechanisms, the scheduling tree control unit can select the most suitable scheduling branch from among many branches, thereby optimizing resource allocation and improving task processing efficiency throughout the cascaded scheduling system.

[0075] Figure 7 A schematic diagram illustrating the execution logic of a dual-authorization scheduler according to an embodiment of this application is shown. Figure 7 As shown, the dual-authorization scheduler also includes a request control module and a status register; the request control module is used to process the requests of each currently accessing request source, close requests without permission, and obtain valid request sources; the first authorization calculation core is used to perform authorization calculation based on the valid request sources processed by the authorization algorithm to determine the first authorization request; the status register is used to store the first authorization request.

[0076] Furthermore, the dual-authorization scheduler also includes a mask calculation module and a second request calculation module; the mask calculation module is used to generate an upper mask and a lower mask based on the first authorization request;

[0077] The upper mask is located above the last authorized position in the authorization schedule, and its high-level bit is high. This high-level area is the part to be masked. The lower mask is the inverse of the upper mask.

[0078] The second request calculation module is used to perform an AND operation between the received request and the upper or lower mask to generate a request that masks the first authorization request.

[0079] The second authorization calculation core is used to perform authorization calculations on the request generated by the second request calculation module to determine the second authorization request.

[0080] Specifically, the following are examples of such cases. Figure 6 The internal logic of the scheduler shown will be explained in detail below:

[0081] The scheduler has an internal status recording function. When there are no requests, its status is reset to 0. If there is a request and the scheduler has not yet authorized it, it means that the final authorization result has not yet been determined. At this time, the scheduler's next authorization status needs to be recorded. This status can be regarded as the initial status flag for the start of scheduling work. When the scheduler has been authorized, its current authorization status needs to be recorded. This corresponds to the output of the first authorization in the diagram, indicating that the scheduler has started operating normally.

[0082] The current authorization state here is the output of the first authorization in the diagram. It represents the authorization result determined by the initial calculation for the current request and is directly used to drive subsequent resource allocation and system scheduling. The next authorization state is the output of the second authorization in the diagram. It represents the candidate authorization result selected from the remaining requests after the already authorized request is blocked. If there is only one request, the same request will be authorized twice. The purpose of recording this state is to ensure that the system can seamlessly and continuously perform the next round of scheduling after the current authorization is completed, thus ensuring low latency and high responsiveness when the system is working continuously.

[0083] The authorization status here is stored in the status register;

[0084] Mask calculation: Two masks can be generated. The upper mask is located above the last authorized position in the authorization schedule, with its high-level bits being high. This high-level area is the part that needs to be masked. The lower mask is the inverse of the upper mask.

[0085] Request control: responsible for closing requests that do not have the necessary permissions after the request algorithm has processed them;

[0086] Request Algorithm: The request algorithm is compatible with various authorization-based algorithm types such as SP fixed priority, RR fair algorithm, DRR differential circular queue algorithm, WRR weighted circular scheduling algorithm, and WDRR weighted differential circular algorithm;

[0087] The first authorization algorithm core's task is to perform a calculation between the request and the previous mask to determine the position of the current scheduling request;

[0088] Second request calculation: After taking the request mask corresponding to the first authorization bit, obtain the new request source. If there is only one request, then authorize the same request twice.

[0089] The second authorization algorithm core: performs a mask operation on the new request source and the previous one to obtain the position of the next scheduling request.

[0090] The aforementioned dual-authorization scheduler design ensures that the scheduler monitors request status in real time and clearly distinguishes between the currently authorized and pre-authorization states, maintaining continuous system operation and low-latency response. By generating upper and lower masks, it masks authorized requests and filters remaining requests, ensuring that each authorization operation only operates on legitimate requests. Furthermore, through the collaborative work of the first and second authorization algorithm kernels, it quickly outputs the current authorization result and pre-calculates the candidate requests for the next round, achieving seamless integration of continuous authorization and scheduling processes. This improves response speed while reducing logical complexity and resource consumption, enabling stable and efficient operation in high-concurrency scenarios.

[0091] Figure 8 A logical schematic diagram of a scheduling tree control unit according to an embodiment of this application is shown. Figure 8 As shown, the scheduling tree control unit includes a tree node request unit; the tree node request unit is used to determine whether the scheduling node has a request based on the nodes and levels in the tree structure, and whether the scheduling node has received a request from the request source or whether the upper-level node of the scheduling node has a request.

[0092] Optional, such as Figure 8 As shown, the scheduling tree control unit also includes a branch path calculation unit, which is used to select the scheduling node if the scheduling node sends an authorization request; and select the authorization result from the requests received by the request sources in the leaf nodes of the target path according to the target path formed by the selected scheduling nodes.

[0093] Specifically, the following are examples of such cases. Figure 6 The internal logic of the scheduling tree control unit shown is explained in detail below:

[0094] Branch node request unit: Based on whether there is a request in the leaf nodes linked under this node, it determines whether there is a request in the corresponding branch of this node, and then obtains the request signals of all nodes.

[0095] Next Node State Refresh: This is mainly used to calculate and store the next authorization state reported by each node. When a node has no request, its state should be cleared to zero; if a node has not been authorized, it indicates that the node is in the initial working state, and the next authorization state reported by the node needs to be recorded; when a node has authorized feedback, the current state reported by the node needs to be recorded, which means that the entire tree network has entered a continuous working state.

[0096] Node Current State Refresh: Responsible for calculating and storing the current authorization state reported by each node. When a node has no request, its state should be cleared to zero; if a node is not authorized, i.e., in the initial working state, the current authorization state reported by the node should be recorded; when a node reports authorization, the value recorded for the next state refresh should be recorded, indicating that the entire tree network has entered a continuous working process; or when a node's request matches the recorded state and it is found that the node cannot be continuously scheduled, the state corresponding to this node should also be refreshed and recorded with the latest value reported by the node.

[0097] Branch Path Calculation Unit: This unit matches the current value returned by the node or the recorded current value with the node's request. If both values ​​are 1 (valid), it means that the branch has been selected. Finally, based on the request status from the root node to all leaf nodes, if a unique path is selected, then the request corresponding to that leaf node is the pre-authorized request.

[0098] Authorization request output: If the request matches the only pre-authorized request, it means that the request can be quickly authorized; if they do not match, the internal node will continue to update until the returned pre-authorization request matches the current request.

[0099] Tree node feedback unit: When a request is authorized for output, the selected nodes in the tree structure need to be updated in one round.

[0100] In the aforementioned scheduling tree processing unit, the entire tree-structured scheduling mechanism employs a hierarchical state update and feedback strategy. From the aggregation of requests at leaf nodes and the state update of each internal node, to the matching and pre-authorization of the entire path, and finally to the authorization output and feedback update, all modules work closely together. The next state update and current state update modules ensure that each node can instantly reflect its eligibility to participate in scheduling and its previous and current states, providing a foundation for accurate path calculation. The branch path calculation unit matches each node's state with its requests. When only one path meets the conditions, a pre-authorization request is triggered, and then the authorization output module completes the rapid authorization. The tree node feedback unit updates the state of the entire tree after authorization, ensuring that the system remains up-to-date with continuous scheduling requests, thereby achieving low latency and high-efficiency scheduling response.

[0101] In summary, the scheduling circuit of this application includes a scheduling tree control unit and a scheduling tree; the nodes in the scheduling tree are used to generate corresponding authorization results based on the received requests; the scheduling tree includes scheduling nodes; each scheduling node includes a root node at the bottom layer, intermediate nodes at the middle layer, and leaf nodes at the top layer; the root node, intermediate nodes, and leaf nodes each include at least one authorization scheduler; the scheduling nodes are cascaded through the scheduling tree control unit; the leaf nodes are used to receive requests from request sources; the scheduling tree control unit is also used to enable the scheduling nodes to generate requests based on requests from request sources or requests received from upper-level nodes of the scheduling nodes; the authorization schedulers in the scheduling nodes are used to determine authorization requests from the requests received by the scheduling nodes; and then the scheduling tree control unit is used to select authorization results from the requests from request sources received by the leaf nodes based on the authorization requests of the scheduling nodes. In the above scheme, the scheduling nodes authorize a selected next-level scheduling node containing the request in parallel based on the received request. After receiving the authorization results from all nodes, the scheduling tree control unit merges the authorization results layer by layer from the highest tree root layer to the lowest leaf layer to select a unique source of authorization request, directly filter out the requests to be processed, greatly shorten the task waiting scheduling time, and improve the scheduling efficiency of the scheduling circuit.

[0102] Each unit in the scheduling circuit in this embodiment can be presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0103] This application also provides a computer device that may include the scheduling circuit shown in the embodiments of this application to schedule various requests that the computer device needs to execute. Please refer to... Figure 9 , Figure 9 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of this application, such as... Figure 9As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information in a graphical user interface on an external input / output device (such as a display device coupled to the interface). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 9 Take a processor 10 as an example.

[0104] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0105] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0106] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0107] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0108] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0109] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A scheduling circuit, characterized in that, The scheduling circuit includes a scheduling tree control unit and a scheduling tree; The scheduling tree includes scheduling nodes; The scheduling node includes a root node at the bottom layer, intermediate nodes in the middle layer, and leaf nodes at the top layer; each of the root node, intermediate nodes, and leaf nodes includes at least one authorized scheduler. The scheduling nodes are cascaded through scheduling tree control units; the leaf nodes are used to receive requests from request sources. The scheduling tree control unit is used to enable the scheduling node to generate the request of the scheduling node based on the request from the request source, or after receiving the request from the upper-level node of the scheduling node. The authorization scheduler in the scheduling node is used to determine the authorization request from the requests received by the scheduling node; The scheduling tree control unit is used to select an authorization result from the requests received by the request source in the leaf node according to the authorization request of the scheduling node.

2. The scheduling circuit according to claim 1, characterized in that, The root node of the scheduling tree manages the requests of intermediate nodes cascaded with the root node through the scheduling tree control unit; the intermediate nodes manage the requests of leaf nodes cascaded with the intermediate nodes through the scheduling tree control unit.

3. The scheduling circuit according to claim 2, characterized in that, The authorization scheduler in each scheduling node is used to select authorization requests from the requests received by the scheduling node; The scheduling tree control unit is also used to merge the nodes corresponding to all authorization requests into a target path from the bottom layer to the top layer after receiving authorization requests from each scheduling node, and select the authorization result from the requests received by the leaf nodes in the target path.

4. The scheduling circuit according to any one of claims 1 to 3, characterized in that, Each scheduling node includes a dual-authorization computation scheduler; the dual-authorization computation scheduler is used to generate a first authorization request and a second authorization request based on the input request; the second authorization request is generated after excluding the first authorization request.

5. The scheduling circuit according to claim 4, characterized in that, The dual-authorization computing scheduler includes a first authorized computing core, a second authorized computing core, and an authorization status control module; The first authorization calculation core is used to perform authorization calculation on the received request according to the authorization algorithm to determine the first authorization request; The second authorization calculation core is used to confirm the first authorization request in the received request, and then perform authorization calculation through the authorization algorithm to determine the second authorization request; The authorization status control module is used to record the first authorization request and the second authorization request, and send the recording results to the scheduling tree control unit.

6. The scheduling circuit according to claim 5, characterized in that, The dual-authorization computing scheduler also includes a request control module and a status register; The request control module is used to process the currently accessed requests, close requests without permission, and obtain valid requests. The first authorization calculation core is used to perform authorization calculation based on the valid request processed by the authorization algorithm, so as to determine the first authorization request; The status register is used to store the first authorization request.

7. The scheduling circuit according to claim 6, characterized in that, The dual-authorization computation scheduler also includes a mask calculation module and a second request calculation module; The mask calculation module is used to generate an upper mask and a lower mask based on the first authorization request; the upper mask is located above the previous authorization position in the authorization schedule, and its high-level bits are high, with the high-level region being the part to be masked; the lower mask is the inverse of the upper mask; The second request calculation module is used to perform an AND operation between the received request and the upper or lower mask to generate a request that masks the first authorization request. The second authorization calculation core is used to perform authorization calculation on the request generated by the second request calculation module to determine the second authorization request.

8. The scheduling circuit according to any one of claims 1 to 3, characterized in that, The scheduling tree control unit includes a tree node request unit; the tree node request unit is used to determine whether a scheduling node has a request based on the node and level of the scheduling node in the scheduling tree, and whether the scheduling node has received a request from a request source or whether the upper-level node of the scheduling node has a request.

9. The scheduling circuit according to claim 8, characterized in that, The scheduling tree control unit also includes a tree branch path calculation unit, which is used to: select the scheduling node if the scheduling node sends an authorization request; Based on the target path formed by the selected scheduling nodes, the authorization result is selected from the requests received by the leaf nodes in the target path.

10. A computer device, characterized in that, The computer device includes a processor and a memory, and the processor is equipped with a scheduling circuit as described in any one of claims 1 to 9.

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