CPU dynamic power distribution method for improving system throughput

Abstract

The invention discloses a CPU (Central Processing Unit) dynamic power distribution method for improving system throughput, which comprises the following steps of: S1, acquiring real-time performance monitoring counter data of each CPU core, and obtaining the current load characteristic composition performance bottleneck risk degree of each core; s2, constructing a load risk prediction model to predict the performance bottleneck risk degree to obtain a risk trend factor, collecting basic power budget data of each CPU core, obtaining an optimal temporary power budget in combination with the risk trend factor, and outputting a prospective power budget bias strategy based on the optimal temporary power budget; s3, performing power consumption modeling based on a power budget bias strategy and the constitution factors of the chip to construct an optimal V-f mapping table; s4, based on the optimal V-f mapping, V-f parameters are issued through a CPU power management interface, closed-loop feedback is formed, CPU dynamic power distribution is achieved, and dynamic power distribution of the CPU is achieved.

Description

Technical Field

[0001] This invention relates to the field of power distribution technology, and in particular to a CPU dynamic power distribution method to improve system throughput. Background Technology

[0002] With the continuous development of computer technology, the contradiction between CPU performance requirements and power consumption control has become increasingly prominent. In the early days, CPU voltage and frequency were mostly statically configured, that is, fixed according to design specifications. Although this method was simple, it could not be dynamically adjusted according to the actual load, resulting in wasted performance or power consumption. Later, adjustment methods based on static power budgets emerged, which roughly divided the Vf combination of each core through a pre-set power budget, but did not take into account the process deviations in chip manufacturing, that is, the differences in chip quality.

[0003] Currently, existing CPU dynamic power allocation methods lack consideration for chip quality when generating power budget bias strategies. Under the same power budget, cores with poor quality may not be able to operate stably at high frequencies due to insufficient power budget, leading to performance bottlenecks or instability. On the other hand, when constructing voltage-frequency mapping tables, a uniform relational model is often used, ignoring the differences in individual core quality. This results in the generated voltage-frequency combination not being the optimal choice for each core. Either the power consumption is too high, exceeding the budget, or the performance is not optimal, making it impossible to maximize performance under power budget constraints. Therefore, this paper proposes a CPU dynamic power allocation method to improve system throughput. Summary of the Invention

[0004] In order to overcome the above-mentioned defects of the prior art and to achieve the above objectives, the present invention proposes the following technical solution: A method for dynamic CPU power allocation to improve system throughput includes: S1: Collect real-time performance monitoring counter data for each CPU core to obtain the current performance bottleneck risk level of each core's responsible features. S2: Construct a load risk prediction model to predict the risk level of performance bottlenecks and obtain risk trend factors. Collect basic power budget data for each CPU core and combine it with risk trend factors to obtain the optimal temporary power budget. Output a forward-looking power budget bias strategy based on the optimal temporary power budget. The load risk prediction model includes a feature embedding layer, a temporal attention layer, a load risk fusion layer, and a prediction output layer. The performance bottleneck risk level is input through the feature embedding layer, and the risk trend factor is output through the prediction output layer. S3: Construct the optimal Vf mapping table by modeling power consumption based on the power budget bias strategy and the chip's quality factor; S4: Based on the optimal Vf mapping, Vf parameters are sent through the CPU power management interface and a closed-loop feedback is formed to realize the dynamic power allocation of the CPU.

[0005] The feature embedding layer maps the three types of load features—computation-type PMC, memory-type PMC, and instruction-type PMC—into a unified feature space and embeds them through a fully connected layer to obtain the memory-type feature embedding vector E. The temporal attention layer predicts the future risk of the current load based on the importance of different load characteristics, which are load characteristics at different times. Assign weights to obtain the temporal attention output vector. ,in, The dimension of the key vector. For querying the matrix, The key matrix, It is a value matrix; The load risk fusion layer is based on the temporal attention output vector corresponding to different load characteristics. For load characteristics respectively Temporal attention output vector The gating weights are calculated by multiplying each feature embedding vector element-wise with its corresponding gating weight, and then summing the results to obtain the fused risk feature vector. ; The prediction output layer is based on the fused risk feature vector. Predict the risk level of performance bottlenecks at future moments: , This indicates a fully connected layer.

[0006] The process for obtaining the risk trend factors is as follows: Risk of performance bottlenecks in future moments The risk trend factor is obtained by comparing it with the current performance bottleneck risk level: ,in, The load is predicted to increase. Predict load decreases during a downturn.

[0007] The process of obtaining the optimal temporary electricity budget by combining risk trend factors is as follows: According to the basic electricity budget Calculate the risk compensation bias by combining risk trend factors. Then, the optimal temporary power budget is obtained based on the risk compensation bias: ,in, For the optimal temporary electricity budget, This is the risk compensation coefficient.

[0008] The process of the forward-looking power budget bias strategy based on the optimal temporary power budget output is as follows: Optimal temporary power budget for all CPU cores Perform global constraints and adjustments, and calculate the sum of all core temporary power budgets. and compare it with the system's total power budget. When comparing, This proves that the initial power distribution scheme exceeds the system's power consumption limit and needs adjustment. At this point, the scaling factor is calculated. ; Then, based on the scaling factor Risk compensation bias for each CPU core After optimization and adjustment, the adjusted bias is expressed as follows: Ultimately, the CPU core's power budget bias strategy is expressed as: ; Finally, the number of each CPU core is associated with its corresponding power budget bias strategy. Organize the data into a mapping table to obtain a forward-looking electricity budget bias strategy.

[0009] The process of obtaining the body constitution factor of the chip is as follows: The chip is quantitatively characterized, and the minimum voltage at which the core can operate stably at the current frequency is recorded, denoted as . where i is the index number. For test frequency, based on test frequency Obtain CPU core frequency lower body constitution factors The calculation formula is: ,in, For test frequency The lowest average stable voltage.

[0010] The process of power consumption modeling based on the power budget bias strategy and the chip's quality factor is as follows: The power consumption rule for the stable voltage V is defined based on the chip's quality factor: ; Will By substituting the power consumption formula into the model, and iterating through different test frequencies f, the corresponding power consumption is calculated. The model is completed by finding the highest frequency at which power consumption is less than or equal to the power budget, thus achieving the goal of maximizing performance within the power budget. The formula is expressed as: ; Where k is a constant related to the CPU architecture, and C is the core's equivalent capacitance.

[0011] The process of constructing the optimal Vf mapping table is as follows: Set the scan interval of the test frequency as ,in This is the lowest operating frequency supported by the CPU. It is the highest operating frequency designed for the CPU; Traverse the scan interval and calculate power consumption, starting from the highest frequency. Start by iterating down to lower frequencies. For each frequency, determine the CPU core's quality factor. and the average minimum stable voltage of the same model Calculate the stable minimum voltage at this frequency = Then, by substituting the power consumption modeling formula, the CPU cores at different test frequencies are obtained. Power consumption ; Determine different test frequencies Power consumption Is it less than or equal to the power budget of the CPU core? Find the first one that satisfies The optimal frequency is denoted as The corresponding minimum stable voltage at this time is Obtain the stable minimum voltage for each CPU core. All core Organized into core numbers and By combining the mapping tables, the optimal Vf mapping table is obtained.

[0012] The present invention has the following beneficial effects: In this invention, firstly, a power budget bias strategy for risk compensation is implemented based on the performance bottleneck risk level. For cores with high risk levels, it means that their current workload is heavy and they need more power resources to maintain efficient operation. The power budget bias strategy will proactively allocate more power budget to these cores, enabling them to work at a higher performance level. For example, when a core is processing a complex computing task, due to the increase in power budget, it can complete integer operations, floating-point operations, etc., more quickly, reducing the processing time of computing tasks, thereby improving the computing power of a single core and promoting the overall improvement of CPU throughput, enabling the CPU to process more computing tasks per unit time. Finally, by constructing an optimal Vf mapping table, fully considering the chip's inherent characteristics, and combining it with a power budget bias strategy, the optimal Vf combination under its power budget constraint is found for each core. For cores with better inherent characteristics, they can stably operate at higher frequencies at lower voltages. For cores with relatively poor inherent characteristics, a Vf combination that satisfies their stable operation and maximizes performance can also be found, enabling the CPU to process more data and tasks in the same amount of time. At the same time, once a change in the operating state of a core is detected, such as an increase in the risk of a performance bottleneck or an actual power consumption exceeding the budget, the risk of the performance bottleneck will be reassessed, the power budget bias strategy will be adjusted, and the Vf mapping table and dynamically set instructions will be optimized. This will prevent performance degradation due to load fluctuations and maintain efficient operation at all times, thereby continuously ensuring and improving the CPU's throughput. This allows the CPU to stably handle a large number of tasks and meet the needs of complex application scenarios. Attached Figure Description

[0013] Figure 1 This is a flowchart illustrating the steps of a CPU dynamic power allocation method for improving system throughput proposed in this invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Example: Figure 1 As shown, the present invention proposes a CPU dynamic power allocation method to improve system throughput, comprising: S1: Collect real-time performance monitoring counter data for each CPU core to obtain the current performance bottleneck risk level of each core's responsible features. Collect and quantify the PMC data from the performance monitoring counters in the CPU core to determine load characteristics, including: Computational PMC: This category reflects the pressure on the core computing unit, such as the utilization rate of integer arithmetic units and the latency of floating-point operations. Memory access-related PMCs reflect the impact of memory access on computation, such as L1 cache miss rate and memory access wait time. Instruction-related PMCs are related to the smoothness of the instruction flow, such as the period of instruction out-of-order execution stalls and the number of branch prediction failures. Load characteristics are represented as , This represents the calculation class PMC. This indicates a memory access class PMC. Indicates the instruction class PMC; The collected computational PMC, memory access PMC, and instruction PMC parameters are preprocessed. Sub-items of each PMC parameter are normalized to convert PMC parameters with different dimensions into comparable values. Then, based on the different degrees of impact of each sub-item on the computational bottleneck, corresponding weights are assigned. Finally, these normalized sub-item values ​​are weighted and summed to obtain the performance bottleneck risk level, expressed by the formula: ,in, Indicates the risk level of performance bottlenecks. For the corresponding weights.

[0016] S2: Construct a load risk prediction model to predict the risk level of performance bottlenecks and obtain risk trend factors. Collect basic power budget data for each CPU core and combine it with risk trend factors to obtain the optimal temporary power budget. Output a forward-looking power budget bias strategy based on the optimal temporary power budget. Based on historical load characteristics The load risk prediction model is constructed to predict the risk level of future performance bottlenecks. The implementation process is as follows: To accurately capture the complex relationship between load characteristics and future risk levels, a load risk prediction model is designed to integrate three types of load characteristics: computational PMC, memory access PMC, and instruction PMC, and to mine time-series dependencies to predict the risk level of future performance bottlenecks. The load risk prediction model includes a feature embedding layer, a temporal attention layer, a load risk fusion layer, and a prediction output layer, wherein: The feature embedding layer maps the three types of load features—computation-type PMC, memory-type PMC, and instruction-type PMC—into a unified feature space and embeds them through a fully connected layer to obtain the memory-type feature embedding vector E. Temporal attention layer is based on load characteristics at different times. The importance of predicting future risk based on current load, and load characteristics at different times. Assign appropriate weights, assuming the time series has a length of t, and consider the load characteristics over the last t sampling periods. , load characteristics Respectively with the query weight matrix Key weight matrix Value weight matrix Multiply to obtain the query matrix Key matrix Value matrix ; Then, calculate the product of the query matrix and the transpose of the key matrix, and divide by the dimension of the key vector. The square root of the matrix is ​​used (this step is to prevent the softmax gradient from vanishing due to an excessively large inner product), and then the attention weights are obtained through the softmax function. Finally, the attention weights are multiplied by the value matrix to obtain the temporal attention output vector. In this way, the network can automatically identify which moments in the time series characteristics are more critical for predicting future risk and thus assign them higher weights. The load risk fusion layer outputs temporal attention vectors based on different load characteristics. For load characteristics respectively Temporal attention output vector Gating weights are calculated, and load characteristics are processed through a fully connected layer (FC). And after passing through the Sigmoid activation function The gating weights of the instruction features are obtained: Simultaneously, obtain the gating weights of the memory access feature vector: E is the memory access feature embedding vector, and the gating weights of the temporal attention output vector are: ; The load risk fusion layer multiplies each feature embedding vector element-wise with its corresponding gating weight, and then adds them together to obtain the fused risk feature vector. ; The prediction output layer is based on the fused risk feature vector. Predict the risk level of performance bottlenecks at future moments: , Indicates a fully connected layer; The training objective is determined based on the load risk prediction model to minimize the performance bottleneck risk at future time points compared to the actual performance bottleneck risk. An optimizer is selected for training, using the stochastic gradient descent Adam optimizer to continuously adjust the load risk prediction model and learn the correlation pattern between load characteristics and future risk levels. After training, for any input load characteristics... Load risk prediction models can all output the predicted risk level of future performance bottlenecks. ; A risk trend factor is obtained by comparing the risk level of future performance bottlenecks with the risk level of current performance bottlenecks. ,Right now Predicting an increase in load can amplify the risk of performance bottlenecks. Predict load decreases during periods of decline to reduce the risk of performance bottlenecks; Define the base power budget for each CPU core. The power consumption is determined directly by the average power consumption during the core's historical operation. This is achieved by collecting power consumption data of the core under different workloads over a period of time, performing statistical analysis, and then obtaining the average power consumption value, which serves as the basis for the power budget. ; The optimal temporary electricity budget is obtained by combining risk trend factors, and the process is as follows: According to the basic electricity budget Calculate the risk compensation bias by combining risk trend factors. Then, the optimal temporary power budget is obtained based on the risk compensation bias: ,in, For the optimal temporary electricity budget, This is the risk compensation coefficient; Specifically, risk compensation coefficient The determination process is as follows: Apply different performance pressures to the CPU cores under different workload scenarios, and then adjust... The value of the observation core is different risk compensation coefficients. Performance under different risk compensation coefficients, such as task execution time, instruction throughput, and power consumption, is compared. Find the optimal value that balances bottleneck mitigation and power consumption constraints, based on the corresponding performance improvement and power consumption increase, and determine the risk compensation coefficient. Then, consider the performance bottleneck risk level of each core. Based on the basic electricity budget P, calculate the risk compensation bias of this core. ; Then, based on the optimal temporary electricity budget, a forward-looking electricity budget bias strategy is output, the process of which is as follows: Optimal temporary power budget for all cores Perform global constraints and adjustments, and calculate the sum of all core temporary power budgets. and compare it with the system's total power budget. When comparing, This proves that the initial power distribution scheme exceeds the system's power consumption limit and needs adjustment. At this point, the scaling factor is calculated. ; Then, based on the scaling factor Risk compensation bias for each CPU core After optimization and adjustment, the adjusted bias is expressed as follows: Ultimately, the CPU core's power budget bias strategy is expressed as: ; Finally, the number of each CPU core is associated with its corresponding power budget bias strategy. Organize the data into a mapping table to obtain a forward-looking electricity budget bias strategy; Specifically, by introducing a load risk prediction model, this strategy can more accurately match future load changes of the cores, providing a more practical power constraint basis for subsequently building an optimal Vf mapping table that considers the chip's physical characteristics. This achieves a better balance between power resource allocation and performance improvement and power consumption control. For cores facing a high risk of performance bottlenecks, it often means that their current load is heavy and close to performance saturation. To improve the overall system throughput, these cores need more power support to release performance. Through the risk-compensated power budget bias strategy, more power budget can be allocated to high-risk cores in a forward-looking manner, ensuring that these cores have enough power to improve operating efficiency and providing a power foundation for throughput improvement.

[0017] S3: Construct the optimal Vf mapping table by modeling power consumption based on the power budget bias strategy and the chip's quality factor; The process of obtaining the physical factors of the chip is as follows: First, the chip is quantitatively characterized. The chip quality of each core is quantified through offline testing. For each CPU core, the frequency is gradually increased starting from the lowest frequency. At each fixed frequency, the voltage is gradually increased starting from the lowest voltage. The working status of the core is continuously monitored until the CPU core encounters errors or instability (such as frequent hardware anomalies). At this point, record the lowest voltage at which the core can operate stably at the current frequency, and denote it as . where i is the index number. To test the frequency, and define a CPU core at a specific frequency. lower body constitution factors The calculation formula is: ,in, This was achieved by conducting identical offline tests on a large number of cores of the same model, and statistically analyzing the frequency performance of that core model. The average minimum stable voltage under these conditions; like This indicates that the CPU core is at the test frequency. The physical condition of the lower-ranked core is better than the average level of the same model. If the physical condition is below average, it indicates that the physical condition is worse than average. Through the physical condition factor, the voltage requirement characteristics of each core at different frequencies can be accurately characterized, providing a basis for the selection of subsequent Vf (voltage-frequency) combinations. The process of power consumption modeling based on the power budget bias strategy and the chip's quality factor is as follows: The power consumption rule for the stable voltage V is defined by combining the chip's quality factor, that is, the CPU core at the test frequency. For the system to operate stably, the required stable voltage V must meet the following conditions: ; Specifically, It is the CPU core at the test frequency The minimum voltage required for stable operation, in order to maximize core performance within the power budget, i.e., to increase the testing frequency as much as possible. The lowest voltage that meets the stability requirements should be selected, because the lower the voltage, the lower the power consumption, which allows for power reserve for higher frequencies. ; Will Modeling is performed by substituting power consumption rules, and the physical factors are known. When considering the power budget (maximum allowable power consumption), the corresponding power consumption is calculated by iterating through different test frequencies f. This allows us to find the highest frequency where power consumption is less than or equal to the power budget, thus achieving the goal of maximizing performance within the power budget and completing the modeling. The power consumption modeling formula is expressed as: ; Where k is a constant related to the CPU architecture, and C is the equivalent capacitance of the core; Specifically, through Given the core properties and power budget, it can analyze the power consumption at different frequencies, and then find a Vf combination that satisfies power consumption constraints while maximizing the frequency, thus achieving a balance between performance and power consumption. The process of constructing the optimal Vf mapping table is as follows: Set the frequency scan range; based on historical data, determine a scan interval for a test frequency. , ,in This is the lowest operating frequency supported by the CPU. It is the highest operating frequency designed for the CPU; Then iterate through the scan intervals and calculate the power consumption, starting from the highest frequency. Start by iterating down to lower frequencies. For each frequency, determine the CPU core's quality factor. and the average minimum stable voltage of the same model Calculate the stable minimum voltage at this frequency = Then substitute it into the power consumption modeling formula The CPU cores were obtained at different test frequencies. Power consumption ; judge Is it less than or equal to the power budget of the CPU core? Find the first one (the first one in the descending order of traversal) that satisfies The optimal frequency is denoted as The corresponding minimum stable voltage at this time is Generate a Vf mapping table and obtain the stable minimum voltage corresponding to each CPU core. All core Organized into core numbers and The combined mapping table, that is, the optimal Vf mapping table considering the chip's physical characteristics, contains the dynamic setting instructions for each CPU core. Specifically, cores with different chip qualities require different combinations of stable operating voltage (V) and frequency (f). This solution constructs an optimal Vf mapping table that takes into account the chip quality, customizing the most suitable Vf combination for each core. Under power budget constraints, cores with good quality can operate stably at higher frequencies at lower voltages, while cores with slightly poorer quality can find the highest stable frequency within their own power budget. The increase in frequency directly means that the core processes instructions and data faster, and can complete more computations or memory accesses per unit time, thereby effectively improving the throughput of a single core.

[0018] S4: Based on the optimal Vf mapping, the Vf parameters are sent through the CPU power management interface and a closed-loop feedback is formed to realize the dynamic power allocation of the CPU. The optimal Vf mapping table records the optimal voltage for each CPU core. and optimal frequency Combining to achieve the optimal frequency According to the mapping relationship specified in the CPU architecture manual, it is converted into binary code recognizable by the frequency control register, and the corresponding write instructions are generated. For voltage configuration, based on the hardware design, ... Convert the write instruction into a binary encoded form that the voltage control register can receive; After the CPU core receives these instructions, its internal hardware circuitry will automatically respond, triggering modules such as the voltage regulator and clock generator to operate. If an increased performance bottleneck risk is detected in a particular core, for example: Computational PMC data shows that the utilization rate of the integer arithmetic unit is consistently too high, resulting in a performance bottleneck, indicating that the current Vf settings may not be able to meet the workload requirements; At this point, it is necessary to rebuild the optimal Vf mapping table, generate new dynamic setting instructions, and issue them again through the CPU power management interface to achieve dynamic allocation of power resources.

[0019] In the application, several formulas are calculated by removing dimensions and taking their numerical values. The formulas are established by collecting a large amount of data and simulating the most recent real situation. Some coefficients or weights in the formulas are set by those skilled in the art according to the actual situation, so they will not be elaborated here.

[0020] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented in software, the above embodiments can be implemented, in whole or in part, as a computer program product. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution.

[0021] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A CPU dynamic power allocation method for improving system throughput, characterized in that, include: S1: Collect real-time performance monitoring counter data for each CPU core to obtain the current performance bottleneck risk level of each core's responsible features. S2: Construct a load risk prediction model to predict the risk level of performance bottlenecks and obtain risk trend factors. Collect basic power budget data for each CPU core and combine it with risk trend factors to obtain the optimal temporary power budget. Output a forward-looking power budget bias strategy based on the optimal temporary power budget. The load risk prediction model includes a feature embedding layer, a temporal attention layer, a load risk fusion layer, and a prediction output layer. The feature embedding layer inputs the performance bottleneck risk level, and the prediction output layer outputs the risk trend factor. S3: Construct the optimal Vf mapping table by power budget bias strategy and chip quality factor; S4: Based on the optimal Vf mapping, Vf parameters are sent through the CPU power management interface and a closed-loop feedback is formed to realize the dynamic power allocation of the CPU.

2. The CPU dynamic power allocation method for improving system throughput according to claim 1, characterized in that, The feature embedding layer maps the three types of load features—computation-type PMC, memory-type PMC, and instruction-type PMC—into a unified feature space and embeds them through a fully connected layer to obtain the memory-type feature embedding vector E. The temporal attention layer predicts the future risk of the current load based on the importance of different load characteristics, which are load characteristics at different times. Assign weights to obtain the temporal attention output vector. ,in, The dimension of the key vector. For querying the matrix, The key matrix, It is a value matrix; The load risk fusion layer is based on the temporal attention output vector corresponding to different load characteristics. For load characteristics respectively Temporal attention output vector The gating weights are calculated by multiplying each feature embedding vector element-wise with its corresponding gating weight, and then summing the results to obtain the fused risk feature vector. ; The prediction output layer is based on the fused risk feature vector. Predict the risk level of performance bottlenecks in the future: , This indicates a fully connected layer.

3. The CPU dynamic power allocation method for improving system throughput according to claim 2, characterized in that, The process for obtaining the risk trend factors is as follows: Risk of performance bottlenecks in future moments The risk trend factor is obtained by comparing it with the current performance bottleneck risk level: ,in, The load is predicted to increase. Predict load decreases during a downturn.

4. The CPU dynamic power allocation method for improving system throughput according to claim 3, characterized in that, The process of obtaining the optimal temporary electricity budget by combining risk trend factors is as follows: According to the basic electricity budget Calculate the risk compensation bias by combining risk trend factors. Then, the optimal temporary power budget is obtained based on the risk compensation bias: ,in, For the optimal temporary electricity budget, This is the risk compensation coefficient.

5. The CPU dynamic power allocation method for improving system throughput according to claim 1, characterized in that, The process of the forward-looking power budget bias strategy based on the optimal temporary power budget output is as follows: Optimal temporary power budget for all CPU cores Perform global constraints and adjustments, and calculate the sum of all core temporary power budgets. and compare it with the system's total power budget. When comparing, Calculate the scaling factor. ; Then, based on the scaling factor Risk compensation bias for each CPU core After optimization and adjustment, the adjusted bias is expressed as follows: Ultimately, the CPU core's power budget bias strategy is expressed as: ; Finally, the number of each CPU core is associated with its corresponding power budget bias strategy. Organize the data into a mapping table to obtain a forward-looking electricity budget bias strategy.

6. The CPU dynamic power allocation method for improving system throughput according to claim 1, characterized in that, The process of obtaining the body constitution factor of the chip is as follows: The chip is quantitatively characterized, and the minimum voltage at which the core can operate stably at the current frequency is recorded, denoted as . where i is the index number. For test frequency, based on test frequency Obtain CPU core frequency lower body constitution factors The calculation formula is: ,in, For test frequency The lowest average stable voltage.

7. A CPU dynamic power allocation method for improving system throughput according to claim 6, characterized in that, The process of power consumption modeling based on the power budget bias strategy and the chip's quality factor is as follows: The power consumption rule for the stable voltage V is defined based on the chip's quality factor: ； Will By substituting the power consumption formula into the model, and iterating through different test frequencies f, the corresponding power consumption is calculated. The model is completed by finding the highest frequency at which power consumption is less than or equal to the power budget, thus achieving the goal of maximizing performance within the power budget. The formula is expressed as: ； Where k is a constant related to the CPU architecture, and C is the core's equivalent capacitance.

8. A CPU dynamic power allocation method for improving system throughput according to claim 7, characterized in that, The process of constructing the optimal Vf mapping table is as follows: Set the scan interval of the test frequency as ,in This is the lowest operating frequency supported by the CPU. It is the highest operating frequency designed for the CPU; Traverse the scan interval and calculate power consumption, starting from the highest frequency. Start by iterating down to lower frequencies. For each frequency, determine the CPU core's quality factor. and the average minimum stable voltage of the same model Calculate the stable minimum voltage at this frequency = Then, by substituting the power consumption modeling formula, the CPU cores at different test frequencies are obtained. Power consumption ; Determine different test frequencies Power consumption Is it less than or equal to the power budget of the CPU core? Find the first one that satisfies The optimal frequency is denoted as The corresponding minimum stable voltage at this time is Obtain the stable minimum voltage for each CPU core. All core Organized into core numbers and By combining the mapping tables, the optimal Vf mapping table is obtained.

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