Signal processing method, chip design verification method and related device
By adjusting the clock cycle delay of key signals to match the behavior of the library synchronization unit simulation model, the problem of inaccurate simulation by the library synchronization unit simulation model was solved, and accurate verification of the chip design was achieved.
Patent Information
- Application Number
- CN202511036947.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-25
- Publication Date
- 2025-11-14
AI Technical Summary
The library synchronization unit simulation model cannot accurately simulate its behavior under different verification scenarios, leading to errors in the verification of the chip design under test.
By acquiring the key signals of the chip under test design, the simulation model of the library synchronization unit used during the jump is determined, and the clock cycle delay is adjusted according to the predefined signal synchronization processing method of the model to make the timing of the processed key signals consistent with the timing of the signals expected to be generated by the library synchronization unit.
This ensures the correctness of the simulation model of the library synchronization unit, simplifies the verification process of the library synchronization unit, and thus simplifies the verification of the chip design under test.
Smart Images
Figure CN120951541A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of chip verification technology, specifically to a signal processing method, a chip design verification method, and related devices. Background Technology
[0002] Library synchronization units (LCUs) are hardware modules specifically designed to solve cross-clock domain communication problems. These LCUs have built-in logic and timing control mechanisms to ensure the correctness and stability of data transmission between different clock domains. The LCU simulation model in the verification platform is used to simulate the behavior of these LCUs in a simulation environment. By ensuring the timing consistency of critical signals processed by the LCU simulation model, the verification platform can accurately verify the timing logic of the Design Under Test (DUT).
[0003] However, because library synchronization units exhibit different behavioral characteristics (e.g., randomness) in different verification scenarios, simulation models of these units may fail to accurately simulate their behavior, leading to errors in the verification of the chip under test (DUT). Therefore, ensuring the accuracy of the library synchronization unit simulation model is a problem that verification personnel need to address. Summary of the Invention
[0004] In view of this, embodiments of the present invention provide a signal processing method, a chip design verification method, and related apparatus to ensure the simulation correctness of the library synchronization unit simulation model.
[0005] To address the above problems, the embodiments of the present invention provide the following technical solutions.
[0006] In a first aspect, embodiments of the present invention provide a signal processing method applied to an inspector of a verification platform, the signal processing method comprising:
[0007] Obtain key signals from the design of the chip under test;
[0008] Determine the library synchronization unit simulation model used when the key signal jumps;
[0009] A predefined signal synchronization processing method is determined corresponding to the determined library synchronization unit simulation model. The signal synchronization processing method is defined as follows: different library synchronization unit simulation models are used to adjust the clock cycle delay of the key signal, and the clock cycle delay is matched with the behavior of the library synchronization unit simulated by the library synchronization unit simulation model.
[0010] The clock cycle of the key signal is adjusted according to the clock cycle delay amount defined by the signal synchronization processing method to obtain the processed key signal; so that the timing of the processed key signal is consistent with the expected signal timing of the library synchronization unit under the corresponding behavior.
[0011] Secondly, embodiments of the present invention provide a chip design verification method, including:
[0012] Determine the design of the chip under test;
[0013] The key signals of the chip under test design are verified. If the timing of the key signals after processing is consistent with the timing of the signals expected to be generated by the library synchronization unit, then the chip under test design is verified.
[0014] The processed key signal is obtained based on the signal processing method described in the first aspect.
[0015] Thirdly, embodiments of the present invention provide a signal processing apparatus for use as an inspector in a verification platform, the signal processing apparatus comprising:
[0016] The key signal acquisition module is used to acquire key signals of the chip under test design.
[0017] The jump confirmation module is used to determine the library synchronization unit simulation model used when the key signal jumps;
[0018] The synchronization processing method determination module is used to determine a predefined signal synchronization processing method corresponding to the determined library synchronization unit simulation model. The signal synchronization processing method is defined as follows: different library synchronization unit simulation models are used to adjust the clock cycle delay of the key signal, and the clock cycle delay is matched with the behavior of the library synchronization unit simulated by the library synchronization unit simulation model.
[0019] The key signal adjustment module is used to adjust the clock period of the key signal according to the clock period delay amount defined by the signal synchronization processing method to obtain the processed key signal; so that the timing of the processed key signal is consistent with the expected signal timing of the library synchronization unit under the corresponding behavior.
[0020] Fourthly, embodiments of the present invention provide a chip design verification apparatus, comprising:
[0021] The chip under test design determination module is used to determine the design of the chip under test.
[0022] The verification module is used to verify the processed key signals of the chip under test design. If the timing of the processed key signals is consistent with the timing of the signals expected to be generated by the library synchronization unit, the chip under test design is verified.
[0023] The processed key signal is obtained based on the signal processing device described in the third aspect.
[0024] Fifthly, embodiments of the present invention provide an electronic device, including a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the signal processing method as described in the first aspect.
[0025] In a sixth aspect, embodiments of the present invention provide a storage medium storing a program that, when executed, implements the signal processing method as described in the first aspect.
[0026] In a seventh aspect, embodiments of the present invention provide a computer program product, including a computer program that, when executed, implements the signal processing method as described in the first aspect.
[0027] This invention provides a signal processing method applied to a checker of a verification platform. The signal processing method includes: acquiring key signals of a chip under test design; determining the library synchronization unit simulation model used when the key signal jumps; determining a predefined signal synchronization processing method corresponding to the determined library synchronization unit simulation model, wherein the signal synchronization processing method defines: different library synchronization unit simulation models are used to adjust the clock cycle delay of the key signal, the clock cycle delay matching the behavior of the library synchronization unit simulated by the library synchronization unit simulation model; adjusting the clock cycle of the key signal according to the clock cycle delay defined by the signal synchronization processing method to obtain a processed key signal; and ensuring that the timing of the processed key signal is consistent with the expected signal timing of the library synchronization unit under the corresponding behavior.
[0028] The signal processing method provided in this invention can determine the signal synchronization processing method corresponding to the library synchronization unit simulation model based on the specific simulation model used when the critical signal jumps. Since the signal synchronization processing method defines a clock cycle delay quantity corresponding to the library synchronization unit simulation model, different clock cycle delay quantities can be flexibly used based on the determined specific library synchronization unit simulation model to ensure that the timing of the finally generated processed critical signal is consistent with the expected signal generated by the library synchronization unit. This avoids the situation where the library synchronization unit simulation model cannot meet the actual behavior of the library synchronization unit due to the inherent behavioral characteristics (e.g., randomness) of the library synchronization unit, resulting in the processed critical signal...
[0029] The timing of the signal is inconsistent with the timing of the signal expected to be generated by the library synchronization unit (i.e., the signal generated after hardware processing by the library synchronization unit). Furthermore, since the key information is checked and processed in the checker of the verification platform in this embodiment of the invention, that is, the key signal checking and processing function is added to the checker, it is convenient to use different library synchronization unit simulation models. Thus, it is possible to simplify the verification of the library synchronization unit while ensuring that the library synchronization unit simulation model correctly simulates the behavior of the library synchronization unit, thereby simplifying the verification of the chip under test design. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0031] Figure 1 A schematic diagram illustrating the process of verifying a chip design under test.
[0032] Figure 2 A flowchart illustrating a signal processing method provided in one embodiment of the present invention;
[0033] Figure 3 This is a timing diagram of the output signal provided in one embodiment of the present invention;
[0034] Figure 4 A flowchart illustrating a signal output method provided in one embodiment of the present invention;
[0035] Figure 5 A flowchart illustrating a chip design verification method provided in an embodiment of the present invention;
[0036] Figure 6 This is a schematic diagram of the structure of a signal processing device provided in one embodiment of the present invention;
[0037] Figure 7 A schematic diagram of the structure of a chip design verification device provided in an embodiment of the present invention. Detailed Implementation
[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0039] A verification environment is a complex system involving multiple components and tools used to ensure that a chip design meets all functional, performance, and timing requirements before manufacturing. The checker generates critical timing signals for verification.
[0040] It is an important part of the verification environment, which ensures that the timing behavior of the design meets expectations by generating and verifying these signals.
[0041] The various components of the verification environment work closely together to verify the Design Under Test (DUT). The verification process typically involves multiple steps, each performed by a different component. The following details the verification steps and the role of each component:
[0042] Step 1: Define validation requirements
[0043] This step is to clarify the functional specifications and verification objectives of the DUT. It is usually done by verification engineers and design engineers through documents and meetings to obtain verification test documents, which include: test scenarios, functional points and verification strategies.
[0044] Step 2: Set up the test platform
[0045] This step is to create a test framework that can simulate a real-world environment. Typically, a test platform is defined to provide the interface and test framework for the DUT; a Stimulus Generator generates test stimuli to be output to the DUT interface, which include randomized test vectors and predefined test scenarios.
[0046] Step 3: Generate test stimuli
[0047] The test stimuli generated by the stimulus generator in step 2 are used to provide input signals to the DUT, simulating various possible usage scenarios, and driving the test stimuli generated by the stimulus generator to the input interface of the DUT.
[0048] Step 4: Run the simulation
[0049] The simulation task is performed using a simulator to mimic the behavior of the DUT running the stimulus signals generated by the stimulus generator. The input and output signals of the DUT are monitored using a monitor, and these are converted into transactions. Simulation waveforms, log files, and transaction records are generated.
[0050] Step 5: Check and Verify
[0051] This step is used to verify whether the DUT's output meets expectations. The checker verifies the DUT's actual output using assertions or a reference model; it compares the DUT's actual output with the expected output using a scoreboard, records the verification results, and generates a verification report. The verification report includes pass / fail information and error logs.
[0052] Through the collaboration of these steps and components, the verification platform can comprehensively and efficiently verify the chip design under test, ensuring that it can operate correctly under various conditions.
[0053] To facilitate understanding the verification implementation of chip-under-test designs based on a verification platform, please refer to [link / reference]. Figure 1 , Figure 1 This is a schematic diagram illustrating the process of verifying a chip design under test.
[0054] exist Figure 1 In this context, the verification environment (ENV) and the test sequence define a series of transactions input to the verification environment and changes in the interface signals of the Design Under Test (DUT). Each transaction describes how to manipulate the interface signals of the DUT.
[0055] Within ENV, there are two modules: the agent module (i_agent) and the checker. The main function of i_agent is to provide a configurable, modular verification component for generating and driving transactions to the DUT, while simultaneously monitoring the DUT's input behavior. It acts as an input verification agent in the verification environment, ensuring the DUT functions correctly under various input conditions. The checker plays a crucial role in the verification environment, ensuring the DUT's behavior conforms to design specifications through protocol checks, functional checks, timing checks, error detection, and coverage collection.
[0056] The i-agent typically includes a Sequencer and a Driver. The Sequencer is a component that acts as a bridge between the Sequence and the Driver, receiving transactions from the Sequence and passing these transactions to the Driver. The Driver is a key component responsible for converting transactions into actual signals and driving these signals to the DUT.
[0057] Please refer to Figure 1 , combined Figure 1 A brief overview of the verification process for chip designs under test (e.g., multi-clock domain designs):
[0058] 1) Load the Sequence into the Sequencer; the Sequencer uses the key signals of the chip under test generated by the Sequence as excitation signals. These excitation signals can be random, predefined, or generated according to specific verification requirements.
[0059] 2) The driver applies the excitation signal generated by the sequence to the input terminal of the chip under test design through a virtual interface.
[0060] When critical signals need to be transmitted across clock domains, these signals are synchronized using a library synchronization unit simulation model. This synchronization ensures the critical signals are stable in the target clock domain, avoiding metastability issues. The library synchronization unit simulation model adjusts the timing of the critical signals based on the behavior of the synchronization units in the actual hardware. This may include delay adjustments and signal transition detection.
[0061] 3) The monitor monitors the output signals of the chip under test and sends the results to the checker.
[0062] 4) The Checker verifies whether the synchronized excitation signal meets the design requirements. This includes checking the timing, stability, and functional correctness of the signal. Specifically, the Checker performs timing checks to ensure that the timing of the synchronized excitation signal is consistent with the timing of the signal generated by the library synchronization unit in the actual hardware (i.e., the expected generated signal).
[0063] However, since the behavior of the library synchronization unit varies in different verification scenarios, the simulation model of the library synchronization unit cannot accurately simulate the random behavior of the library synchronization unit. As a result, when the library synchronization unit simulation model is used to process key signals in the verification platform, the timing of the processed key signals is inconsistent with the timing of the expected generated signals obtained by the actual hardware processing of the library synchronization unit, leading to errors in the verification of the chip design under test.
[0064] To address the above problems, embodiments of the present invention provide a signal processing method applied to the checker of a verification platform. Please refer to [link / reference]. Figure 2 , Figure 2 A flowchart of a signal processing method provided in one embodiment of the present invention.
[0065] like Figure 2 As shown, the method includes:
[0066] Step S201: Obtain key signals of the chip under test design.
[0067] Critical signals are signals that have a significant impact on the functionality, performance, and timing behavior of the chip design under test during the verification process.
[0068] Critical signals can originate directly from the stimulus signals generated by the aforementioned sequences. For example, when the critical signal is a clock signal or a reset signal, these critical signals are typically stimulus signals generated by sequences. Critical signals can also originate from the response signals generated by the chip under test (DUT) under the stimulus signal. For instance, after receiving a stimulus signal, the DUT will generate a response signal based on its internal logic. These generated response signals are also a type of critical signal.
[0069] When using the library synchronization unit simulation model to handle the synchronization problem of key signals in the design of a chip under test, the design of the chip under test can be various types of digital circuit designs, including multi-clock domain designs, complex digital logic designs, interface designs, mixed-signal designs, low-power designs, and security and reliability designs.
[0070] Step S202: Determine the library synchronization unit simulation model used when the key signal jumps.
[0071] When a critical signal indicates a jump, the library synchronization unit simulation model should be used for signal processing.
[0072] The library synchronization unit simulation model is used to simulate the behavior of the library synchronization unit under different verification scenarios. In other words, the library synchronization unit simulation model selected in the verification platform is also different for library synchronization units with different behaviors.
[0073] The library synchronization unit is a module provided by the manufacturer, which, after instantiation, enables signal synchronization. The library synchronization unit is not merely a simulation model; it is an actual hardware unit, and a corresponding model (the library synchronization unit simulation model) is used for verification during the validation process.
[0074] For example, the specific library synchronization unit simulation model used when the key signal jumps can be determined by defining macros; defining macros can better meet the different verification requirements under different library synchronization unit simulation models.
[0075] In addition to defining macros, the library synchronization unit simulation model used when critical signals of the library synchronization unit jump can also be confirmed by using module behavior description code (such as always blocks, assign statements) in SystemVerilog.
[0076] Step S203: Determine the predefined signal synchronization processing method corresponding to the determined library synchronization unit simulation model.
[0077] The signal synchronization processing method is defined as follows: different library synchronization unit simulation models are used to adjust the clock cycle delay of the key signal, and the clock cycle delay is matched with the behavior of the library synchronization unit simulated by the library synchronization unit simulation model.
[0078] Different library synchronization unit simulation models employ different signal synchronization processing methods. Since the clock cycle delay is matched to the behavior of the library synchronization unit simulated by the simulation model, the corresponding signal synchronization processing method can be determined based on the specific library synchronization unit simulation model. When adjusting the key signal, it can satisfy the different behaviors of the library synchronization unit. When facing the random behavior of the library synchronization unit, a matching clock cycle delay can also be used to ensure that the processed key signal is the same as the actual processing result (expected generated signal) of the library synchronization unit.
[0079] Step S204: Adjust the clock cycle of the key signal according to the clock cycle delay amount defined by the signal synchronization processing method to obtain the processed key signal.
[0080] The timing of the processed key signals is consistent with the timing of the signals expected to be generated by the library synchronization unit.
[0081] The clock cycle delay is matched with the behavior of the specific library synchronization unit. The selection of the library synchronization unit simulation model also corresponds to the behavior of the specific library synchronization unit. Therefore, after determining the specific library synchronization unit simulation model, the clock cycle delay defined in the applicable signal synchronization processing method is determined. After adjusting the clock cycle of the key signal, the timing of the processed key signal can be consistent with the expected signal timing of the library synchronization unit under this behavior, thus accurately simulating the behavior of the library synchronization unit.
[0082] As can be seen, the signal processing method provided in this embodiment of the invention can determine the signal synchronization processing method corresponding to the library synchronization unit simulation model based on the specific library synchronization unit simulation model used when the key signal jumps. Since the signal synchronization processing method defines a clock cycle delay number corresponding to the library synchronization unit simulation model, different clock cycle delay numbers can be flexibly used based on the determined specific library synchronization unit simulation model to ensure that the timing of the finally generated processed key signal is consistent with the timing of the signal expected to be generated by the library synchronization unit. This avoids the situation where the library synchronization unit simulation model cannot meet the actual behavior of the library synchronization unit due to the behavior characteristics of the library synchronization unit itself (e.g., randomness), resulting in a timing inconsistency between the timing of the processed key signal and the timing of the signal expected to be generated by the library synchronization unit (i.e., the signal generated after hardware processing by the library synchronization unit). Furthermore, since this embodiment of the invention performs key information inspection and processing in the checker of the verification platform, that is, adds key signal inspection and processing functions to the checker, it facilitates the use of different library synchronization unit simulation models. This allows for the simplification of library synchronization unit verification while ensuring that the library synchronization unit simulation model correctly simulates the behavior of the library synchronization unit, thereby simplifying the verification of the chip under test design.
[0083] Since the selection of the library synchronization unit simulation model is related to the behavior of the specific library synchronization unit, in order to accurately simulate different behaviors of the library synchronization unit, in one embodiment, the library synchronization unit simulation model may include: a non-random library synchronization unit simulation model and a random library synchronization unit simulation model.
[0084] The non-random library synchronization unit simulation model refers to a model that can be used to simulate the behavior of library synchronization units that do not have randomness.
[0085] For example, the non-random library synchronization unit simulation model can be the SYNC_CELL library synchronization unit simulation model. The SYNC_CELL library synchronization unit simulation model is mainly used to accurately simulate the hardware behavior of the library synchronization unit, focusing on verifying the correctness of its function rather than simulating its randomness or uncertainty. Therefore, the SYNC_CELL library synchronization unit simulation model can be used to simulate the non-random behavior of the library synchronization unit.
[0086] The aforementioned random library synchronization unit simulation model refers to a model that can be used to simulate the random behavior of a library synchronization unit.
[0087] For example, the stochasticity library synchronization unit simulation model can be a VCS (Verilog Compiler Suite, a hardware description language simulation tool) library synchronization unit simulation model or an XPROP (X-Propagation) library synchronization unit simulation model.
[0088] The VCS (Verilog Compiler Suite) simulation tool itself supports randomization. When verifying library synchronization units, the VCS library synchronization unit simulation model can be used to simulate the random behavior of the library synchronization units (e.g., due to input signal uncertainty or clock jitter). In other words, the randomization function of VCS is used to simulate and verify the random behavior of library synchronization units. This helps to discover potential problems in the design, such as metastability or timing violations.
[0089] The XPROP library's synchronization unit simulation model is primarily used to simulate the propagation of X-states (indeterminate states), which are closely related to stochastic behavior. In the XPROP library's synchronization unit simulation model, the simulator attempts to simulate the X-states that may occur in the synchronization unit and attempts to propagate these X-states.
[0090] When the behavior of library synchronization units is random, the XPROP library synchronization unit simulation model can help verify whether these random behaviors will cause problems in the chip under test (DUT) design. For example, if the library synchronization unit generates X states under certain conditions, the XPROP library synchronization unit simulation model can simulate the propagation of these X states, ensuring that the DUT design can correctly handle these uncertainties.
[0091] There are two ways to synchronize key signals. The first way is to synchronize by clock ticking. This synchronization method is easy to generate and can be achieved by simple clock ticking. The second way is to synchronize by calling the synchronization unit in the process library. The signal generated by this method has randomness and is more in line with the actual situation in the chip.
[0092] However, for the checker, generating the same logic (i.e., randomness) of the processed key signal using the second method (implemented by simple clock ticking) is a significant challenge. In other words, it is extremely difficult to generate the processed key signal in the checker solely through ticking, while maintaining the same randomness as the signal generated by the library synchronization unit (the expected generated signal).
[0093] Because the randomness of the library synchronization unit is directly related to the random seed, and the random seed in the library synchronization unit will randomly jump before and after use, this will result in a large degree of randomness in the timing of the expected generated signal produced by the library synchronization unit.
[0094] For example, when synchronizing the rising edge of a critical signal in a chip under test (DUT) design, due to the presence of a random seed, the timing of the expected generated signal after synchronization will be delayed by one clock cycle, i.e., the rising edge will be delayed by 3 + 1 clock cycles. After synchronizing the rising edge of the critical signal, the random seed changes, and when synchronizing the falling edge of the critical signal, there is a simple delay of 3 clock cycles, without any additional delay. In this case, the checker cannot generate the same expected signal using the simple clock pacing method described in the first approach. Furthermore, if the timing logic controlled by this critical signal is sensitive, such as using a counter to control frequency increase / decrease, errors may occur in the timing logic of the verification environment.
[0095] The following section describes the key signal processing steps using simulation models of library synchronization units, including the SYNC_CELL, VCS, and XPROP models. Please refer to [link / reference]. Figure 3 , Figure 3 The output signal timing diagram is provided for one embodiment of the present invention.
[0096] Figure 3 In this context, CLK represents the clock signal, and the corresponding waveform is the clock signal waveform.
[0097] like Figure 3 As shown in waves 2-5:
[0098] wave1 represents the waveform of the processed key signal obtained using the simulation model of the non-random library synchronization unit; it can be seen that the processed key signal is delayed by a fixed three clock cycles compared to the unprocessed key signal, that is, the clock cycle delay is 3.
[0099] wave2 represents the waveform of the processed key information obtained using the simulation model of the randomness library synchronization unit, with the random seed set to 0, meaning there is no random delay. The processed key signal is delayed by four clock cycles compared to the unprocessed key signal, i.e., the clock cycle delay is 4.
[0100] wave3 represents the waveform of the processed key information obtained using the simulation model of the randomness library synchronization unit, with a random seed of 1. This means that when there is a random delay, the processed key signal is delayed by five clock cycles compared to the processor's key signal, which is equivalent to a clock cycle delay of 4.
[0101] Wave 4 represents the waveform of the critical signal after processing, generated when the critical signal is adjusted (synchronized) using a simulation model with a randomness library synchronization unit, and the random seed is 1 when adjusting the rising edge and 0 when adjusting the falling edge. It can be seen that the rising edge of the processed critical signal is delayed by five clock cycles compared to the rising edge of the original critical signal, that is, the clock cycle delay at the rising edge is 5; the falling edge of the processed critical signal is delayed by four clock cycles compared to the falling edge of the original critical signal, that is, the clock cycle delay at the falling edge is 4.
[0102] Wave 5 represents the waveform of the critical signal after processing, obtained by adjusting (synchronizing) the critical signal using a simulation model of a random library synchronization unit, with the random seed set to 0 when adjusting the rising edge and to 1 when adjusting the falling edge. It can be seen that the rising edge of the processed critical signal is delayed by four clock cycles compared to the rising edge of the original critical signal, i.e., the clock cycle delay at the rising edge is 4; the falling edge of the processed critical signal is delayed by five clock cycles compared to the falling edge of the original critical signal, i.e., the clock cycle delay at the falling edge is 5.
[0103] Depend on Figure 3 It can be seen that under the random library synchronization unit simulation model, that is, under the VCS library synchronization unit simulation model and the XPOP library synchronization unit simulation model, the processed key signal obtained not only differs from the non-random library synchronization unit simulation model (wave1) in timing, but also the number of clock cycle delays changes with the presence of random delays, resulting in changes in the timing of the processed key signal, as shown in wave4 and wave5.
[0104] Therefore, simply adjusting key signals using a simple non-random library synchronization unit simulation model is insufficient to meet the actual working requirements and behavioral characteristics of the library synchronization unit. A model that satisfies the random behavior of the simulated library synchronization unit can also be used to ensure the correctness of the simulation of the library synchronization unit and the verification correctness of the chip design under test.
[0105] In one embodiment, under a non-random library synchronization unit simulation model, the clock cycle delay amount used in the first method is used to adjust the key signal, and the processed key signal is a signal delayed by three clock cycles. Under random library synchronization unit simulation models such as VCS and XPROP, the clock cycle delay amount used under different random delay conditions is used to adjust the key signal. Specifically, in the case of no random delay, a four-clock-cycle delay is used to adjust the key signal; in the case of random delay, a five-clock-cycle delay is used. Therefore, in one embodiment, before step S201, the signal processing method further includes: defining the signal synchronization processing method under each library synchronization unit simulation model; specifically, it includes the following steps:
[0106] For the simulation model of the non-random library synchronization unit, based on the non-random synchronization processing method adopted by the simulation model, the number of clock cycle delays of the key signal is defined as a first value to obtain the first signal synchronization processing method.
[0107] For the random library synchronization unit simulation model, it is determined whether the library synchronization unit simulated by the random library synchronization unit simulation model has random delay. If so, the number of clock cycle delays of the key signal is defined as a second value to obtain a second signal synchronization processing method; if not, the number of clock cycle delays of the key signal is defined as a third value to obtain a third signal synchronization processing method.
[0108] Wherein, the first value is the fixed clock cycle delay in the non-random synchronization processing method; the third value is the basic clock cycle delay used in the simulation model of the randomness library synchronization unit; and the second value is the random clock cycle delay obtained by adding the random delay clock cycle to the third value.
[0109] The first value is the number of clock cycle delays used in the simulation model of the non-random library synchronization unit, that is, the first value is 3.
[0110] The third value is the number of 4 clock cycle delays used in the randomness library synchronization unit simulation model when there is no random delay, that is, the third value is the number of base clock cycle delays, which is 4.
[0111] The second value is the number of 5 clock cycle delays used in the randomness library synchronization unit simulation model when there is random delay, i.e., the second value is 5.
[0112] After determining the appropriate signal synchronization processing method for different library synchronization unit simulation models, when using a non-random library synchronization unit simulation model, step S204 may include:
[0113] For the simulation model of the non-random library synchronization unit, the key signal is adjusted according to the first value defined by the first signal synchronization processing method to obtain the processed key signal.
[0114] Based on the above... Figure 3 As can be seen from the waveform analysis, under the simulation model of the non-random library synchronization unit, the first value is three clock cycles. That is, the key signal is delayed by 3 clock cycles.
[0115] When using a stochastic library synchronization unit simulation model, step S204 may include:
[0116] For the simulation model of the random library synchronization unit, it is determined whether there is a random delay in the library synchronization unit corresponding to the simulation model. If so, the key signal is adjusted according to the second value defined by the second signal synchronization processing method to obtain the processed key signal; if not, the key signal is adjusted according to the third value defined by the third signal synchronization processing method to obtain the processed key signal.
[0117] Based on the above Figure 3 As can be seen from the waveform analysis, under the simulation model of the random library synchronization unit: the second value when there is random delay is five beats, and the third value when there is no random delay is four beats.
[0118] Based on the above, the first value is the delay amount for three clock cycles, the second value is the delay amount for five clock cycles, and the third value is the delay amount for four clock cycles.
[0119] The following uses three library synchronization unit simulation models—SYNC_CELL, VCS, and XPROP—as examples to illustrate the simulation process of the behavior of the library synchronization unit using the signal processing method provided in this embodiment of the invention.
[0120] Please refer to Figure 4 , Figure 4 A flowchart of a signal output method provided in one embodiment of the present invention.
[0121] like Figure 4 As shown, in one embodiment, the signal output method may include the following steps:
[0122] Step 1: Determine if a critical signal triggers a jump;
[0123] After confirming that a critical signal has triggered a transition, the following steps can be taken:
[0124] Step 2: Determine whether the SYNC_CELL library synchronization unit simulation model is used when the critical signal jumps. If yes, proceed to step 3; otherwise, proceed to step 4.
[0125] Step 3: Process the key signal by delaying it by three clock cycles to obtain the processed key signal.
[0126] Step 4: Determine if the random delay is 1. If yes, proceed to step 5; otherwise, proceed to step 6.
[0127] If the library synchronization unit simulation model is not the SYNC_CELL library synchronization unit simulation model, that is, the library synchronization unit simulation model is the VCS library synchronization unit simulation model or the XPROP library synchronization unit simulation model, then determine whether the random delay is 1. If the random delay is 1, proceed to step 5; otherwise, proceed to step 6.
[0128] Step 5: Process the key signal by delaying it by five clock cycles to obtain the processed key signal.
[0129] Step 6: Process the key signal by delaying it by four clock cycles to obtain the processed key signal.
[0130] Step 7: Output the processed key signals.
[0131] Based on the same inventive concept, embodiments of the present invention also provide a chip design verification method, please refer to... Figure 5 , Figure 5 This is a flowchart illustrating a chip design verification method provided in an embodiment of the present invention.
[0132] like Figure 5 As shown, the method includes:
[0133] Step S500: Determine the design of the chip under test.
[0134] Step S501: Verify the processed key signals of the chip under test design. If the timing of the processed key signals is consistent with the timing of the signals expected to be generated by the library synchronization unit, then the chip under test design verification is passed.
[0135] The processed key signal is obtained based on the signal processing method described in any of the foregoing embodiments.
[0136] As can be seen, the chip design verification method provided in this embodiment of the invention obtains the processed key signal based on the signal synchronization processing method corresponding to the specific library synchronization unit simulation model. The signal synchronization processing method defines a clock cycle delay number corresponding to the library synchronization unit simulation model. Therefore, based on the determined specific library synchronization unit simulation model, different clock cycle delay numbers can be flexibly used to ensure that the timing of the finally generated processed key signal is consistent with the timing of the signal expected to be generated by the library synchronization unit. This avoids the situation where the library synchronization unit simulation model cannot meet the actual behavior of the library synchronization unit due to the inherent behavioral characteristics (e.g., randomness) of the library synchronization unit itself, resulting in inconsistencies between the timing of the processed key signal and the timing of the signal expected to be generated by the library synchronization unit (i.e., the signal generated after hardware processing by the library synchronization unit). Furthermore, since this embodiment of the invention performs key information inspection and processing in the checker of the verification platform, i.e., adds key signal inspection and processing functions to the checker, it facilitates the use of different library synchronization unit simulation models. This allows for the verification of the library synchronization unit while ensuring that the library synchronization unit simulation model correctly simulates the behavior of the library synchronization unit, thereby simplifying the verification of the library synchronization unit and ultimately simplifying the verification of the chip design under test.
[0137] Based on the same inventive concept, embodiments of the present invention also provide a signal processing apparatus, which is applied to the checker of a verification platform. Please refer to [reference needed]. Figure 6 , Figure 6 This is a schematic diagram of the structure of a signal processing device provided in one embodiment of the present invention.
[0138] like Figure 6 As shown, the device includes:
[0139] The key signal acquisition module 61 is used to acquire key signals of the chip under test design.
[0140] Jump confirmation module 62 is used to determine the library synchronization unit simulation model used when the key signal jumps;
[0141] The synchronization processing mode determination module 63 is used to determine a predefined signal synchronization processing mode corresponding to the determined library synchronization unit simulation model. The signal synchronization processing mode is defined as follows: different library synchronization unit simulation models are used to adjust the clock cycle delay of the key signal, and the clock cycle delay is matched with the behavior of the library synchronization unit simulated by the library synchronization unit simulation model.
[0142] The key signal adjustment module 64 is used to adjust the clock period of the key signal according to the clock period delay amount defined by the signal synchronization processing method to obtain the processed key signal; so that the timing of the processed key signal is consistent with the expected signal timing of the library synchronization unit under the corresponding behavior.
[0143] In one embodiment, the library synchronization unit simulation model includes: a non-random library synchronization unit simulation model and a random library synchronization unit simulation model.
[0144] In one embodiment, the apparatus further includes:
[0145] The synchronization processing method definition module is used to define the signal synchronization processing method under the simulation model of each library synchronization unit;
[0146] The synchronization processing method definition module is used to define the signal synchronization processing method under the simulation model of each library synchronization unit, including:
[0147] For the simulation model of the non-random library synchronization unit, based on the non-random synchronization processing method adopted by the simulation model, the number of clock cycle delays of the key signal is defined as a first value to obtain the first signal synchronization processing method.
[0148] For the random library synchronization unit simulation model, it is determined whether the library synchronization unit simulated by the random library synchronization unit simulation model has random delay. If so, the number of clock cycle delays of the key signal is defined as a second value to obtain a second signal synchronization processing method; if not, the number of clock cycle delays of the key signal is defined as a third value to obtain a third signal synchronization processing method.
[0149] Wherein, the first value is the fixed clock cycle delay in the non-random synchronization processing method; the third value is the basic clock cycle delay used in the simulation model of the randomness library synchronization unit; and the second value is the random clock cycle delay obtained by adding the random delay clock cycle to the third value.
[0150] In one embodiment, the key signal adjustment module is used to adjust the key signal according to the clock cycle delay defined by the signal synchronization processing method to obtain the processed key signal, including:
[0151] For the simulation model of the non-random library synchronization unit, the key signal is adjusted according to the first value defined by the first signal synchronization processing method to obtain the processed key signal.
[0152] In one embodiment, the key signal adjustment module is used to adjust the key signal according to the clock cycle delay defined by the signal synchronization processing method to obtain the processed key signal, including:
[0153] For the simulation model of the random library synchronization unit, it is determined whether there is a random delay in the library corresponding to the simulation model. If there is, the key signal is adjusted according to the second value defined by the second signal synchronization processing method to obtain the processed key signal. If there is no delay, the key signal is adjusted according to the third value defined by the third signal synchronization processing method to obtain the processed key signal.
[0154] As can be seen, the signal processing apparatus provided in this embodiment of the invention can avoid the problem that the simulation model of the library synchronization unit cannot meet the actual behavior of the library synchronization unit due to the behavioral characteristics (e.g., randomness) of the library synchronization unit itself, resulting in inconsistency between the timing of the processed key signals and the timing of the signals expected to be generated by the library synchronization unit (i.e., the signals generated after hardware processing by the library synchronization unit). Furthermore, since this embodiment of the invention performs key information inspection and processing in the checker of the verification platform, that is, adds key signal inspection and processing functions to the checker, it facilitates the use of different library synchronization unit simulation models. This allows for the simplification of library synchronization unit verification while ensuring that the library synchronization unit simulation model correctly simulates the behavior of the library synchronization unit, thereby simplifying the verification of the chip under test design.
[0155] Based on the same inventive concept, embodiments of the present invention also provide a chip design verification device, please refer to... Figure 7 , Figure 7 A schematic diagram of the structure of a chip design verification device provided in an embodiment of the present invention.
[0156] like Figure 7 As shown, the device includes:
[0157] The chip under test design determination module 71 is used to determine the chip under test design.
[0158] The verification module 72 is used to verify the processed key signals of the chip under test design. If the timing of the processed key signals is consistent with the timing of the signals expected to be generated by the library synchronization unit, the chip under test design is verified.
[0159] The processed key signal is obtained based on the signal processing device described in any of the foregoing embodiments.
[0160] As can be seen, the chip design verification device provided in this embodiment of the invention obtains the processed key signal based on the signal synchronization processing method corresponding to the specific library synchronization unit simulation model. This signal synchronization processing method defines a clock cycle delay number corresponding to the library synchronization unit simulation model. Therefore, based on the determined specific library synchronization unit simulation model, different clock cycle delay numbers can be flexibly used to ensure that the timing of the finally generated processed key signal is consistent with the timing of the signal expected to be generated by the library synchronization unit. This avoids the situation where the library synchronization unit simulation model cannot meet the actual behavior of the library synchronization unit due to the inherent behavioral characteristics (e.g., randomness) of the library synchronization unit itself, resulting in inconsistencies between the timing of the processed key signal and the timing of the signal expected to be generated by the library synchronization unit (i.e., the signal generated after hardware processing by the library synchronization unit). Furthermore, since this embodiment of the invention performs key information inspection and processing in the checker of the verification platform, i.e., adds key signal inspection and processing functions to the checker, it facilitates the use of different library synchronization unit simulation models. This allows for the verification of the library synchronization unit while ensuring that the simulation model correctly simulates the behavior of the library synchronization unit, thereby simplifying the verification of the library synchronization unit and ultimately simplifying the verification of the chip design under test.
[0161] Based on the same inventive concept, embodiments of the present invention also provide an electronic device, including a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute a signal processing method or a method of a verification library synchronization unit.
[0162] Based on the same inventive concept, embodiments of the present invention also provide a storage medium storing a program that, when executed, implements a signal processing method.
[0163] Based on the same inventive concept, embodiments of the present invention also provide a computer program product, including a computer program that, when executed, implements a signal processing method.
[0164] The electronic devices in the embodiments of the present invention include, but are not limited to, mobile communication devices, ultra-mobile personal computer devices, portable entertainment devices, servers, and other electronic devices with data interaction functions. Among them, mobile communication devices include, but are not limited to, smartphones and multimedia phones; ultra-mobile personal computer devices include, but are not limited to, tablet computers; portable entertainment devices include, but are not limited to, e-book readers and handheld game consoles; and servers include, but are not limited to, computer devices.
[0165] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.
[0166] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A signal processing method, characterized in that, The signal processing method for the inspector applied to the verification platform includes: Obtain key signals from the design of the chip under test; Determine the library synchronization unit simulation model used when the key signal jumps; A predefined signal synchronization processing method is determined corresponding to the determined library synchronization unit simulation model. The signal synchronization processing method is defined as follows: different library synchronization unit simulation models are used to adjust the clock cycle delay of the key signal, and the clock cycle delay is matched with the behavior of the library synchronization unit simulated by the library synchronization unit simulation model. The clock cycle of the key signal is adjusted according to the clock cycle delay amount defined by the signal synchronization processing method to obtain the processed key signal; so that the timing of the processed key signal is consistent with the expected signal timing of the library synchronization unit under the corresponding behavior.
2. The signal processing method according to claim 1, characterized in that, The library synchronization unit simulation model includes: a non-random library synchronization unit simulation model and a random library synchronization unit simulation model.
3. The signal processing method according to claim 2, characterized in that, Before the step of acquiring the key signals of the chip under test design, the method further includes: defining the signal synchronization processing method under the simulation model of each library synchronization unit; The definition of the signal synchronization processing method under the simulation model of each library synchronization unit includes: For the simulation model of the non-random library synchronization unit, based on the non-random synchronization processing method adopted by the simulation model, the number of clock cycle delays of the key signal is defined as a first value to obtain the first signal synchronization processing method. For the random library synchronization unit simulation model, it is determined whether the library synchronization unit simulated by the random library synchronization unit simulation model has random delay. If so, the number of clock cycle delays of the key signal is defined as a second value to obtain a second signal synchronization processing method; if not, the number of clock cycle delays of the key signal is defined as a third value to obtain a third signal synchronization processing method. Wherein, the first value is the fixed clock cycle delay in the non-random synchronization processing method; the third value is the basic clock cycle delay used in the simulation model of the randomness library synchronization unit; and the second value is the random clock cycle delay obtained by adding the random delay clock cycle to the third value.
4. The signal processing method according to claim 3, characterized in that, The step of adjusting the clock period of the key signal according to the clock period delay amount defined by the signal synchronization processing method to obtain the processed key signal includes: For the simulation model of the non-random library synchronization unit, the key signal is adjusted according to the first value defined by the first signal synchronization processing method to obtain the processed key signal.
5. The signal processing method according to claim 3, characterized in that, The step of adjusting the clock period of the key signal according to the clock period delay amount defined by the signal synchronization processing method to obtain the processed key signal includes: For the simulation model of the random library synchronization unit, it is determined whether there is a random delay in the library synchronization unit corresponding to the simulation model. If so, the key signal is adjusted according to the second value defined by the second signal synchronization processing method to obtain the processed key signal; if not, the key signal is adjusted according to the third value defined by the third signal synchronization processing method to obtain the processed key signal.
6. The signal processing method according to claim 3, characterized in that, The random delay is bound to the inspector via a binding statement.
7. The signal processing method according to claim 1, characterized in that, The library synchronization unit simulation model used when the key signal jumps is determined by defining macros.
8. The signal processing method according to any one of claims 2-7, characterized in that, The simulation model of the randomness library synchronization unit includes: the X-state propagation library synchronization unit simulation model and the compiled library synchronization unit simulation model; the existence of random delay is determined by the random seed in the library synchronization unit.
9. A method for verifying chip design, characterized in that, include: Determine the design of the chip under test; The key signals of the chip under test design are verified. If the timing of the key signals after processing is consistent with the timing of the signals expected to be generated by the library synchronization unit, then the chip under test design is verified. The processed key signal is obtained based on the signal processing method described in any one of claims 1-8.
10. A signal processing apparatus, characterized in that, The inspector used in the verification platform, the signal processing device includes: The key signal acquisition module is used to acquire key signals of the chip under test design. The jump confirmation module is used to determine the library synchronization unit simulation model used when the key signal jumps; The synchronization processing method determination module is used to determine a predefined signal synchronization processing method corresponding to the determined library synchronization unit simulation model. The signal synchronization processing method is defined as follows: different library synchronization unit simulation models are used to adjust the clock cycle delay of the key signal, and the clock cycle delay is matched with the behavior of the library synchronization unit simulated by the library synchronization unit simulation model. The key signal adjustment module is used to adjust the clock period of the key signal according to the clock period delay amount defined by the signal synchronization processing method to obtain the processed key signal; so that the timing of the processed key signal is consistent with the expected signal timing of the library synchronization unit under the corresponding behavior.
11. The signal processing apparatus according to claim 10, characterized in that, The library synchronization unit simulation model includes: a non-random library synchronization unit simulation model and a random library synchronization unit simulation model.
12. The signal processing apparatus according to claim 11, characterized in that, The device further includes: The synchronization processing method definition module is used to define the signal synchronization processing method under the simulation model of each library synchronization unit; The synchronization processing method definition module is used to define the signal synchronization processing method under the simulation model of each library synchronization unit, including: For the simulation model of the non-random library synchronization unit, based on the non-random synchronization processing method adopted by the simulation model, the number of clock cycle delays of the key signal is defined as a first value to obtain the first signal synchronization processing method. For the random library synchronization unit simulation model, it is determined whether the library synchronization unit simulated by the random library synchronization unit simulation model has random delay. If so, the number of clock cycle delays of the key signal is defined as a second value to obtain a second signal synchronization processing method; if not, the number of clock cycle delays of the key signal is defined as a third value to obtain a third signal synchronization processing method. Wherein, the first value is the fixed clock cycle delay in the non-random synchronization processing method; the third value is the basic clock cycle delay used in the simulation model of the randomness library synchronization unit; and the second value is the random clock cycle delay obtained by adding the random delay clock cycle to the third value.
13. A chip design verification device, characterized in that, include: The chip under test design determination module is used to determine the design of the chip under test. The verification module is used to verify the processed key signals of the chip under test design. If the timing of the processed key signals is consistent with the timing of the signals expected to be generated by the library synchronization unit, the chip under test design is verified. The processed key signal is obtained based on the signal processing apparatus according to any one of claims 10-12.
14. An electronic device comprising a memory and a processor, characterized in that, The memory stores a program, and the processor calls the program stored in the memory to execute the signal processing method as described in any one of claims 1-8.
15. A storage medium storing a program, characterized in that, When the program is executed, it implements the signal processing method as described in any one of claims 1-8.
16. A computer program product, comprising a computer program, characterized in that, When the computer program is executed, it implements the signal processing method as described in any one of claims 1-8.