A core particle device cross-level design method

By employing a cross-level design approach for chip-particle devices, the problem of fragmentation between device unit, chip, and integrated device design stages is solved, achieving cross-level collaborative optimization, improving design efficiency and accuracy, and overcoming the limitations of traditional design.

CN120951922BActive Publication Date: 2026-01-27上海芯源创新中心
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Patent Information

Application Number
CN202511469867.6
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-10-14
Publication Date
2026-01-27
Estimated Expiration
2045-10-14

AI Technical Summary

Technical Problem

In existing technologies, the design stages of device units, chips, and integrated devices are fragmented, information transmission is unidirectional and it is difficult to achieve cross-level and cross-scale collaborative optimization, resulting in low design efficiency.

Method used

A cross-level design approach for chip-particle devices is adopted. By calling external TCAD tools for simulation, parameterized device unit models are established, topology construction and layout mapping are performed, and efficient simulation algorithms are combined to improve design efficiency, realizing cross-level collaborative design of device units, chips, and integrated devices.

Benefits of technology

It enables efficient collaborative design across levels, improves simulation accuracy and design flexibility, breaks through the design limitations of traditional single-scale levels, and enhances design efficiency and accuracy.

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Abstract

The present disclosure relates to a kind of core particle device cross-level design method, including a kind of device unit-core particle-integrated device design method covering device unit design, core particle design, system package collaborative design. By collaborative optimization design as a whole to integrated device, it can cover device unit design, core particle design, system package collaborative design and other various requirements, so as to break through the design limit of traditional single scale level circuit, and speed up design efficiency.
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Citation Information

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