Dense digital arithmetic circuit utilization for fixed point machine learning

Abstract

Systems and methods relate to improving throughput of neural networks in integrated circuits by combining values in operands to increase computational density. A system includes an integrated circuit (IC) having a multiplier circuit. The IC receives a first value and a second value in a first operand. The IC performs a multiplication operation on the first operand and the second operand via the multiplier circuit to produce a first multiplied product based at least in part on the first value and a second multiplied product based at least in part on the second value.

Description

[0001] This application is a divisional application of the same patent application, filed on March 21, 2018, with application number 201810233635.4.

[0002] Cross-references to related applications

[0003] This application is a non-provisional application claiming priority to U.S. Provisional Patent Application No. 62 / 488,636, filed April 21, 2017, entitled "Lower Precision Neural Network Systems and Methods," the entire contents of which are incorporated herein by reference for all purposes. Background Technology

[0004] This disclosure generally relates to the efficient use of arithmetic circuits (e.g., multiplication-accumulation circuits and / or digital signal processor (DSP) circuits) in integrated circuits for machine learning.

[0005] This section is intended to introduce the reader to various aspects of the field that may relate to the various aspects of this disclosure described below and / or claimed. This discussion is intended to help provide the reader with background information to facilitate a better understanding of the various aspects of this disclosure. Therefore, it is to be understood that these statements should be interpreted accordingly and not considered as prior art.

[0006] Integrated circuits such as field-programmable gate arrays (FPGAs) can include circuitry for performing various mathematical operations. For example, deep learning neural networks can be implemented in one or more integrated circuit devices for machine learning applications. The integrated circuit device can perform several operations to output results for the neural network. However, in some instances, the throughput of mathematical operations in the neural network may be limited by the hardware of the integrated circuit. Due to these limitations, the neural network may execute at a slower rate than expected. Attached Figure Description

[0007] A better understanding of the various aspects of this disclosure can be achieved by reading the following detailed description and by referring to the accompanying drawings, in which:

[0008] Figure 1 This is a block diagram of a data processing system that performs machine learning via machine learning circuitry according to an embodiment;

[0009] Figure 2 According to the embodiments Figure 1 A block diagram of a machine learning circuit;

[0010] Figure 3 According to the embodiments, it is used for via Figure 1A network diagram of a neural network that performs machine learning tasks;

[0011] Figure 4 According to the embodiments, by Figure 1 A flowchart illustrating the process of machine learning circuit execution;

[0012] Figure 5 According to the embodiments, it is used for via Figure 1 A graph of another neural network that performs machine learning circuits to perform tasks;

[0013] Figure 6 According to the embodiments Figure 1 A block diagram of the data structure for multiplication operations performed by a machine learning circuit;

[0014] Figure 7 This is a method for performing multiplication operations according to an embodiment. Figure 1 A block diagram of a machine learning circuit;

[0015] Figure 8 According to the embodiments Figure 1 A block diagram of a generalized data structure for multiplication operations performed by a machine learning circuit;

[0016] Figure 9 This is according to an embodiment for performing a generalized multiplication operation. Figure 1 A block diagram of a machine learning circuit;

[0017] Figure 10 According to the embodiments Figure 1 A block diagram of another data structure for multiplication operations performed by machine learning circuits; and Figure 11 According to the embodiments, by Figure 1 The flowchart shows the process by which a machine learning circuit performs a multiplication operation for a neural network. Detailed Implementation

[0018] One or more specific embodiments will now be described. To provide a concise description of these embodiments, not all features of the actual implementations are described in the specification. It will be appreciated that in the development of any such actual implementation (as in any engineering or design project), several implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related constraints and business-related constraints, which may vary from one implementation to another. Furthermore, it will be appreciated that such development efforts can be complex and time-consuming, but nevertheless, they will be routine tasks of design, fabrication, and manufacturing for those skilled in the art who benefit from this disclosure.

[0019] Machine learning is used in various settings to perform tasks through the use of examples. For example, neural networks can be used to perform tasks without task-specific programming. That is, a neural network can be trained from previous data to classify or infer information from current data. For example, training data can be used to identify images containing an object by analyzing other images that include and do not include the object. While the images are used as examples, this is merely illustrative, and any suitable neural network task can be performed in the embodiments described below.

[0020] Configurable devices such as programmable logic devices (PLDs) can perform one or more operations to perform tasks via machine learning. For example, an integrated circuit (IC) such as a field-programmable gate array (FPGA) can include one or more digital signal processing (DSP) blocks or DSP circuits having one or more dedicated processing blocks to perform arithmetic operations on data received by the DSP blocks. One type of dedicated processing block in a DSP block can be a multiply-accumulate (MAC) block or MAC circuit, which includes one or more multiplier circuits and / or one or more accumulator circuits. For example, in some FPGAs, the MAC block can be a hardened intellectual property (IP) block with dedicated multiplication circuitry coupled to dedicated adder circuitry. Examples of operations performed by MAC blocks include dot products, vector multiplication, etc. As described below, one or more multipliers in a DSP block can be used to perform neural network arithmetic operations during classification or derivation phases. However, the throughput of a digital signal processor (DSP) may be limited by the hardware of the IC. For example, the number of MAC blocks may limit the performance (e.g., speed) of the IC when performing arithmetic operations on neural networks.

[0021] Some arithmetic operations in neural networks may not involve the same precision as those designed to be processed in a MAC block. For example, a MAC block may include circuitry for processing 18-bit operands, but a neural network may involve multiplying lower-precision 6-bit operands. The systems and methods described below improve neural network performance in ICs by better utilizing operand capacity in multiplication operations. By combining more than one quantity into each operand of a multiplication operation, the speed at which MAC operations (e.g., weighted summation) are performed by the IC's MAC block in neural network applications can be increased. For example, two or more quantities can be packaged into a first operand received by a multiplier circuit. Two or more quantities can be packaged into a second operand received by a multiplier circuit. The multiplier circuit can then perform a multiplication operation between the first and second operands to determine the product between each of the corresponding quantities. The multiplier circuit can then output each of the products to be accumulated. To prevent multiplication overflow, gaps may be included between each of the quantities combined in the operands.

[0022] Furthermore, to reduce the possibility of accumulation overflow, the accumulator circuit of the MAC block can be bypassed to a soft logic accumulator. That is, the multiplication of the MAC operation can be performed in a hardened multiplier dedicated to performing multiplication and accumulation, and the accumulation of the MAC operation can be performed in soft logic to prevent overflow due to the accumulation of several products from the multiplication output.

[0023] Considering the above, Figure 1 A block diagram of a data processing system 10 that can be used to perform one or more tasks via machine learning is shown. The data processing system 10 may include a processor 10 operatively coupled to a memory 14. The processor 10 can execute one or more instructions stored on the memory 14 to perform one or more tasks. The data processing system 10 may include a network interface 16 for sending and / or receiving data via a network to communicate with other electronic devices. The data processing system 10 may include one or more input / output (I / O) devices 18 that can be used to receive data via I / O devices such as a keyboard, mouse, display, buttons, or other controls. The data processing system 10 may include machine learning circuitry 20 that uses machine learning methods and techniques to perform one or more tasks. The machine learning circuitry 20 may include a PLD, such as an FPGA. Each of the processor 12, memory 14, network interface 16, I / O 18, and machine learning circuitry 20 may be communicatively coupled to each other via interconnect circuitry 22, such as a communication bus.

[0024] The hardware of machine learning circuit 20 can use neural networks 100 and 138 to perform one or more tasks. Now let's turn to a more detailed discussion of examples of machine learning circuit 20. Figure 2IC 30 is shown, which can be a programmable logic device, such as a field-programmable gate array (FPGA) 32. For the purposes of this example, the device is referred to as IC 30, but it should be understood that the device can be any suitable type of device that can be used (e.g., a dedicated standard product). As shown, IC 30 may have input / output circuitry 34 for driving signals away from IC 30 via input / output pins 36 and receiving signals from other devices. Interconnect resources 38 (e.g., global and local, vertical and horizontal wires and buses) can be used to route signals on IC 30. Additionally, interconnect resources 38 may include fixed interconnects (wires) and programmable interconnects (i.e., programmable connections between corresponding fixed interconnects). Programmable logic 40 may include combinational and sequential logic circuitry. For example, programmable logic 40 may include lookup tables, registers, and multiplexers. In various embodiments, programmable logic 40 may be configured to perform custom logic functions. Programmable interconnects associated with interconnect resources can be considered as part of programmable logic 40. IC 30 may include programmable elements 42 having programmable logic 40. Programmable element 42 can be based on any suitable programmable technology, such as fuses, antifuse, electrically programmable read-only memory technology, random access memory cells, mask-programmed elements, etc.

[0025] The circuitry of IC 30 can be organized using any suitable architecture. As an example, the logic of IC 30 can be organized as a series of rows and columns of larger programmable logic regions, each of which can have multiple smaller logic regions. The logic resources of IC 30 can be interconnected using interconnect resources 38, such as associated vertical and horizontal conductors. For example, in some embodiments, these conductors may include global wires spanning substantially the entire IC 30, fractional lines such as half-lines or quarter-lines spanning portions of IC 30, staggered lines of a specific length (e.g., sufficient to interconnect several logic regions), smaller local lines, or any other suitable interconnect resource arrangement. Furthermore, in other embodiments, the logic of IC 30 can be arranged in multiple levels or layers, where multiple large regions are interconnected to form larger logic portions. Additionally, other device arrangements can use logic not arranged in rows and columns. As explained below, machine learning circuitry 20 can use the hardware of IC 30 to perform one or more tasks. For example, machine learning circuitry 20 can utilize arithmetic logic circuitry to perform arithmetic operations used in machine learning methods and techniques.

[0026] Figure 3This is a network diagram of an example machine learning network (e.g., neural network 100) that can be used to perform one or more tasks on machine learning circuit 20. While neural network 100 is described in detail as an example, any suitable machine learning methods and techniques can be used. Neural network 100 includes a set of inputs 102, 103, 104, and 106, a set of weights 108, 109, 110, and 112, a set of sums 114 and 115, and a result value 116. Each of the inputs 102, 103, 104, and 106 is weighted using the corresponding weights to determine the corresponding weighted values ​​108, 109, 110, and 112. Weighted values ​​108 and 109 can be summed at sum 114, and weighted values ​​110 and 112 can be summed at sum 115. The result value 116 can be output from sums 114 and 115 and used to perform one or more tasks from the previous data. Although four inputs and two sums are shown, this is intended to be illustrative and any suitable combination of inputs, weights, sums, and connections between them can be used.

[0027] Figure 4 This is a flowchart of the process 130 that can be performed on IC 30 in conjunction with neural network 100. At block 132, IC 30 can perform training, in which weights 108, 109, 110, and 112 are determined and / or adjusted such that the weights applied to inputs 102, 103, 104, and 106 indicate the probability of predicting the outcome value 116 for the corresponding inputs 102, 103, 104, and 106.

[0028] During training of neural network 100, at box 134, IC 30 can perform inference and / or classification on new data. In an example involving, for example, image recognition, neural network 100 can be trained using images of shapes (e.g., circles, triangles, squares), where the shapes in the images are known. Then, after adjusting the weights based on the training data, IC 30 can use neural network 100 to classify the shapes of new data. By adjusting the weights applied to inputs 102, 103, 104, and 106 based on the training data, weights can be obtained that, when applied to a new image, reflect the probability that the corresponding input of the new image includes a specific shape. In some embodiments, continuous learning may occur, where new data is then validated and the weights are continuously adjusted. Each of boxes 134 can be performed via machine learning circuitry 20, and / or some operations of each of boxes 134 can be performed via processor 12.

[0029] Figure 5This is a network diagram of an example of a neural network 138 having an input layer 140, more than one computational layer 142, and an output layer 144. The illustrated embodiment can be referred to as a deep neural network due to having more than one computational layer 142 (also called a hidden layer). As the number of computational layers 142 increases, the complexity of the input and the processing increase. In the illustrated embodiment, each input is weighted and summed at four sums, and then each corresponding sum is weighted and summed at three sums, which are then used to output the result value.

[0030] As explained below, the circuitry of IC 30 may also include one or more DSP blocks. DSP blocks may include one or more (multiplication-accumulation) MAC blocks or MAC circuitry. Each MAC block may include hardened circuitry (e.g., multiplier circuitry and accumulator circuitry) designed and specifically designed to perform multiplication and accumulation operations. While MAC blocks may include circuitry that performs multiplication and accumulation on inputs with a specific amount of precision, the neural network 100 may have inputs 102, 103, 104, and 106 with lower precision than the circuitry of the MAC blocks, along with weights. For example, while the neural network 100 may utilize weights with six-bit precision and inputs 102, 103, 104, and 106, the MAC block may include circuitry designed to process eighteen-bit inputs. By combining more than one value from the neural network 100 into the same operand of the MAC block, each multiplication of the MAC block can process additional values ​​associated with the neural network 100 to improve the throughput of the neural network 100.

[0031] Figure 6 This is an example of a set of data structures 200 of IC 30 that combine values ​​into the same operand to allow IC 30 to process the values ​​of neural network 100 at a faster rate. IC 30 can combine a first value 204 and a second value 206 into a first operand 208. That is, IC 30 can pack each bit of the first value 204 and each bit of the second value 206 into the first operand 208. For example, a first component (e.g., a first group of bits) of the first operand 208 can represent the first value 204, and a second component (e.g., a second group of bits) of the first operand 208 can represent the second value 206. Furthermore, operand 208 can include a gap between the first value 204 and the second value 206 to prevent overflow. For example, the gap 210 can be at least the number of bits of the first value 204 or the second value 206. The first value 204 can be a first input 102, and the second value 206 can be a second input 104.

[0032] Similarly, IC 30 can combine the third value 212 and the fourth value 214 into a second operand 216. The second operand 216 may include a gap 218 between the third value 212 and the fourth value 214 to prevent overflow. The gap 218 may be at least the number of bits of either the third value 212 or the fourth value 214. In the example described above where the neural network 100 utilizes six-bit precision, the first value 204, the second value 206, the third value 212, the fourth value 214, and the gaps 210 and 218 may each be six bits. The third value 212 may be a first weight to be applied to the first input 102, and the fourth value 106 may be a second weight to be applied to the second input 104.

[0033] IC 30 can perform a multiplication operation on the first operand 208 and the second operand 216 such that the product 230 includes a first product 232 of the first value 204 multiplied by the third value 212 and a second product 234 of the second value 206 multiplied by the fourth value 214 from the same multiplication operation. That is, by combining or packing more than one value into each operand 208 and 216 with sufficient gaps 210 and 218 between the values, the product 230 can include each corresponding product without overflow. For example, in neural network 100, the first product 232 could be a weighted value 108 from the first weight applied to the first input 102, and the second product 234 could be a second weighted value 110 from the second weight applied to the second input 104. By combining values ​​from neural network 100 into each operand 208 and 216, the result value 116 can be determined at a faster rate due to increased throughput.

[0034] Each of the first product 232 and the second product 234 can then be split from the multiplied product 230 and accumulated. Since accumulation can be a faster operation than multiplication, the performance of the neural network 100 can be improved by using more available precision in the hardened multiplier circuitry of IC 30 to determine more than one product from a single multiplication operation. Furthermore, the hardened circuitry of the MAC block in IC 30 can be dedicated to performing multiplication, determining the weights 108, 109, 110, and 112 at a faster rate than in circuits performing multiplication in soft logic due to the specialization of the hardened circuitry.

[0035] Figure 7 Is to implement regarding Figure 6A block diagram of the circuitry of IC 30, which describes arithmetic operations. IC 30 may include a DSP block 250 having a first input circuit 252 and a second input circuit 254 that respectively receive a first operand 208 and a second operand 216. DSP block 250 may include a MAC block 260 having a multiplier circuit 262 that multiplies the first operand 208 by the second operand 216 and outputs the product. That is, multiplier circuit 262 may be designed or hardened using circuitry that performs multiplication operations on operands with a specific precision. By including more than one value with a precision lower than the designed operand precision in the operands before performing the multiplication operation, more than one product can be determined based on the multiplication operation.

[0036] In some embodiments, MAC block 260 may include adder circuit 264, which can add products from multiplier circuit 262. Upon completion of the MAC operation, MAC block 260 may output the result via output circuit 268. In the illustrated embodiment, IC 30 may include more than one DSP block 250 (e.g., 2, 3, 4, 5, or more), and each DSP block may include more than one MAC block 252 (e.g., 2, 3, 4, 5, 10, 20, 50, or more).

[0037] MAC block 252 may include bypass circuitry 270 (e.g., a multiplexer) to bypass adder 264 and provide the multiplied product 230 to soft logic 274 of IC 30. Furthermore, IC 30 can then execute neural network sums 114 and 115 within its soft logic 274. Soft logic 274 may refer to programming instructions (e.g., code) stored in memory on IC 30 for performing operations of IC 30. IC 30 may be programmed to execute instructions to split a first product 232 and a second product 234 from the multiplied product 230. IC 30 can then execute instructions to accumulate the first product (e.g., a first weighted value 108) with one or more other products (e.g., weighted values ​​108) 276 to determine the total based on the sum 114. IC 30 can execute instructions to accumulate a second product (e.g., weighted value 110) with one or more other products (e.g., weighted value 112) for 278. For example, a first product (e.g., weighted value 108) can be retained at block 282. IC 30 can then perform another multiplication to determine a third and fourth product (e.g., weighted values ​​109 and 112) by combining a fifth and sixth value (e.g., inputs 103 and 106) into a third operand and combining a seventh and eighth value (e.g., the weights of the corresponding inputs) into a fourth operand. The third and fourth products (e.g., weighted values ​​109 and 112) are then added to each of the retained corresponding totals (282 and 284). By implementing the accumulator in soft logic 274, more accumulation operations can be performed with lower or no overflow risk. By moving to a neural network with lower precision than the six-bit example, IC 30 can obtain additional products in each multiplication operation.

[0038] Figure 8 This is a more generalized example of the data structure 300 used when performing multiplication operations in the neural network 100 on IC 30. IC 30 can combine values ​​A[0] to A[n] into a first operand. Similarly, IC 30 can combine values ​​B[0] to B[n] into a second operand. Each of values ​​302 and 306 can be separated from the other values ​​302 and 306 by gaps 304 and 308 to prevent overflow.

[0039] When performing a multiplication operation, the product 310 can include a set of multiplied values ​​312C[0] to C[n] from each corresponding value of A to B. The lower precision level of neural networks allows for the inclusion of additional values ​​in each multiplication operation. For example, in an 18-bit multiplication operation, the following table can reflect the level of precision regarding the number of values ​​in each operand:

[0040] Precision (bits) Improved calculation (low precision - 18 bits) 1 9x 2 5x 3 3x 4 2x 5 2x 6 2x

[0041] According to the following equation, this relation can be further generalized:

[0042]

[0043] Where, num comp Width refers to the number of values ​​that can be included in each operand. Mult Precision refers to the number of bits in each operand, and precision refers to the number of bits used in the operation in the neural network 100.

[0044] Figure 9 Is using Figure 8 Data structure execution Figure 3 A generalized block diagram of the circuitry for IC 30, which performs arithmetic operations on a neural network. IC 30 includes components related to... Figure 7 The circuit described is similar to the circuit described above. Furthermore, additional accumulators (e.g., in coded form) can be used for each of the values ​​312 in the product 310.

[0045] Figure 10 It can be combined with information about Figure 9 The described circuit uses a block diagram of another data structure 324. Data structure 324 includes a first operand having N values ​​326A[0] to A[n], with gaps 328 between each value in the value 326. Data structure 324 includes a second operand having a single value B[0] 330, and is padded 332 throughout the remainder of the first operand. The single value B[0] can have the same precision as each of the N values ​​of the first operand. When performing a multiplication operation, IC 30 can determine the first product 334 by multiplying the first value A[0] of the first operand with B[0] 330. IC 30 can determine the second product 334 by multiplying the second value A[1] of the first operand with B[0] 330. That is, B[0] 330 can be multiplied by each of the N values ​​326 of the first operand.

[0046] Figure 11 It is a combination Figure 5 and Figure 6 The example describes a flowchart of process 340 performed by IC 30 to perform arithmetic operations on neural network 100 to output a result value 116. At block 342, IC 30 may combine (e.g., pack) a first value and a second value into a first operand. In some embodiments, IC 30 may combine (e.g., pack) a third value and a fourth value into a second operand. (See above regarding...) Figure 8 and Figure 9 As mentioned, the additional value can be included in each of the first and second operands. Furthermore, regarding... Figure 10In the specific embodiment described, IC 30 may have only a single value in the second operand. At block 344, IC 30 may multiply the first operand by the second operand to determine a first product based at least partially on the first value and a second product based at least partially on the second value. In examples where the second operand includes a third and a fourth value, for example, the first product may be the first value multiplied by the third value, and the second product may be the second value multiplied by the fourth value. In this way, more than one product can be determined based on the same multiplication operation performed by the hardened multiplier circuitry. In some embodiments, the multiplication operation may be performed in the hardened multiplier circuitry, and the result of multiplying both the first product and the second product may be output to soft logic, in which the first product and the second product may be separated from each other.

[0047] In some embodiments, at block 346, IC 30 may perform a correction operation (e.g., in soft logic) to correct for any conflicts in the multiplication operation. For example, if the product of the first multiplication overlaps with the product of the second multiplication due to overflow, IC 30 may perform an XOR operation, a masking operation, etc., to correct for the overlapping values. At block 348, IC 30 may then add the product of the first multiplication, the product of the second multiplication, or both, to at least one sum. For example, the product of the first multiplication and the product of the second multiplication may be added to the same sum 114, or each product may be added to different sums 114 and 115, respectively. At block 350, IC 30 may output a result value that is at least partially based on at least one sum. That is, the result value may come from the sum of the two sums 114 and 115 (as in...). Figure 3 (in the middle), or the result value can be determined after several computational layers (such as in the middle). Figure 5 (In the middle). The resulting value 116 can be output (e.g., via I / O pin 36) to control the operation of IC 30. In some embodiments, the resulting value 116 can be displayed to a user. In other embodiments, the resulting value 116 can be sent to another electronic device. By combining lower-precision values ​​into operands with a design precision greater than that lower-precision value, the throughput through the neural network can be improved.

[0048] While the embodiments set forth in this disclosure may be susceptible to various modifications and alternatives, specific embodiments have been shown by way of example in the accompanying drawings and described in detail herein. However, it is to be understood that the disclosure is not intended to limit it to the specific forms disclosed. The disclosure covers all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. An integrated circuit device, comprising: Multiplier circuit; The multiplier circuit has a first input circuit, wherein the first input circuit is configured to receive a first operand obtained by a set of input values ​​from a combined neural network, wherein the first operand has a first precision, and each input value in the set of input values ​​has a second precision lower than the first precision; and The second input circuit of the multiplier circuit is configured to receive a second operand obtained by combining a set of weight values ​​of the neural network, wherein each weight value in the set of weight values ​​corresponds to a corresponding input value in the set of input values; The multiplier circuit is configured to multiply the first operand and the second operand to produce a product, the product comprising multiple weighted values ​​of the neural network that are equal to a plurality of different multiplication operations, wherein each of the plurality of weighted values ​​is equal to one of the plurality of different multiplication operations based on a weighted value from the set of weighted values ​​and an input value from the set of input values ​​corresponding to the weighted value.

2. The integrated circuit device according to claim 1, wherein, The integrated circuit device includes soft logic circuitry configured to determine a plurality of accumulated values, wherein each of the plurality of accumulated values ​​is determined at least in part based on a corresponding weighted value among the plurality of weighted values.

3. The integrated circuit device according to claim 1 or 2, wherein, The multiplier circuit is configured to perform the multiplication operation via digital signal processing (DSP) circuitry.

4. The integrated circuit device according to claim 1 or 2, wherein, The first precision is 18 bits, and the second precision is between 1 bit and 6 bits.

5. The integrated circuit device according to claim 1 or 2, wherein, The integrated circuit device also includes an adder circuit.

6. The integrated circuit device according to claim 5, wherein, The adder circuit is configured to receive one or more inputs that include at least the plurality of weighted values.

7. The integrated circuit device according to claim 5, wherein, The integrated circuit device further includes a bypass circuit configured to bypass the adder circuit.

8. The integrated circuit device according to claim 1 or 2, wherein, The first operand includes a gap between a first input value in the set of input values ​​and a second input value in the set of input values ​​to prevent or reduce overflow in the plurality of weighted values.

9. The integrated circuit device according to claim 1 or 2, wherein, The integrated circuit device is configured to perform a correction operation to correct any conflicts caused by the multiplication operation, wherein the correction operation includes an XOR operation, a masking operation, or any combination thereof.

10. The integrated circuit device according to claim 1 or 2, wherein, The integrated circuit device further includes programmable logic circuitry, wherein the programmable logic circuitry includes a multiplexer.

11. A data processing system comprising an integrated circuit device according to any one of claims 1 to 10.

12. The data processing system according to claim 11, comprising: processor; Memory coupled to the processor; as well as A network interface coupled to the memory and the processor, wherein the network interface is configured to send or receive data via a network to communicate with other electronic devices.

13. A method comprising: Receive a first operand obtained by combining a set of input values ​​through a neural network, wherein the first operand has a first precision, and each input value in the set of input values ​​has a second precision lower than the first precision; Receive a second operand obtained by combining a set of weight values ​​of the neural network, wherein each weight value in the set of weight values ​​corresponds to a corresponding input value in the set of input values; and The first operand is multiplied by the second operand to produce a product, the product comprising multiple weighted values ​​of the neural network that are equal to a plurality of different multiplication operations, wherein each of the plurality of weighted values ​​is equal to one of the plurality of different multiplication operations, the multiplication operation being based on a weighted value from the set of weighted values ​​and an input value from the set of input values ​​corresponding to the weighted value.

14. The method of claim 13, further comprising determining a plurality of accumulated values, wherein, Each of the plurality of accumulated values ​​is determined at least in part based on the corresponding weighted value among the plurality of weighted values.

15. The method according to claim 13 or 14, wherein, The first precision is 18 bits, and the second precision is between 1 bit and 6 bits.

16. The method according to claim 13 or 14, wherein, The first operand includes a gap between a first input value in the set of input values ​​and a second input value in the set of input values ​​to prevent or reduce overflow in the plurality of weighted values.

17. The method of claim 13 or 14, further comprising performing a correction operation to correct any conflicts arising from the multiplication operation, wherein, The correction operations include XOR operations, masking operations, or any combination thereof.

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