Method for testing ion implantation diffusion distance of tellurium-cadmium-mercury mesa junction
By photolithographically etching high-precision markings and mesa patterns on the mercury cadmium telluride infrared detector chip and performing IV testing, the problems of quantification of ion diffusion behavior and process monitoring lag were solved, achieving efficient process verification and cost control.
Patent Information
- Application Number
- CN202510740971.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-05
- Publication Date
- 2025-11-14
AI Technical Summary
In p-on-n structure mercury cadmium telluride infrared detectors, ion implantation diffusion behavior is difficult to quantify and predict, leading to inaccurate mesa design, lag in process monitoring, and difficulty in quantifying diffusion parameters. This results in low efficiency, high cost, and low tape-out success rate of traditional process development methods.
An ion implantation diffusion distance test method for mercury cadmium telluride mesa junctions was adopted. A mesa array was prepared by photolithography of high-precision alignment marks and multi-size mesa patterns on the chip. Ion implantation diffusion distance test patterns were then photolithographically ...
Real-time monitoring and quantitative analysis of ion diffusion were achieved, which improved the positive feedback efficiency of process design, shortened the process debugging cycle, reduced the cost of fabrication, and increased the success rate of fabrication.
Smart Images
Figure CN120954992A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of photoelectric detection technology, and in particular to a method for measuring the ion implantation diffusion distance of a mercury cadmium telluride mesa junction. Background Technology
[0002] In p-on-n structured mercury cadmium telluride (HgCdTe) infrared detectors, heterostructures are typically formed through ion implantation, and pixels are separated by mesa structures to obtain highly uniform individual pixels. Thanks to its excellent process consistency, this technology has become the preferred method for fabricating high-performance infrared detectors. However, during device fabrication, HgCdTe materials require multi-stage heat treatment (including annealing, passivation, etc.), and implanted ions are prone to lateral / vertical migration, leading to the following technical bottlenecks: 1. Inaccurate mesa design: Ion diffusion behavior is difficult to quantify and predict, leading to insufficient margin in mesa depth or spacing design. If the mesa depth does not cover the lateral diffusion range of ions, it will cause electrical crosstalk between pixels; if the mesa depth / spacing is excessively increased, it will reduce device integration density and quantum efficiency. Current designs rely on empirical parameters and lack a real-time feedback mechanism for diffusion distance.
[0003] 2. Lag in process monitoring: The current process monitoring system can only verify the rationality of process parameters for a single design after the device is fully fabricated (such as after metallization and packaging) during the IV characteristic testing stage. The process debugging cycle is too long and the efficiency is low.
[0004] 3. Difficulty in quantifying diffusion parameters: There is a lack of quantitative characterization methods for ion diffusion depth and lateral expansion. Among related technologies, secondary ion mass spectrometry detection method has a measurement error of 20% and cannot achieve in-situ monitoring.
[0005] The aforementioned limitations result in a low wafer fabrication success rate, high process verification costs, long process development cycles, and low wafer yield due to the traditional "trial and error" process development model. Summary of the Invention
[0006] This invention provides a method for testing the ion implantation diffusion distance of mercury cadmium telluride mesa junctions, which solves the problems of difficulty in quantifying diffusion parameters, lag in process monitoring, and inability to monitor in situ in the ion implantation diffusion distance testing of mercury cadmium telluride mesa junctions.
[0007] To achieve the above objectives, this application adopts the following technical solution: A method for measuring the ion implantation diffusion distance of a mercury cadmium telluride mesa junction is provided, including: High-precision alignment marks and multi-size mesa patterns were photolithographically etched onto the ion-implanted mercury cadmium telluride chip to prepare a mesa array. A passivation layer is deposited on the chip, and the chip is activated by an annealing process; A test unit is fabricated by photolithographically lithographically forming an ion implantation diffusion distance test pattern structure on a passivation layer; wherein the ion implantation diffusion distance test pattern structure includes: gradient size markings, contact hole patterns, electrode test patterns, and ground electrode patterns; the test unit includes test electrodes and ground electrodes for forming an IV test circuit; The test probes of the test equipment are connected to the corresponding test electrode and ground electrode to perform IV testing. The IV results are observed through the test electrodes to distinguish the diffusion of ion implantation during the process.
[0008] In a first possible implementation, the high-precision alignment mark is used to achieve sub-micron level overlay alignment and observation of lithographic offset.
[0009] Based on the first possible implementation, in the second possible implementation, the high-precision alignment mark is a crosshair alignment mark, and the number of such marks is at least two sets; each set of the high-precision alignment mark includes at least one of the crosshair alignment marks.
[0010] In a third possible implementation, the gradient size markers include multiple size numerical identifiers arranged in a tabular pattern.
[0011] Based on the third possible implementation, in the fourth possible implementation, multiple sets of test unit patterns consisting of multi-size mesa array patterns, contact hole patterns and electrode test patterns are arranged in the order corresponding to the gradient size markings. The multi-size tabletop graphic is used to identify tabletop size parameters and different tabletop spacings, and includes a combination array of at least two tabletop spacings and at least two tabletop sizes; A set of contact hole patterns is set at the center of each test unit pattern; The contact hole pattern corresponds one-to-one with the electrode test pattern and is connected, and is arranged opposite to each other on both sides of the multi-size platform pattern.
[0012] Based on the fourth possible implementation, in the fifth possible implementation, the contact hole pattern is located at the center of two opposing platform patterns in the center of the multi-size platform array pattern.
[0013] Based on the fourth possible implementation, in the sixth possible implementation, the test electrode is used to connect to the test probe of the test equipment to perform IV testing; The ground electrode pattern is a ring structure that surrounds the edge of the entire test pattern structure.
[0014] Based on the sixth possible implementation, in the seventh possible implementation, the electrode test pattern includes a rectangular portion and a strip connecting portion, the strip connecting portion being connected to the contact hole pattern; the electrode test pattern is symmetrically distributed along the length direction of the multi-size mesa array pattern array.
[0015] In the eighth possible implementation, the fabrication of the test unit by photolithographically lithographically implanting ion diffusion distance testing pattern structure on the passivation layer specifically includes: Contact hole patterns are photolithographically patterned on the passivation layer, and contact holes are fabricated on the mesa. A predetermined amount of metal is deposited inside the contact hole; A test electrode is fabricated by photolithography of an electrode test pattern and deposition of metal in a passivation layer; the test electrode is electrically connected to the contact hole. Gradient size markings and ground electrode patterns are photolithographically applied to the passivation layer, and the ground electrode is then fabricated.
[0016] The present invention has the following advantages: This application performs special patterning on the ion-implanted chip, observes the presence of junction regions in the IV results to analyze the diffusion of ion implantation during the process, and provides timely feedback. This not only confirms the appropriateness of the ion implantation dose before formal tape-out but also assesses the rationality of the tape-out process within the existing design after dose confirmation, allowing for timely positive feedback on the chip design. Furthermore, it can predict the process effects of tape-outs with different mesa sizes and spacings under the same process conditions using a single tape-out, and adjust the chip design and implantation dose based on the test results. This provides a simpler and more intuitive method for evaluating chip forward design and process adjustments.
[0017] Based on this, the rationality of the current process design can be determined by fabricating a single chip in the same batch before testing in device packaging, overcoming the problem of process verification lag. A test pattern structure compatible with standard process lines has been developed, enabling simultaneous measurement of ion lateral diffusion (∆L) and longitudinal diffusion depth (∆D) under the same process conditions. Test results are fed back in a timely manner to optimize existing designs, resolving the problem of design mismatch. Process verification can be performed through a single fabrication, compressing the process debugging cycle, effectively saving fabrication costs, improving process verification efficiency, and rapidly optimizing existing processes, thus solving the cost control problem. In-situ chip monitoring has been achieved. Attached Figure Description
[0018] Figure 1 A schematic flowchart illustrating an ion implantation diffusion distance test method for a mercury cadmium telluride mesa junction provided in this application embodiment; Figure 2A schematic diagram of an ion implantation diffusion distance test pattern for a mercury cadmium telluride mesa junction provided in an embodiment of this application; Figure 3 This is a schematic diagram of a test unit graphic provided in an embodiment of this application.
[0019] Figure label: High-precision alignment mark 1, gradient size mark 2, multi-size platform pattern 3, contact hole pattern 4, electrode test pattern 5, ground electrode pattern 6. Detailed Implementation
[0020] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the technical solutions in the embodiments of this application are clearly described. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.
[0021] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0022] The steps described in the specification and the flowcharts in the accompanying drawings of this invention are not necessarily strictly executed according to the step numbers; the execution order of the method steps can be changed. Furthermore, certain steps can be omitted, multiple steps can be combined into one step, and / or one step can be broken down into multiple steps.
[0023] The following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the ion implantation diffusion distance test of the mercury cadmium telluride mesa junction provided in this application.
[0024] To address the issues of blind spots in ion diffusion monitoring, difficulties in quantifying diffusion parameters, lag in process monitoring, and inability to monitor in situ in existing HgCdTe infrared detector manufacturing processes, the traditional "trial and error" process development model results in low wafer fabrication success rates and high process verification costs. There is an urgent need to develop a real-time monitoring method compatible with standard process lines to achieve dynamic tracking and quantitative analysis of ion diffusion behavior, providing timely positive feedback to process design or chip design, improving fabrication efficiency, increasing chip fabrication success rates, and establishing a feedback optimization mechanism between process parameters and device performance.
[0025] See Figure 1 This application provides a method for testing the ion implantation diffusion distance of a mercury cadmium telluride mesa junction, comprising the following steps: Step S1 involves photolithographically etching high-precision alignment marks 1 and multi-sized mesa patterns 3 onto the ion-implanted mercury cadmium telluride chip to prepare a mesa array. Mesa patterns of a certain depth can be obtained through etching or corrosion.
[0026] Step S2: Deposit a passivation layer on the chip and activate the chip through an annealing process.
[0027] Step S3: Photolithographically etch an ion implantation diffusion distance test pattern structure on the passivation layer to prepare a test unit; wherein, the ion implantation diffusion distance test pattern structure includes: gradient size marker 2, contact hole pattern 4, electrode test pattern 5, and ground electrode pattern 6; the test unit includes a test electrode and a ground electrode for forming an IV test circuit.
[0028] Specifically, see Figure 2-3 The high-precision alignment mark 1 is used to achieve sub-micron level overlay alignment and observation of lithographic offset. The gradient size marker 2 includes multiple size numerical identifiers arranged in a tabular pattern; Multiple test unit patterns, consisting of the multi-size mesa array pattern 3, contact hole pattern 4, and electrode test pattern 5, are arranged sequentially according to the gradient size mark 2. The multi-size tabletop graphic 3 is used to identify tabletop size parameters and different tabletop spacings, and includes a combination array of at least two tabletop spacings and at least two tabletop sizes; A set of contact hole patterns 4 is provided at the center of each test unit; The contact hole pattern 4 corresponds one-to-one with the electrode test pattern 5 and is connected, and is arranged opposite to each other on both sides of the multi-size platform pattern 3; The test electrode is used to connect to the test probe of the test equipment for IV testing; The ground electrode pattern 6 is a ring structure that surrounds the edge of the entire test pattern structure.
[0029] Furthermore, the high-precision alignment mark 1 is a cross alignment mark, and there are at least two sets of them; each set of the high-precision alignment mark 1 includes at least one of the cross alignment marks.
[0030] Furthermore, the contact hole pattern 4 is positioned at the center of two opposing platform patterns in the center of the multi-size platform array pattern 3.
[0031] Furthermore, the electrode test pattern 5 includes a rectangular portion and a strip connecting portion, the strip connecting portion being connected to the contact hole pattern 4; the electrode test pattern 5 is symmetrically distributed along the length direction of the multi-size mesa array pattern 3 array.
[0032] Furthermore, the fabrication of the test unit by photolithographically lithographically implanting ion diffusion distance testing pattern structure on the passivation layer specifically includes the following steps: Step S31: Photolithographically pattern the contact hole pattern 4 on the passivation layer and fabricate the contact hole on the mesa. The contact hole can be formed on the mesa by etching or corrosion.
[0033] Step S32: Deposit a predetermined amount of metal into the contact hole. Protect the contact hole.
[0034] Step S33: Photolithographically pattern the electrode test pattern 5 on the passivation layer and deposit metal to prepare the test electrode; the test electrode is electrically connected to the contact hole. The test electrode can be formed by methods such as peeling, etching, or etching.
[0035] In step S34, gradient size marking 2 and ground electrode pattern 6 are photolithographically formed on the passivation layer, and the ground electrode is fabricated.
[0036] Step S4: Connect the test probe of the test equipment to the corresponding test electrode and ground electrode to perform IV test. Observe the IV results through the test electrode to distinguish the diffusion of ion implantation in the process.
[0037] In practical implementation, the high-precision alignment mark 1 can include a cross alignment mark to achieve sub-micron level overlay accuracy. Real-time feedback of lithographic offset can be obtained through microscopic observation, facilitating alignment in subsequent steps. The gradient size mark 2, for easy differentiation during testing, has corresponding dimensions marked on each box. This marking facilitates observation and analysis of ion implantation diffusion under different mesa spacings and mesa sizes. This design supports direct determination of mesa deformation parameters under an optical microscope. The gradient size mark 2 is formed in the electrode test pattern step 5, and the intuitive size markings facilitate data recording and organization during testing. In the multi-size mesa array pattern 3 design, this testing method integrates multiple mesa spacings and sizes, requiring only a single fabrication run to obtain all diffusion information. The fabrication cycle is short, process consistency is high, and results can be fed back promptly. The contact hole size is consistent, allowing control of variables during fabrication so that differences only appear in mesa spacing and mesa size. The electrode test pattern 5 and the symmetrical design of the test electrodes allow the probes of a semiconductor parameter analyzer or other testing equipment to contact the two sets of test electrodes, judging the diffusion after ion implantation based on the IV test results. IV testing provides a direct visual indication of the presence of junction regions. Furthermore, during IV testing, one end is connected to the ground electrode, and the other end to the test electrode, allowing for quantitative measurement of the photoelectric performance of a single mesa as a reference value.
[0038] This application performs special patterning on the ion-implanted chip, observes the presence of junction regions in the IV results to analyze the diffusion of ion implantation during the process, and provides timely feedback. This not only confirms the appropriateness of the ion implantation dose before formal tape-out but also assesses the rationality of the tape-out process within the existing design after dose confirmation, allowing for timely positive feedback on the chip design. Furthermore, it can predict the process effects of tape-outs with different mesa sizes and spacings under the same process conditions using a single tape-out, and adjust the chip design and implantation dose based on the test results. This provides a simpler and more intuitive method for evaluating chip forward design and process adjustments.
[0039] Based on this, the rationality of the current process design can be determined by fabricating a single chip in the same batch before testing in device packaging, overcoming the problem of process verification lag. A test pattern structure compatible with standard process lines has been developed, enabling simultaneous measurement of ion lateral diffusion (∆L) and longitudinal diffusion depth (∆D) under the same process conditions. Test results are fed back in a timely manner to optimize existing designs, resolving the problem of design mismatch. Process verification can be performed through a single fabrication, compressing the process debugging cycle, effectively saving fabrication costs, improving process verification efficiency, and rapidly optimizing existing processes, thus solving the cost control problem. In-situ monitoring has been achieved.
[0040] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
[0041] It is understood that the embodiments of this application have been described above in conjunction with the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. As those skilled in the art will know, various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, those skilled in the art, under the guidance or instruction of this application, can modify these features and embodiments to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of this invention.
Claims
1. A method for measuring the ion implantation diffusion distance of a mercury cadmium telluride mesa junction, characterized in that, include: High-precision alignment marks and multi-size mesa patterns were photolithographically etched onto the ion-implanted mercury cadmium telluride chip to prepare a mesa array. A passivation layer is deposited on the chip, and the chip is activated by an annealing process; A test unit is fabricated by photolithographically lithographically forming an ion implantation diffusion distance test pattern structure on a passivation layer; wherein the ion implantation diffusion distance test pattern structure includes: gradient size markings, contact hole patterns, electrode test patterns, and ground electrode patterns; the test unit includes test electrodes and ground electrodes for forming an IV test circuit; The test probes of the test equipment are connected to the corresponding test electrode and ground electrode to perform IV testing. The IV results are observed through the test electrodes to distinguish the diffusion of ion implantation during the process.
2. The method for testing the ion implantation diffusion distance of a mercury cadmium telluride mesa junction according to claim 1, characterized in that, The high-precision alignment mark is used to achieve sub-micron level overlay alignment and observation of lithographic offset.
3. The method for testing the ion implantation diffusion distance of a mercury cadmium telluride mesa junction according to claim 2, characterized in that, The high-precision alignment marks are crosshair alignment marks, and there are at least two sets of them; each set of the high-precision alignment marks includes at least one of the crosshair alignment marks.
4. The method for testing the ion implantation diffusion distance of a mercury cadmium telluride mesa junction according to claim 1, characterized in that, The gradient size markers include multiple size numerical identifiers arranged in a tabular pattern.
5. The method for testing the ion implantation diffusion distance of a mercury cadmium telluride mesa junction according to claim 4, characterized in that, The gradient size markings correspond to multiple sets of test unit patterns, which are composed of multi-size mesa array patterns, contact hole patterns, and electrode test patterns. The multi-size tabletop graphic is used to identify tabletop size parameters and different tabletop spacings, and includes a combination array of at least two tabletop spacings and at least two tabletop sizes; A set of contact hole patterns is set at the center of each test unit pattern; The contact hole pattern corresponds one-to-one with the electrode test pattern and is connected, and is arranged opposite to each other on both sides of the multi-size platform pattern.
6. The method for testing the ion implantation diffusion distance of a mercury cadmium telluride mesa junction according to claim 5, characterized in that, The contact hole pattern is located at the center of two opposing platform patterns in the center of the multi-size platform array pattern.
7. The method for testing the ion implantation diffusion distance of a mercury cadmium telluride mesa junction according to claim 5, characterized in that, The test electrode is used to connect to the test probe of the test equipment for IV testing; The ground electrode pattern is a ring structure that surrounds the edge of the entire test pattern structure.
8. The method for testing the ion implantation diffusion distance of a mercury cadmium telluride mesa junction according to claim 7, characterized in that, The electrode test pattern includes a rectangular portion and a strip connecting portion, the strip connecting portion being connected to the contact hole pattern; the electrode test pattern is symmetrically distributed along the length direction of the multi-size platform array pattern array.
9. The method for testing the ion implantation diffusion distance of a mercury cadmium telluride mesa junction according to claim 1, characterized in that, The aforementioned method of fabricating a test unit by photolithography of an ion implantation diffusion distance test pattern on a passivation layer specifically includes: Contact hole patterns are photolithographically patterned on the passivation layer, and contact holes are fabricated on the mesa. A predetermined amount of metal is deposited inside the contact hole; A test electrode is fabricated by photolithography of an electrode test pattern and deposition of metal in a passivation layer; the test electrode is electrically connected to the contact hole. Gradient size markings and ground electrode patterns are photolithographically applied to the passivation layer, and the ground electrode is then fabricated.