Data pulse width detection circuit

Abstract

The invention discloses a data pulse width detection circuit which comprises an input pulse interface circuit, a waveform conversion circuit, a delay adjustment circuit and a pulse width decision circuit. The input end of the input pulse interface circuit is connected with external trigger pulse input, the output end A is connected with the data input end D of the pulse width decision circuit, and the output end B is connected with the input end of the waveform conversion circuit; the input end of the waveform conversion circuit is connected with the output end B of the input pulse interface circuit, and the output end is connected with the input end of the delay adjustment circuit; the input end of the delay adjustment circuit is connected with the output end of the waveform conversion circuit, and the output end is connected with the CLK of the pulse width decision circuit; a data input end D of the pulse width decision circuit is connected with an output end A of the input pulse interface circuit, CLK is connected with an output end of the delay adjustment circuit, and an output end Q is connected with pulse width decision output. According to the invention, the transmission delay is slightly influenced by temperature, the detected pulse width is 20-100ns, the detection precision is + / -4ns, the fixed time delay change at 0-40 DEG C is less than or equal to 400ps, and the pulse rising edge jitter is less than or equal to 200ps.

Description

Technical Field

[0001] This invention belongs to the field of data pulse width detection technology, and specifically relates to a data pulse width detection circuit. Background Technology

[0002] In some distributed multi-node data control systems, data trigger pulses are transmitted from the root of the control system down to each lower-level node. Each lower-level node needs to transmit the data trigger pulses to its respective lower-level node at the required time. Data trigger pulses may be subject to interference and changes in ambient temperature during transmission, resulting in time transmission errors. To eliminate interference and ensure the validity and synchronization of data trigger pulses, each node is often required to first determine the pulse width of the received data trigger pulses. Pulse widths greater than the specified requirements are considered data trigger pulses, while those smaller than the specified requirements are considered interference. At the same time, the transmission of each node needs to have a fixed transmission delay, a fast and low-jitter rising edge to ensure the time accuracy of data trigger pulse transmission.

[0003] There are many commonly used methods for detecting data pulse width, such as counting methods and hardware circuit delay methods. The counting method uses a high-speed clock to count the data pulse width. The delay of the pulse width detection circuit and the jitter of the output pulse edge are affected by the clock frequency and whether the clock and the data trigger pulse are synchronized. If the data trigger pulse and the counting clock are asynchronous, the jitter of the data trigger pulse edge is one counting clock cycle. The hardware circuit delay method uses delay lines, gate circuits, RC circuits, etc. For pulse width delays of tens of ns, the hardware circuit transmission delay is affected by temperature. Temperature drift affects the stability of the transmission delay time and the pulse edge jitter of the data trigger pulse. For pulse widths of tens of ns, in the range of 0℃ to 50℃, the transmission delay time stability is about 1 ns, and the pulse edge jitter is about several hundred ps. If the transmission delay variation is required to be less than 300 ps and the pulse edge jitter less than 200 ps, ​​it is quite difficult to achieve. Taking constant temperature measures can effectively overcome the temperature effect, but the circuit is relatively complex and has a certain delay or discontinuity, making it unsuitable for applications with high synchronization and precision requirements. Summary of the Invention

[0004] The purpose of this invention is to provide a data pulse width detection circuit for detecting the width of positive pulses; it solves to a certain extent the problem that the transmission delay of the detection circuit in the prior art is affected by temperature. The data pulse width detection circuit of this invention detects a pulse width of 20ns to 100ns, with a detection accuracy of ±4ns, a fixed delay variation of ≤400ps at 0℃ to 40℃, and a pulse rise edge jitter of ≤200ps.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A data pulse width detection circuit includes an input pulse interface circuit, a waveform transformation circuit, a delay adjustment circuit, and a pulse width decision circuit. The input terminal IN of the input pulse interface circuit is connected to an external trigger pulse input, its output terminal A is connected to the data input terminal D of the pulse width decision circuit, and its output terminal B is connected to the input terminal of the waveform transformation circuit. The input terminal of the waveform transformation circuit is connected to the output terminal B of the input pulse interface circuit, and its output terminal is connected to the input terminal of the delay adjustment circuit. The input terminal of the delay adjustment circuit is connected to the output terminal of the waveform transformation circuit, and its output terminal is connected to the clock input terminal CLK of the pulse width decision circuit. The data input terminal D of the pulse width decision circuit is connected to the output terminal A of the input pulse interface circuit, its clock input terminal CLK is connected to the output terminal of the delay adjustment circuit, its output terminal Q is connected to the pulse width decision output, and its reset input / CLR is connected to an external reset signal input.

[0007] Preferably, this solution includes an interface chip U1, a low-noise, low-temperature-drift precision broadband amplifier U2, a high-speed voltage comparator U3, and a D flip-flop U4. An external digital positive pulse width detection signal is input from J1, matched by resistor R1, and then connected to the positive input terminal of the interface chip U1. The detection signal is shaped by the interface chip U1 into a fast-rising-edge data pulse. The data pulse is output in two paths: one path, without delay, is connected to the data input terminal D of the D flip-flop U4 via resistor R3; the other path is input to the positive input terminal of the low-temperature-drift precision broadband amplifier U2 via resistor R2 for first-stage in-phase amplification. The sawtooth wave output from the low-noise, low-temperature-drift precision broadband amplifier U2 is input to the positive input terminal of the high-speed voltage comparator U3 after passing through a voltage divider network composed of high-speed diode D1 and resistors R8, R9, and R10. The negative input terminal of the high-speed voltage comparator U3 is connected to a variable potentiometer RP1. The output of high-speed voltage comparator U3 is connected to the clk terminal of D flip-flop U4. When / CLR is at a "0" level, the rising edge of the trigger clock clk of D flip-flop U4 reads the level of the data input D. When the D flip-flop is working ( / CLR=1 level), if the output Q of D flip-flop U4 is "1", it means that the width of the input pulse signal is greater than or equal to the delay time of the trigger clock clk, which is a data trigger pulse; if the output Q of D flip-flop U4 is "0", it means that the width of the input pulse signal is less than the delay time of the trigger clock clk, which is an interference pulse that is not a data trigger signal.

[0008] Preferably, the input pulse interface circuit uses the LINEAR LTC6957-3 interface chip, with the following main parameters: power supply voltage 3.15V~3.45V, operating frequency DC~300MHz, input signal level TTL\CMOS\CML\LVPECL\sine wave, output level CMOS, minimum pulse width 0.6ns, output amplitude high level VCC-0.1V, output amplitude low level 0.1V, transmission delay temperature drift 1.7ps / ℃, A and B output delay consistency 5ps, pulse rise time ≤320ps, and additional jitter ≤200fs.

[0009] Preferably, the waveform conversion circuit is a low-noise, low-temperature-drift precision broadband amplifier circuit, using a National LMH6622 dual-channel low-noise broadband voltage feedback amplifier. Its main parameters are: power supply voltage of ±2.5V to ±6V for dual power supplies or 5V to 12V for a single power supply; bandwidth of 160MHz when gain Av=+2; slew rate of 0.85V / 10ns; input offset voltage of 0.2mV; input temperature drift of -2.5uV / ℃; input common-mode voltage range of -4.75V to 5.7V@power supply ±6V; output swing (no load) of ±5V@power supply ±6V; maximum linear output current of 90mA; and harmonic distortion of 90dBc.

[0010] Preferably, the delay adjustment circuit is a high-speed voltage comparator circuit, using the TI TLV3601 high-speed voltage comparator; the main parameters are: power supply voltage 2.4V~5.5V, switching frequency 325MHz, minimum detection pulse width 1.25ns, propagation delay 2.5ns, input common mode range is rail-to-rail input, output offset voltage ±0.5mV, output is TTL level, rise time 0.75ns, jitter 4ps.

[0011] Preferably, the pulse width decision circuit is a high-speed D flip-flop circuit, using the TI SN74LVC2G74 D flip-flop. The data input D of the D flip-flop is a pulse signal without delay, and the clock CLK is a TTL pulse output after being determined by the delay adjustment circuit. The main parameters are: power supply voltage 1.65V~5.5V, operating frequency 200MHz, input "1" level ≥0.7*Vcc, input "0" level ≤0.3*Vcc, output voltage 0~Vcc, and CLK read D to Q output propagation delay 1.4ns@Vcc=5V.

[0012] Compared with the prior art, the present invention has the following advantages:

[0013] 1. The transmission delay of the detection circuit of the present invention is less affected by temperature. Its detection pulse width is 20ns to 100ns, the detection accuracy is ±4ns, the fixed delay variation at 0℃ to 40℃ is ≤400ps, and the pulse rise edge jitter is ≤200ps. Its synchronization and detection accuracy are improved, and it can be applied to synchronous transmission in master-slave architecture systems.

[0014] 2. In this invention, the externally input data triggers a positive pulse. First, the input pulse interface circuit shapes the data trigger pulse with an uncertain rise rate into a positive pulse with a very fast rise rate. Then, it is output synchronously in two channels. One pulse is not delayed, and the other pulse is delayed according to the required pulse width time. The output time of the delayed pulse's rising edge is used to judge the level of the undelayed pulse. If the undelayed pulse is at a "1" level, it means that the input pulse width is greater than the required pulse width, and it is a data trigger pulse. If the undelayed pulse is at a "0" level, it means that the input pulse width is less than the required pulse width, and it is an interference pulse that is not a data trigger signal. Attached Figure Description

[0015] Figure 1 This is a functional block diagram of a data pulse width detection circuit according to the present invention.

[0016] Figure 2 This is a circuit diagram of a data pulse width detection circuit according to the present invention.

[0017] Figure 3 The waveform output diagrams for test points A, B, and C are shown when the input pulse width is 20ns.

[0018] Figure 4 The waveform output diagrams for test points A, B, and C are shown when the input pulse width is 50ns.

[0019] Figure 5 The waveform output diagrams for test points A, B, and C are shown when the input pulse width is 1100ns.

[0020] Figure 6 The waveforms at each test point from the pulse input to the width detection output are shown. Detailed Implementation

[0021] To make the objectives and advantages of the present invention clearer, the present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] like Figure 1As shown, this invention discloses a data pulse width detection circuit, comprising an input pulse interface circuit, a waveform transformation circuit, a delay adjustment circuit, and a pulse width decision circuit. The input terminal IN of the input pulse interface circuit is connected to an external trigger pulse input, its output terminal A is connected to the data input terminal D of the pulse width decision circuit, and its output terminal B is connected to the input terminal of the waveform transformation circuit. The input terminal of the waveform transformation circuit is connected to the output terminal B of the input pulse interface circuit, and its output terminal C is connected to the input terminal of the delay adjustment circuit. The input terminal of the delay adjustment circuit is connected to the output terminal C of the waveform transformation circuit, and its output terminal is connected to the clock input terminal CLK of the pulse width decision circuit. The data input terminal D of the pulse width decision circuit is connected to the output terminal A of the input pulse interface circuit, its clock input terminal CLK is connected to the output terminal of the delay adjustment circuit, its output terminal Q is connected to the pulse width decision output, and its reset input / CLR is connected to an external reset signal input.

[0023] As a preferred embodiment, such as Figure 2As shown, a data pulse width detection circuit includes an interface chip U1, a low-temperature drift, low-noise precision broadband voltage amplifier U2, a high-speed voltage comparator U3, and a D flip-flop U4. The external digital positive pulse width detection signal is input from J1, matched by resistor R1, and then input to the interface chip U1. After being shaped by the interface chip U1, the detected signal becomes a fast-rising-edge data pulse with an output amplitude of 0–3.3V. The data pulse is output in two paths: one path, without delay, is connected to the data input terminal D of the D flip-flop U4 via resistor R3; the other path, via resistor R2, is input to the low-temperature drift, precision low-noise operational amplifier U2 for in-phase amplification with a gain of 4. After amplification, the data pulse signal is limited by the rise rate of amplifier U2, becoming a sawtooth wave with a rise slope of 0.85V / 10ns (the slew rate of U2 is 0.85V / 10ns). The rising edge of the data pulse from input amplifier U2 is defined as t=0. At t=0, the amplitude of the sawtooth wave output by feedback amplifier U2 is 0V. When the data pulse signal remains high, the sawtooth wave amplitude is 0.85V at t=10ns, 8.5V at t=100ns, and 9V at t=105ns. 9V is the amplifier's output saturation amplitude, which is the amplifier's maximum output amplitude. If the pulse width of the input amplifier's data pulse is less than t=105ns, the amplitude of the sawtooth wave output by the amplifier begins to decrease at the falling edge of the data pulse, with a decrease slope of approximately -0.85V / 10ns, until it drops to 0V. The sawtooth wave output by amplifier U2 is input to the positive input terminal of high-speed comparator U3 after passing through a voltage divider network composed of high-speed diode D1 and resistors R8, R9, and R10. The input amplitude is approximately 0–4.5V, with a rising slope of 0.425V / 10ns. The negative input terminal of comparator U3 is connected to a variable potentiometer RP1. Adjusting RP1 adjusts the negative input voltage (VREF). The level VREF of the negative input terminal is adjusted according to the required pulse width. Considering that the high-speed comparator U3 has a propagation delay of 2.5ns, the negative input level VREF ranges from 0.32V to 4.5V, corresponding to a pulse delay of 10ns to 105ns. The output of comparator U3 is connected to the clk of D flip-flop U4. When the D flip-flop is working (reset input / CLR=1), the rising edge of clk of U4 reads the level of the D input. After the external Q output is detected to be high, the reset signal is used to reset the device, waiting for the next pulse width detection. Figures 3-5 The waveform output diagrams are for the low-temperature drift precision low-noise voltage feedback amplifier U2 with input pulse widths of 20ns, 50ns, and 110ns. Figure 6The waveforms at each test point from the pulse input to the width detection output are shown. The delay time from the input pulse to test point A and test point B is the propagation delay of chip U1. Test point C is the output waveform of the waveform conversion circuit. The waveform at test point CLK is the output waveform when the delay adjustment circuit U3in- is set to Vref. The delay time of this waveform corresponds to the pulse width of the decision. This width is equal to the decision time of U3 level Vref plus the propagation delay of the high-speed voltage comparator U3 itself, which is about 2.5ns. When the reset input ( / CLR) is "1", the output waveform at test point Q is "1", and the output time is td4 later than that at test point CLK. td4 is the propagation delay of the D flip-flop. When the reset input ( / CLR) is "0", the D flip-flop is reset, and the waveform at test point Q is "0". When the reset input ( / CLR) is "1" again, it waits for one pulse width decision.

[0024] The input pulse interface circuit uses the LINEAR LTC6957-3 interface chip; its main parameters are: power supply voltage 3.15V~3.45V, operating frequency DC~300MHz, input signal level TTL\CMOS\CML\LVPECL\sine wave, output level CMOS, minimum pulse width 0.6ns, output amplitude high level VCC-0.1V, output amplitude low level 0.1V, transmission delay temperature drift 1.7ps / ℃, A and B output delay consistency 5ps, pulse rise time ≤320ps, and additional jitter ≤200fs.

[0025] The waveform conversion circuit is a low-noise, low-temperature drift precision broadband amplifier circuit, using a National LMH6622 dual-channel low-temperature drift precision low-noise broadband voltage feedback amplifier with a voltage amplification gain of 4. The main parameters of the amplifier are: power supply voltage of ±2.5V to ±6V for dual power supply or 5V to 12V for single power supply; bandwidth of 160MHz when gain Av=+2; slew rate of 0.85V / 10ns; input offset voltage of 0.2mV; input temperature drift of -2.5uV / ℃; input common-mode voltage range of -4.75V to 5.7V@power supply ±6V; output swing (no load) of ±5V@power supply ±6V; maximum linear output current of 90mA; and harmonic distortion of 90dBc.

[0026] The delay adjustment circuit is a high-speed voltage comparator circuit, using a TI TLV3601 comparator. Its main parameters are: power supply voltage 2.4V~5.5V, switching frequency 325MHz, minimum detection pulse width 1.25ns, propagation delay 2.5ns, input common-mode range rail-to-rail input, input offset voltage ±0.5mV, output TTL level, rise time 0.75ns, and jitter 4ps.

[0027] The pulse width decision circuit is a high-speed D flip-flop circuit, using the TI SN74LVC2G74 D flip-flop. The data input D of the D flip-flop is a pulse signal without delay, and the clock CLK is a TTL pulse output after being determined by the delay adjustment circuit. The main parameters are: power supply voltage 1.65V~5.5V, operating frequency 200MHz, input "1" level ≥0.7*Vcc, input "0" level ≤0.3*Vcc, output voltage 0~Vcc, and CLK reading from D to Q output transmission delay 1.4ns@Vcc=5V.

[0028] The truth table of the SN74LVC2G74 D flip-flop is shown in Table 1:

[0029]

[0030] The above embodiments are merely specific examples to further illustrate the purpose, technical solution, and beneficial effects of the present invention, and the present invention is not limited thereto. Any modifications, equivalent substitutions, improvements, etc., made within the scope of the disclosure of the present invention are included within the protection scope of the present invention.

Claims

1. A data pulse width detection circuit, characterized in that: This includes an input pulse interface circuit, a waveform transformation circuit, a delay adjustment circuit, and a pulse width decision circuit. The input terminal IN of the input pulse interface circuit is connected to an external trigger pulse input, the output terminal A is connected to the data input terminal D of the pulse width decision circuit, and the output terminal B is connected to the input terminal of the waveform conversion circuit. The input terminal of the waveform transformation circuit is connected to the output terminal B of the input pulse interface circuit, and the output terminal C is connected to the input terminal of the delay adjustment circuit. The input of the delay adjustment circuit is connected to the output C of the waveform conversion circuit, and the output is connected to the clock CLK input of the pulse width decision circuit. The data input terminal D of the pulse width decision circuit is connected to the output terminal A of the input pulse interface circuit, the clock input terminal CLK is connected to the output terminal of the delay adjustment circuit, the output terminal Q is connected to the pulse width decision output, and the reset input / CLR is connected to the external reset signal input.

2. The data pulse width detection circuit according to claim 1, characterized in that: Includes interface chip U1, low-noise, low-temperature drift precision broadband amplifier U2, high-speed voltage comparator U3, and D flip-flop U4; The external digital positive pulse width detection signal is input from J1, matched by resistor R1, and then connected to the positive input terminal of interface chip U1. The detected signal is shaped by interface chip U1 into a fast-rising-edge data pulse. The data pulse is output in two paths: one path, without delay, is connected to the data input terminal D of D flip-flop U4 via resistor R3; the other path is input to the positive input terminal of low-noise, low-temperature-drift precision broadband amplifier U2 via resistor R2 for first-stage in-phase amplification. The sawtooth wave output from low-noise, low-temperature-drift precision broadband amplifier U2 is then input to the positive input terminal of high-speed voltage comparator U3 via a voltage divider network composed of high-speed diode D1 and resistors R8, R9, and R10. The negative input terminal of high-speed voltage comparator U3 is connected to variable potentiometer RP1. The output of high-speed voltage comparator U3 is connected to the clk terminal of D flip-flop U4. When / CLR is at "0", the rising edge of the trigger clock clk of D flip-flop U4 reads the level of the data input D. When D flip-flop U4 is working, if the output Q of D flip-flop U4 is "1", it means that the width of the input pulse signal is greater than or equal to the delay time of the trigger clock clk, which is a data trigger pulse; if the output Q of D flip-flop U4 is "0", it means that the width of the input pulse signal is less than the delay time of the trigger clock clk, which is an interference pulse that is not a data trigger signal.

3. A data pulse width detection circuit according to claim 1 or 2, characterized in that: The input pulse interface circuit uses the LINEAR LTC6957-3 interface chip.

4. A data pulse width detection circuit according to claim 1 or 2, characterized in that: The waveform conversion circuit is a low-noise, low-temperature drift precision broadband amplifier circuit, using a National LMH6622 dual-channel low-noise wideband voltage feedback amplifier with a gain of 4.

5. A data pulse width detection circuit according to claim 1 or 2, characterized in that: The delay adjustment circuit is a high-speed voltage comparator circuit, using a TI TLV3601 comparator.

6. A data pulse width detection circuit according to claim 1 or 2, characterized in that: The pulse width decision circuit is a high-speed D flip-flop circuit, using the TI SN74LVC2G74 D flip-flop. The data input D of the D flip-flop is a pulse signal without delay, and the clock CLK is a TTL pulse output by the delay adjustment circuit.

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