Quick relocking system and method of all-digital phase-locked loop

Abstract

The invention discloses a quick relocking system and method for an all-digital phase-locked loop, and the system comprises a dynamic disturbance evaluation module which is used for determining a disturbance type; the state switching module comprises a locking state storage unit and is used for switching the initial relocking state of the phase-locked loop to a corresponding locking state according to the disturbance type after the loss of lock is detected; the tuning word prediction module comprises a linear relation calculation unit and is used for mapping the current error into a predicted initial tuning word based on a slope factor generated by historical tuning words and error data in a target state stage; the locking process is accelerated by reducing the current locking judgment threshold value; and the cooperative control module comprises a data bus interface and is used for synchronizing the operation time sequence of the dynamic disturbance evaluation module, the state switching module and the tuning word prediction module and writing the predicted initial tuning word into the corresponding oscillator tuning word generation module. According to the invention, the rapid relocking of the whole ADPLL can be realized only by correcting a relatively small frequency error or phase error.

Description

Technical Field

[0001] This invention belongs to the field of all-digital phase-locked loop (ADPLL) technology, and particularly relates to an all-digital phase-locked loop fast relocking control system and method with disturbance classification capability. Background Technology

[0002] When operating normally, an ADPLL maintains frequency and phase synchronization between its output clock and the reference clock, i.e., it is in a locked state. However, due to various disturbances (such as reference clock anomalies, power supply noise, temperature changes, etc.), the ADPLL may lose lock. In this case, the ADPLL re-enters the lock-in process, adjusting its output frequency and phase. This involves processes such as coarse frequency locking, frequency locking, and phase locking to regain synchronization with the reference clock.

[0003] Existing ADPLL locking technology features fast locking of fully digital phase-locked loops with extended tracking range. During phase locking, it reduces the phase locking time of the phase-locked loop through multiple consecutive cascaded steps, such as initial frequency adjustment, coarse frequency adjustment, clock edge alignment, and phase locking. If the lock is lost, the above process must be repeated. The phase-locked loop cannot start working from the middle of the process. Furthermore, it lacks a fast relocking mechanism when the lock is lost due to various disturbances.

[0004] The above background information is provided only to aid in understanding the concept and technical solution of this invention. It does not necessarily belong to the prior art of this patent application. In the absence of clear evidence that the above information was disclosed on the filing date of this patent application, the above background information should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0005] This invention proposes a fast relocking system and method for a fully digital phase-locked loop (PLL), which solves the problem of excessively long relocking time after a loss of lock in an ADPLL, and improves the response speed and stability of the PLL.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A fast relocking system for a fully digital phase-locked loop (PLL) includes: a dynamic disturbance assessment module, including a frequency error and phase error acquisition unit, used to determine the disturbance type as a coarse frequency disturbance, a fine frequency disturbance, or a phase disturbance based on the amplitude of the current frequency error and phase error; a state switching module, including a locked state storage unit, used to switch the initial relocking state of the PLL to the corresponding locked state among automatic frequency control state, frequency locked state, or phase locked state according to the disturbance type after a loss of lock is detected; a tuning word prediction module, including a linear relationship calculation unit, used to map the current error to a predicted initial tuning word based on a slope factor generated from historical tuning words and error data within the target state stage; the tuning word prediction module further includes a threshold dynamic adjustment unit, which accelerates the locking process by reducing the current locking judgment threshold when the predicted initial tuning word is in the vicinity of the target state tuning word range; and a cooperative control module, including a data bus interface, used to synchronize the operation timing of the dynamic disturbance assessment module, the state switching module, and the tuning word prediction module, and write the predicted initial tuning word into the corresponding oscillator tuning word generation module.

[0007] In some embodiments, the following technical features are also included: The dynamic disturbance assessment module includes a disturbance assessment component integrated in a digital comparator, which implements the frequency error threshold comparison function through hardware logic circuits; the threshold dynamic adjustment unit includes a threshold dynamic configuration component connected to the lock judgment module, which has a programmable gain parameter interface.

[0008] In some embodiments, the following technical features are also included: The locked state also includes the initial frequency adjustment state, coarse frequency adjustment state, or clock edge alignment state described in the background art. The system further includes a state memory component that stores the tuning word, frequency error, and phase error datasets for each locked stage. The linear operation component, including a multiplier accumulator and a shift register, performs calculations of the product of the slope factor and the real-time frequency error or phase error.

[0009] In some embodiments, the following technical features are also included: In the disturbance classification logic of the dynamic disturbance assessment module, the judgment condition for coarse frequency disturbances is FE. n > FE afc The criterion for determining fine frequency perturbations is FE. afc ≥ FE n > FE fl The condition for determining phase perturbation is FE. n ≤ FE fl , of which FE n For the frequency error under the current disturbance, FE afcFor the frequency lock-in error threshold during the automatic frequency control phase, FE fl This is the frequency locking error threshold during the frequency locking phase.

[0010] In some embodiments, the following technical features are also included: The slope factor is calculated as K = (OTW) n -OTW m ) / (E n -E m ), of which OTW n OTW m E represents the oscillator tuning word in the nth and mth control cycles within the target state phase, respectively. n E m This refers to the frequency error or phase error corresponding to the period.

[0011] In some embodiments, the following technical features are also included: Piecewise linearization is used during the locking phase, and multiple approximate slope parameters are set for the phase error-tuning word relationship curve.

[0012] In some embodiments, the following technical features are also included: In the threshold dynamic adjustment unit, the threshold adjustment formula is: LOCK_TH_ADJ = LOCK_TH×[1-R×(OTW1-OTW adj ) / OTW1] Where LOCK_TH_ADJ is the adjustment threshold, OTW1 is the tuning word threshold during the current locking phase, and OTW... adj To predict the initial tuning word, LOCK_TH is the lock-in threshold, and R is a dimensionless coefficient.

[0013] The present invention also adopts the following technical solutions: A fast relocking method for an all-digital phase-locked loop includes the following steps: Upon detecting a phase-locked loop (PLL) loss of lock, the current frequency error and phase error are collected. The disturbance type is determined based on the amplitude of the frequency and phase errors, including coarse frequency disturbance, fine frequency disturbance, or phase disturbance. Based on the disturbance type, the PLL's initial relocking state is switched to the corresponding locked state, including automatic frequency control, frequency locking, or phase locking. A slope factor is calculated based on historical tuning words and error data within the target locked state phase, and the current error is mapped to a predicted initial tuning word. When the predicted initial tuning word is within a neighboring range of the target state tuning word, the current locking threshold is dynamically reduced to accelerate the locking process. The predicted initial tuning word is written into the oscillator tuning word generation module, and the PLL is controlled to relock in the target locked state.

[0014] In some embodiments, the following technical features are also included: The step of determining the disturbance type includes: if the current frequency error FE n The frequency error threshold FE locked during the automatic frequency control phase is greater than the threshold value. afc If the current frequency error FE is... n Satisfy FE afc ≥FE n >FE fl , of which FE fl If the frequency error threshold locked during the frequency locking phase is used, it is determined to be a minor frequency disturbance; if the current frequency error FE n Satisfy FE n ≤FE fl If so, it is determined to be a phase perturbation.

[0015] In some embodiments, the following technical features are also included: The step of dynamically reducing the current locking threshold is calculated using the following formula. LOCK_TH_ADJ = LOCK_TH×[1-R×(OTW1-OTW adj ) / OTW1] Where LOCK_TH_ADJ is the adjusted lock judgment threshold, OTW1 is the tuning word threshold when the target is locked, and OTW... adj To predict the initial tuning word, LOCK_TH is the original lock judgment threshold, and R is a dimensionless coefficient.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: This technical solution can assess the magnitude of the disturbance when the ADPLL loses lock and switch the ADPLL to re-lock the initial working state based on the disturbance type. This initial state is a certain state in the locking process. By using the oscillator tuning words of each state that have been saved, a suitable oscillator tuning word under the current disturbance is calculated. Based on this oscillator tuning word, the initial oscillator tuning word for a certain state is used. Since this oscillator tuning word is an intermediate value in the locking process, only a relatively small frequency error or phase error needs to be corrected to achieve locking in the corresponding state, reducing the locking time in that state. At the same time, if the initial oscillator tuning word is close to the oscillator tuning word at the end of the state, a new locking threshold is calculated (reducing the original locking threshold), reducing the number of iterations, further accelerating the locking judgment in that state, and realizing fast relocking of the entire ADPLL. Attached Figure Description

[0017] Figure 1 This is an overall framework diagram of the fast relocking control system according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating the rapid relocking process in an embodiment of the present invention. Figure 3 This is a flowchart illustrating the logical judgment process for disturbance classification in an embodiment of the present invention. Detailed Implementation

[0018] The embodiments of the present invention will be described in detail below. It should be emphasized that the following description is merely exemplary and not intended to limit the scope and application of the present invention.

[0019] It should be noted that when a component is said to be "connected to" another component, it can be directly connected to the other component or indirectly connected to it. Furthermore, a connection can be used for both fixing purposes and for circuit / signal connectivity.

[0020] Furthermore, in the description of the embodiments of the present invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] In existing technologies, after an ADPLL loses lock, it needs to undergo a complete relocking process (including automatic frequency control state, frequency locking state, phase locking state, etc.), resulting in a long relocking time. Analysis reveals the main technical problems include: Lack of disturbance classification mechanism: unable to adaptively select the optimal relocking starting point based on the cause of lock loss; Fixed locking threshold limitation: Threshold optimization is not performed for tuning words that are nearing a locking state; Linearity not fully utilized: The linear relationship between historical tuning words and error data was not used to predict the initial tuning word.

[0022] To address the time redundancy caused by the inability of traditional relocking processes to skip completed stages, the following embodiments of the present invention propose a fast relocking system for an all-digital phase-locked loop, comprising: The dynamic disturbance assessment module includes frequency error and phase error acquisition units, which are used to determine the disturbance type as coarse frequency disturbance, fine frequency disturbance, or phase disturbance based on the amplitude of the current frequency error and phase error. The state switching module includes a locked state storage unit, which is used to switch the initial relocking state of the phase-locked loop to the corresponding locked state among automatic frequency control state, frequency locking state or phase locking state according to the disturbance type after a loss of lock is detected. The tuning word prediction module includes a linear relationship calculation unit, which is used to map the current error to the predicted initial tuning word based on the slope factor generated by the historical tuning words and error data within the target state stage; the tuning word prediction module further includes a threshold dynamic adjustment unit, which accelerates the locking process by reducing the current locking judgment threshold when the predicted initial tuning word is in the adjacent interval of the target state tuning word range. The collaborative control module includes a data bus interface for synchronizing the operation timing of the dynamic disturbance evaluation module, the state switching module, and the tuning word prediction module, and for writing the predicted initial tuning word into the corresponding oscillator tuning word generation module.

[0023] The following embodiments of the present invention also propose a fast relocking method for an all-digital phase-locked loop, comprising the following steps: After detecting a phase-locked loop loss, the current frequency error and phase error are collected; The disturbance type is determined based on the magnitude of the frequency error and phase error, and the disturbance type includes coarse frequency disturbance, fine frequency disturbance, or phase disturbance; According to the type of disturbance, the initial relocking state of the phase-locked loop is switched to the corresponding locking state, which includes at least an automatic frequency control state, a frequency locking state, or a phase locking state. Based on the historical tuning words and error data during the target locking state phase, the slope factor is calculated, and the current error is mapped to the predicted initial tuning word. When the predicted initial tuning word is in the adjacent range of the target state tuning word, the current locking judgment threshold is dynamically reduced to accelerate the locking process; The predicted initial tuning word is written into the oscillator tuning word generation module, and the phase-locked loop is controlled to relock under the target locked state.

[0024] Specific examples are as follows:

[0025] Example like Figure 1 As shown, this embodiment includes modules such as Automatic Frequency Control (AFC), Frequency Locking (FL), Digital Loop Filter (DLF), Digital Controlled Oscillator (DCO), Time-to-Digital Converter (TDC), State Machine (FSM), and Lock Determination (LOCK_DET) found in conventional ADPLL circuits. It also includes a fast relocking system that supports rapid re-locking after lock loss, specifically implemented as a fast relocking module (FAST_RELOCK) in this embodiment. This module integrates functional sub-modules, including: Dynamic Disturbance Assessment Module: In this embodiment, a dynamic disturbance assessment module (also referred to as the disturbance assessment module) is used to collect the amplitude of the current frequency error and phase error and determine the disturbance type. The frequency error and phase error acquisition unit in the dynamic disturbance assessment module monitors the error signal from the lock-on judgment module in real time.

[0026] State switching module: In this embodiment, its function is integrated into the state machine, and it performs state switching according to the instructions of the fast relock module. The state switching module includes a lock state storage unit, which is used to store historical data of each lock state (such as tuning words, errors, etc.).

[0027] The tuning word prediction module includes a linear relationship calculation unit and a threshold dynamic adjustment unit. The linear relationship calculation unit calls historical data from the locked state storage unit to calculate the slope factor (K); the threshold dynamic adjustment unit is used to perform dynamic adjustment of the locked threshold.

[0028] Cooperative control module: In this embodiment, it is implemented by the fast relock control module, which contains a data bus interface for synchronizing the operation timing of the above sub-modules and writing the predicted initial tuning word to the oscillator tuning word generation module (such as automatic frequency control, frequency locking, digital loop filtering module).

[0029] The main data relationships between modules are as follows: 1. Automatic frequency control, frequency locking, and digital loop filtering modules transmit the corresponding oscillator tuning word OTW. afc OTW fl and OTW pl Provide a digitally controlled oscillator; 2. Automatic frequency control, frequency locking, and digital loop filtering modules respectively transmit the corresponding frequency error FE. afc Frequency error FE fl and phase error PE pl Provide a lock detection module; 3. The locking judgment module outputs a control signal to the state machine to switch states based on the locking threshold. 4. The locking judgment module transmits the frequency error and phase error to the fast relocking module; 5. The state machine transmits the real-time status to the fast relock module, and the relock module transmits the state switching signal to the state machine for state switching. 6. The fast relock module calculates the oscillator tuning word (predicted initial tuning word OTW). adj The signal is transmitted to the automatic frequency control, frequency locking, and digital loop filtering modules. 7. The fast relock control module is used to control the data interaction between sub-modules within the fast relock module and between the fast relock module and other modules. Specifically, it synchronizes the operation timing of the dynamic disturbance evaluation module, the state switching module, and the tuning word prediction module, and writes the predicted initial tuning word.

[0030] like Figure 2 As shown, the operation of this circuit mainly includes the initial state (IDLE), automatic frequency control state (S_AFC), frequency lock state (S_FL), phase lock state (S_PL), PLL lock state (S_PLL_RDY), and PLL unlock state (S_LOSE_LOCK).

[0031] like Figure 3 As shown, during the ADPLL locking process, the oscillator tuning word OTW, frequency error FE, phase error PE, and other information for each state during the locking process are stored in the locked state storage unit. Within each stage of the locking process, the target frequency and the oscillator tuning word have a linear relationship. The slope factor K of the frequency error, phase error, and oscillator tuning word at each stage can be calculated, where K... fe K is the frequency error slope factor. pe This represents the phase error slope factor. The slope factor K can be calculated based on any two historical data points within the target state stage. For example, using the start and end points of this stage: K fe = (OTW Start - OTW End ) / (FE Start - FE End ), of which OTW Start FE Start The value at the start of the phase, OTW End FE End The value represents the value when the phase locking is completed.

[0032] K fe = (OTW0 - OTW1) / (FE0 - FE1) K pe = (OTW0 - OTW1) / (PE0 - PE1) FE0, PE0, and OTW0 represent the frequency error, phase error, and oscillator tuning word when entering the current stage, respectively. FE1, PE1, and OTW1 represent the frequency error, phase error, and oscillator tuning word when leaving the current stage after locking in the current stage, respectively.

[0033] When an ADPLL lockout is detected, the disturbance assessment module classifies the disturbance based on frequency error into three categories: coarse frequency disturbance, fine frequency disturbance, and phase disturbance. a. Coarse frequency perturbation: FE n > FE afc； b. Fine frequency perturbation: FE afc ≥FE n > FE fl； c. Phase perturbation: FE n ≤FE fl .

[0034] Where FE n For the frequency error under the current disturbance, FE afc For the frequency error after coarse frequency locking in AFC state, FE fl This represents the frequency error after frequency locking in FL mode.

[0035] The above disturbances correspond to the conditions in one of the following states: automatic frequency control, frequency locking, and phase locking, respectively, when entering re-locked operation.

[0036] Based on the disturbance type, after the ADPLL loses lock, the state machine switches to one of the states in the locking process, and retrieves the K value from the tuning word prediction module in each state. fe and K pe And based on the current frequency error FE n or phase error PE n Calculate the oscillator tuning word OTW adj Specifically: a. In automatic frequency control mode K fe = (OTW afc0 - OTW afc1 ) / (FE) afc0 - FE afc1 ) OTW adj = K fe * FE n + B Where B is the intercept (e.g., fitted using historical data via least squares).

[0037] b. In frequency-locked state K fe = (OTW fl0 - OTW fl1 ) / (FE) fl0 - FE fl1 ) OTW adj = K fe * FE n + B Where B is the intercept (e.g., fitted using historical data via least squares).

[0038] c. In phase-locked state K pe = (OTW pl0 - OTW pl1 ) / (PE pl0 - PE pl1 ) OTW adj = K pe * PE n + B Where B is the intercept (e.g., fitted using historical data via least squares).

[0039] Calculated OTW adj As the initial oscillator tuning word in this state, subsequent oscillator tuning words are calculated based on this value. If this initial oscillator tuning word is close to the final oscillator tuning word OTW1 in the state, i.e., 0.9*OTW1≤OTW adj If ≤OTW1, then further adjust the locking threshold LOCK_TH_ADJ to LOCK_TH_ADJ = LOCK_TH×[1-R×(OTW1-OTW adj ) / OTW1] Where R is a dimensionless coefficient representing the adjustment intensity, which is a configurable parameter and is adjusted based on the debugging results. This accelerates locking in the current state. Based on the linear relationship, the initial tuning word OTW is predicted. adj It can be achieved through the formula OTW adj = K fe *FE n + B or OTW adj = K pe * PE n The result is calculated using +B, where B is the intercept. In practical applications, due to good system linearity or to simplify calculations, B can be approximated as 0, i.e., OTW can be used. adj =K fe *FE n or OTW adj = K pe *PE n Perform a mapping. Those skilled in the art will understand that 'mapping' encompasses the complete linear relationship including the intercept.

[0040] In this embodiment, when entering AFC, FL, or PL states after losing lock under different degrees of disturbance, the locking time can be reduced by approximately 4.7%, 23.4%, and 50.9% respectively compared to the conventional complete relocking process.

[0041] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fast relocking system for a fully digital phase-locked loop, characterized in that, include: The dynamic disturbance assessment module includes frequency error and phase error acquisition units, which are used to determine the disturbance type as coarse frequency disturbance, fine frequency disturbance, or phase disturbance based on the amplitude of the current frequency error and phase error. The state switching module includes a locked state storage unit, which is used to switch the initial relocking state of the phase-locked loop to the corresponding locked state among automatic frequency control state, frequency locking state or phase locking state according to the disturbance type after a loss of lock is detected. The tuning word prediction module includes a linear relationship calculation unit, which is used to map the current error to the predicted initial tuning word based on the slope factor generated by the historical tuning words and error data within the target state stage; the tuning word prediction module further includes a threshold dynamic adjustment unit, which accelerates the locking process by reducing the current locking judgment threshold when the predicted initial tuning word is in the adjacent interval of the target state tuning word range. The collaborative control module includes a data bus interface for synchronizing the operation timing of the dynamic disturbance evaluation module, the state switching module, and the tuning word prediction module, and for writing the predicted initial tuning word into the corresponding oscillator tuning word generation module.

2. The system as described in claim 1, characterized in that, The dynamic disturbance assessment module includes a disturbance assessment component integrated in a digital comparator, which implements the frequency error threshold comparison function through hardware logic circuits; the threshold dynamic adjustment unit includes a threshold dynamic configuration component connected to the lock judgment module, and has a programmable gain parameter interface.

3. The system as described in claim 1, characterized in that, The locked state further includes an initial frequency adjustment state, a coarse frequency adjustment state, or a clock edge alignment state; the system also includes: The state memory component stores the tuning word, frequency error, and phase error datasets for each locking phase. The linear operation component, including a multiplier accumulator and a shift register, performs calculations of the product of the slope factor and the real-time frequency error or phase error.

4. The system according to claim 1, characterized in that: In the disturbance classification logic of the dynamic disturbance evaluation module, the judgment condition for coarse frequency disturbance is FE. n >FE afc The criterion for determining fine frequency perturbations is FE. afc ≥FE n >FE fl The condition for determining phase perturbation is FE. n ≤FE fl , of which FE n For the frequency error under the current disturbance, FE afc For the frequency error threshold locked during the automatic frequency control phase, FE fl This is the frequency error threshold locked during the frequency locking phase.

5. The system according to claim 1, characterized in that: The slope factor is calculated as K=(OTW) n -OTW m ) / (E n -E m ), of which OTW n OTW m E represents the oscillator tuning word in the nth and mth control cycles within the target state phase, respectively. n E m This refers to the frequency error or phase error corresponding to the period.

6. The system according to claim 4, characterized in that: Piecewise linearization is used during the locking phase, and multiple approximate slope parameters are set for the phase error-tuning word relationship curve.

7. The system according to claim 1, characterized in that: In the threshold dynamic adjustment unit, the threshold adjustment formula is LOCK_TH_ADJ = LOCK_TH × [1 - R × (OTW1 - OTW)] adj ) / OTW1], where LOCK_TH_ADJ is the adjustment threshold, OTW1 is the tuning word threshold when locked in the current stage, and OTW adj To predict the initial tuning word, LOCK_TH is the lock-in threshold, and R is a dimensionless coefficient.

8. A fast relocking method for an all-digital phase-locked loop, characterized in that, Includes the following steps: After detecting a phase-locked loop loss, the current frequency error and phase error are collected; The disturbance type is determined based on the magnitude of the frequency error and phase error, and the disturbance type includes coarse frequency disturbance, fine frequency disturbance, or phase disturbance; According to the type of disturbance, the initial relocking state of the phase-locked loop is switched to the corresponding locking state, which includes at least an automatic frequency control state, a frequency locking state, or a phase locking state. Based on the historical tuning words and error data during the target locking state phase, the slope factor is calculated, and the current error is mapped to the predicted initial tuning word. When the predicted initial tuning word is in the adjacent range of the target state tuning word, the current locking judgment threshold is dynamically reduced to accelerate the locking process; The predicted initial tuning word is written into the oscillator tuning word generation module, and the phase-locked loop is controlled to relock under the target locked state.

9. The method as described in claim 8, characterized in that, The step of determining the type of disturbance includes: If the current frequency error FE n The frequency error threshold FE locked during the automatic frequency control phase is greater than the threshold value. afc If so, it is determined to be a coarse frequency disturbance; If the current frequency error FE n Satisfy FE afc ≥FE n >FE fl , of which FE fl If the frequency error threshold locked during the frequency locking phase is used, it is determined to be a minor frequency disturbance. If the current frequency error FE n Satisfy FE n ≤FE fl If so, it is determined to be a phase perturbation.

10. The method as described in claim 8, characterized in that, The step of dynamically reducing the current lock judgment threshold adopts the formula LOCK_TH_ADJ = LOCK_TH×[1-R×(OTW1-OTW)]. adj The calculation is performed using LOCK_TH_ADJ, where LOCK_TH_ADJ is the adjusted lock judgment threshold, OTW1 is the tuning word threshold when the target is locked, and OTW... adj To predict the initial tuning word, LOCK_TH is the original lock judgment threshold, and R is a dimensionless coefficient.

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