A data caching apparatus, method and device

Abstract

The application relates to the technical field of data storage, and discloses a data caching device, method and equipment. The data caching device comprises a storage module, an idle address management module and a consumed address storage module. The storage module is used for storing message data of multiple data streams; and the multiple data streams share each buffer area in the storage module. The idle address management module is used for storing and allocating idle addresses in the storage module. The consumed address storage module is used for storing addresses consumed by target message data in the multiple data streams when the target message data is stored in the storage module; and when the target message data is lost, the addresses consumed by the target message data are written into the idle address management module. The above scheme realizes error packet rollback when multiple messages share a storage space, and improves the utilization rate of the storage space.

Description

Technical Field

[0001] This application relates to the field of data storage technology, specifically to a data caching device, method, and apparatus. Background Technology

[0002] In data storage, linked lists are widely used because they can improve the utilization of fragmented space, especially in smart network interface card data caching. In cases of large-scale data storage, copying, and forwarding, multiple linked lists often share part of the data space.

[0003] In scenarios where two data streams (e.g., wireline data and loopback data) arrive simultaneously, the traditional approach uses two completely independent management lists and memory storage systems. While this design facilitates rollback in case of packet errors (directly returning to the packet header pointer) and simplifies space release, it suffers from low data space utilization and inflexible resource management. Therefore, to improve space utilization, a shared cache can be used to store both data streams simultaneously.

[0004] However, when using a shared cache, the error status of the message data can only be known in the last step of the two data streams. Since the messages are linked simultaneously and intertwined when using storage space, it is impossible to directly backtrack to the message header pointer position when an erroneous packet is received, resulting in the erroneous packet not being discarded. Summary of the Invention

[0005] In view of this, this application provides a data caching device, method, and apparatus that enables error rollback when multiple packets share storage space, thereby improving the utilization rate of storage space.

[0006] In a first aspect, this application provides a data caching device, which includes a storage module, a free address management module, and a consumed address storage module;

[0007] The storage module is used to store message data from multiple data streams; and the multiple data streams share each buffer area in the storage module.

[0008] The free address management module is used to store and allocate free addresses in the storage module;

[0009] The consumed address storage module is used to cache the address consumed by the target packet data when the target packet data in the multi-channel data stream is stored in the storage module; and when the target packet data is lost, to write the address consumed by the target packet data into the free address management module.

[0010] In one optional implementation, the device further includes an address release module; the address release module is used to cache the addresses released after unlinking and write the addresses released after unlinking into the free address management module.

[0011] In one optional implementation, the storage module includes multiple storage units;

[0012] The free address management module is used to arbitrate a corresponding number of free addresses when storing target message data from multiple data streams simultaneously; the stored addresses are used to indicate the chaining of the multiple data streams.

[0013] In one alternative implementation, the corresponding number of free addresses are located on different memory banks.

[0014] In one optional implementation, the free address management module further includes multiple free address storage units; each of the multiple free address storage units corresponds one-to-one with the multiple memory banks; the free address storage unit is used to store the free address of the corresponding memory bank.

[0015] In one optional implementation, the free address management module further includes a pre-read address unit; the pre-read address unit is used to pre-read free addresses from the plurality of free address storage units.

[0016] In one optional implementation, when the target message data of the target data stream in the multi-channel data stream is corrupted, the data linked list of the target data stream is rolled back to the message header pointer position of the target message data, and the linked address corresponding to the target message data is read through the consumption address storage module.

[0017] In one optional implementation, if the target message data in the target data stream is correct, the linked address corresponding to the target message data in the consumed address storage module is released.

[0018] In one optional implementation, the number of storage units in the consumed address storage module, the number of storage units in the address release module, and the number of free address storage units are the same.

[0019] Secondly, a data caching method is also provided, which is applied to the aforementioned data caching device, and the method includes:

[0020] When multiple data streams are received, a free address is obtained from the free address management module;

[0021] Based on the free address, store the target packet data in the multiple data streams, and cache the address consumed by the target packet data;

[0022] When the target packet data is lost, the address consumed by the target packet data is written into the free address management module.

[0023] In an optional implementation, the method further includes:

[0024] If the multi-channel data stream triggers cache unlinking, the address released after unlinking is written to the free address management module.

[0025] In one optional implementation, obtaining a free address from the free address management module when multiple data streams are received includes:

[0026] When storing target message data from multiple data streams simultaneously, a number of free addresses are arbitrated based on the quantity of the target message data.

[0027] In an optional implementation, the method further includes:

[0028] When the target message data of the target data stream in the multi-channel data stream is corrupted, the data linked list of the target data stream is rolled back to the message header pointer position of the target message data, and the linked address corresponding to the target message data is read through the consumption address storage module.

[0029] In an optional implementation, the method further includes:

[0030] If the target message data in the target data stream is correct, then release the linked address corresponding to the target message data in the consumed address storage module.

[0031] Secondly, a computer device is provided, wherein the computer device is provided with the aforementioned data caching device.

[0032] The technical solution provided in this application may include the following beneficial effects:

[0033] The data caching device of this application includes a storage module, a free address management module, and a consumed address storage module. The storage module stores message data from multiple data streams, and the multiple data streams share various buffer areas within the storage module. The free address management module stores and allocates free addresses within the storage module. The consumed address storage module caches the addresses consumed by the target message data when it is stored in the storage module from multiple data streams. Furthermore, when the target message data is lost, the addresses consumed by the target message data are written into the free address management module. In this scheme, when data from multiple data streams is stored in the shared storage module, the consumed addresses are stored in the consumed address storage module. If a message error occurs and packet loss is necessary, space can be released directly based on the addresses stored in the consumed address storage module. This achieves error rollback when multiple messages share storage space, improving the utilization rate of storage space. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0035] Figure 1 A logical flowchart illustrating independent data storage is shown.

[0036] Figure 2 A logical flowchart of a data sharing storage is shown.

[0037] Figure 3 A schematic diagram of a data caching device is shown.

[0038] Figure 4 A working logic diagram of a data caching device illustrated in an embodiment of this application is shown.

[0039] Figure 5 A flowchart illustrating message reception according to an embodiment of this application is shown.

[0040] Figure 6 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of this application. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] In the description of the embodiments of this application, the term "correspondence" may indicate that there is a direct or indirect correspondence between two things, or that there is an association between two things, or that there is a relationship of instruction and being instructed, configuration and being configured, etc.

[0043] In data storage, linked list structures are widely used because they can effectively improve the utilization of fragmented space. Therefore, when dealing with large-scale data storage, copying, and forwarding operations, multiple linked lists often share a portion of the storage space. Figure 1 A logical flowchart illustrating independent data storage is shown. For example... Figure 1 As shown, to meet the needs of the above scenarios, each data path can typically be configured with an independent linked list and storage memory. The advantage of this design is that once an error packet occurs, it is easy to return to the beginning of the corresponding message, and releasing space is relatively simple; however, its disadvantage is that resource utilization efficiency is low and data space usage is not flexible enough. Figure 2 A logical flowchart of a data sharing storage system is shown. (For example...) Figure 2 As shown, the two data streams share a cache and a portion of the storage area, and the error check is only performed at the final stage after data reception is complete. Because the linked lists for these two data streams in memory are interleaved, once an error packet occurs, it is no longer possible to directly backtrack to the packet header as before, and releasing space becomes more complex.

[0044] To address the aforementioned issues, this application provides a data storage device that enables multi-path data cache management with rollback support. It stores multiple data paths through multiple linked lists, while using a single storage device for data storage. It also supports address rollback to discard erroneous packets.

[0045] Figure 3 A schematic diagram of a data caching device is shown. Figure 3 As shown, the data caching device includes a storage module, a free address management module, and a consumed address storage module;

[0046] This storage module is used to store message data from multiple data streams; and these multiple data streams share the various buffers within this storage module.

[0047] This free address management module is used to store and allocate free addresses in the storage module;

[0048] The address consumption storage module is used to cache the address consumed by the target packet data when the target packet data in the multi-channel data stream is stored in the storage module; and when the target packet data is lost, the address consumed by the target packet data is written into the free address management module.

[0049] In this embodiment, the storage module is used to actually store the message content of multiple data streams (such as wired network data, loopback data, etc.), and all message data are placed in the same group of storage space, but logically organized through different linked lists. The free address management module is used to track which addresses in the storage module are not yet occupied and can be used for subsequent message writing. Before message writing, a segment or group of free addresses can be requested from the free address management module; during rollback or release, the addresses are reclaimed and written to the module for subsequent reuse. The consumed address management module is used to cache used addresses. When a message from a multiple data stream is written to the storage module, it records a series of storage addresses occupied by the message in real time. If the message is subsequently determined to be an erroneous packet and needs to be discarded and its occupied space released, the corresponding address needs to be read from here and written back to the free address management module. Since multiple data streams are interleaved in the shared cache, it is not possible to directly locate all related storage blocks based on the linked list head. The consumed address storage module saves a list of fragmented occupied locations of the message at the message granularity to achieve accurate rollback.

[0050] Optional, such as Figure 3 As shown, the device also includes an address release module; the address release module is used to cache the address released after unlinking and write the address released after unlinking into the free address management module.

[0051] In this embodiment, after a message is consumed normally (i.e., verification is successful, forwarding is complete, or the upper-layer protocol has finished processing), the corresponding consumed addresses can be released one by one through the address release module. Specifically: first, all attached (occupied) addresses of the message are retrieved from the consumed address storage module, temporarily stored in the storage unit of the address release module, and then written back to the free address management module.

[0052] For further details, please refer to... Figure 4 It shows a working logic diagram of the data caching device shown in the embodiments of this application. Figure 4 The following example illustrates the working logic of a data caching device using two data streams. Figure 4As shown, the storage module mem_pool includes multiple storage banks; the free address management module free_addr_mng is used to arbitrate a corresponding number of free addresses when storing target packet data from multiple data streams simultaneously; free addresses are used to indicate data stream binding. For example, Figure 4 As shown, when the free address management module free_addr_mng needs to store the target packet data of both data streams simultaneously, it can arbitrate two free storage addresses to indicate the target packet data of the two data streams to be linked, so as to avoid access conflicts.

[0053] Optionally, in this embodiment, the corresponding number of free addresses are located on different storage banks. That is, the two free storage addresses determined by arbitration are located on different storage banks, for example, on bank1 and bank2 respectively.

[0054] like Figure 4 As shown, the free address management module free_addr_mng also includes multiple free address storage units free_addr_fifo; each of these multiple free address storage units free_addr_fifo corresponds one-to-one with the multiple memory banks; the free address storage unit free_addr_fifo is used to store the free address of the corresponding memory bank.

[0055] In this embodiment of the application, since the free address storage unit free_addr_fifo corresponds one-to-one with the multiple storage banks, that is, each storage bank has a set of free address storage units to maintain the available address queue / stack in the storage bank, the device can quickly locate which storage bank a certain data or a certain message should be written to, and how much space is left in the storage bank.

[0056] Optionally, in this embodiment of the application, the free address management module further includes a pre-fetch address unit; the pre-fetch address unit is used to pre-read free addresses from the plurality of free address storage units free_addr_fifo.

[0057] This pre-read address unit can retrieve or mark a batch of available addresses from various free address storage units in advance, so that downstream modules (such as storage write logic) can use them quickly, thereby reducing the latency caused by frequently requesting addresses from the free queue in the write link.

[0058] Specifically, the prefetch address unit can be a small FIFO cache that preloads the most likely free addresses to be allocated into the prefetch unit according to priority or load conditions.

[0059] Optionally, when the target message data of the target data stream in the multi-channel data stream is corrupted, the data linked list of the target data stream is rolled back to the message header pointer position of the target message data, and the attached link address corresponding to the target message data is read through the consumption address storage module drop_addr_mng.

[0060] When a packet from a multi-channel data stream is written to the storage module, the drop_addr_mng address storage module can record in real time a series of free storage addresses occupied by the packet. If the packet is subsequently determined to be an erroneous packet and needs to be discarded and its occupied space released, the corresponding address needs to be read from here and written back to the free address management module free_addr_mng.

[0061] Optionally, if the target message data in the target data stream is correct, the linked address corresponding to the target message data in the consumed address storage module is released.

[0062] In this embodiment, if the packet data of the target data stream is correct, it means that the packet data in the target data stream no longer needs packet loss processing. If the trailing address corresponding to the correct packet data is not released, the trailing address corresponding to the correct packet data will gradually accumulate in the consumption address storage module. These addresses are usually not needed (because normal data does not require packet loss), which will instead cause the storage units in the consumption address storage module to be blocked. Therefore, the consumption address storage module no longer needs to store the trailing address corresponding to the packet data, and the address stored in the consumption address storage module can be released directly so that the consumption address storage module can store the address occupied by subsequent packet data.

[0063] Optionally, the number of storage units in the consumed address storage module drop_addr_mng, the number of storage units in the address release module release_addr_mng, and the number of free address storage units free_addr_fifo are the same.

[0064] Assuming there are M parallel data links in the system (i.e., at most M packets in the "write-pending confirmation" stage simultaneously): the address storage module needs to allocate a separate storage unit for each link or each active packet to record its address list. The address release module needs to prepare a buffer unit for each link or each active packet to temporarily store addresses to be released. The idle address management module reserves a number of idle address storage units for each storage bank, corresponding to the number of consumed / released units, ensuring sufficient capacity for reclamation even in the worst-case scenario (M packets simultaneously malfunctioning). In other words, the number of storage units in the three modules remains consistent, allowing the device shown in this embodiment to function normally even during peak error concurrency periods.

[0065] In summary, the specific implementation process of the above-mentioned device may include:

[0066] 1. Linking: When two data streams need to be linked simultaneously, free_addr_mng arbitrates two addresses from different banks each time, which are used for linking loopback data and net data respectively. The address for net data linking needs to be stored in drop_addr_mng synchronously.

[0067] 2. Error Packet Rollback: When network data is corrupted, the data list rolls back to the current packet header pointer position in one go. The current attached address is read through drop_addr_mng and released to free_addr_mng; if the packet is correct, the address written to drop_addr_mng for the current packet is released.

[0068] 3. Message delinking: When each linked list is delinked, the released address is written to its respective release_addr_mng, and subsequently written back to free_addr_mng.

[0069] 4. Idle Address Reclamation: `drop_addr_mng` and `release_addr_mng` contain the same number of FIFOs (fifoxes) with a smaller depth as `free_addr_fifo`. This is used to achieve efficient out-of-order release of idle addresses, reducing the probability of congestion caused by simultaneous release of multiple addresses and minimizing the impact on overall bandwidth performance. `drop_addr_mng` has a higher release priority.

[0070] Figure 5A flowchart illustrating the message reception process according to an embodiment of this application is shown. This flowchart describes the data cache management process supporting message rollback. This process mainly utilizes two address management modules, `free_addr_mng` and `drop_addr_mng`, to achieve message caching, error rollback, and space reclamation. Specifically, after system initialization, the system first releases the reset state and then waits to receive messages. When the start-of-list (SOP) flag of a message is received, a linked list operation for that message begins. At this time, the `free_addr_mng` module schedules free storage addresses to cache the target message data. While each data segment is added to the linked list, the address used is also synchronously written to `drop_addr_mng`. This module records all linked addresses of the current message in the cache for subsequent error rollback or resource release. When the end-of-list (EOP) flag of the complete message is received, the system determines whether the message is correct. If the message is correct, the linked addresses recorded in `drop_addr_mng` are directly used as temporary cache release addresses and written back to `free_addr_mng`, completing resource reclamation. If a message verification error occurs, the system uses the address recorded in `drop_addr_mng` to backtrack the linked list to the beginning of the message's SOP, discards the attached message, and releases all used cached addresses. Finally, if `drop_addr_mng` is not empty, its contents are used to gradually release addresses to `free_addr_mng`, restoring the idle state, completing the processing flow for this message, and continuing to wait for the next message.

[0071] The above process can handle two data streams simultaneously, making more efficient use of available free addresses, reducing waste of free addresses, and improving overall system performance. Furthermore, it only requires a final error check during data processing, reducing the complexity of rolling back addresses one by one and lowering management overhead. Through one-time arbitration and rollback, it simplifies code complexity, avoiding multiple state checks and updates between different steps, thereby improving code readability and maintainability. Because it can roll back multiple addresses simultaneously, when an error occurs, the associated allocated addresses can be released immediately, avoiding dangling addresses and quickly restoring the system to normal operation. This approach is easily scalable to more data streams, in addition to... Figure 4 The two data streams shown can be extended to more data stream application scenarios. Only the arbitration mechanism and address management logic need to be adjusted, without redesigning the entire system.

[0072] In summary, the data caching device of this application includes a storage module, a free address management module, and a consumed address storage module. The storage module stores message data from multiple data streams, and the multiple data streams share various buffer areas within the storage module. The free address management module stores and allocates free addresses within the storage module. The consumed address storage module caches the addresses consumed by the target message data when it is stored in the storage module from multiple data streams. Furthermore, when the target message data is lost, the addresses consumed by the target message data are written into the free address management module. In this scheme, when data from multiple data streams is stored in the shared storage module, the consumed addresses are stored in the consumed address storage module. If a message error occurs and packet loss is necessary, space can be released directly based on the addresses stored in the consumed address storage module. This achieves error rollback when multiple messages share storage space, improving the utilization rate of storage space.

[0073] Each unit in the data caching device in the target node in this embodiment can be presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0074] This application also provides a computer device that may include the data caching device shown in this application embodiment to schedule various requests that the computer device needs to execute. Please refer to... Figure 6 , Figure 6 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of this application, such as... Figure 6 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information in a graphical user interface on an external input / output device (such as a display device coupled to the interface). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 6 Take a processor 10 as an example.

[0075] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0076] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0077] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0078] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0079] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0080] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A data caching device, characterized in that, The data caching device includes a storage module, a free address management module, and a consumed address storage module; The storage module is used to store message data from multiple data streams; and the multiple data streams share each buffer area in the storage module. The free address management module is used to store and allocate free addresses in the storage module; The consumed address storage module is used to cache the address consumed by the target packet data when the target packet data in the multi-channel data stream is stored in the storage module; and when the target packet data is lost, to write the address consumed by the target packet data into the free address management module.

2. The apparatus according to claim 1, characterized in that, The device further includes an address release module; the address release module is used to cache the addresses released after unlinking and write the addresses released after unlinking into the free address management module.

3. The apparatus according to claim 2, characterized in that, The storage module includes multiple storage units; The free address management module is used to arbitrate a corresponding number of free addresses when storing target message data from multiple data streams simultaneously; the free addresses are used to indicate the linking of the multiple data streams.

4. The apparatus according to claim 3, characterized in that, The corresponding number of free addresses are located on different memory banks.

5. The apparatus according to claim 4, characterized in that, The free address management module also includes multiple free address storage units; each of the multiple free address storage units corresponds one-to-one with the multiple memory banks; the free address storage unit is used to store the free address of the corresponding memory bank.

6. The apparatus according to claim 5, characterized in that, The free address management module also includes a pre-read address unit; the pre-read address unit is used to pre-read free addresses from the plurality of free address storage units.

7. The apparatus according to any one of claims 1 to 6, characterized in that, When the target message data of the target data stream in the multi-channel data stream is corrupted, the data linked list of the target data stream falls back to the message header pointer position of the target message data, and the linked address corresponding to the target message data is read through the consumption address storage module.

8. The apparatus according to claim 7, characterized in that, The consumed address storage module is also used to release the attached link address corresponding to the target message data if the target message data in the target data stream is correct.

9. The apparatus according to claim 5, characterized in that, The number of storage units in the consumed address storage module, the number of storage units in the address release module, and the number of free address storage units are the same.

10. A data caching method, characterized in that, The data caching method is applied to the data caching device as described in any one of claims 1 to 9, the method comprising: When multiple data streams are received, a free address is obtained from the free address management module; Based on the free address, store the target packet data in the multiple data streams, and cache the address consumed by the target packet data; When the target packet data is lost, the address consumed by the target packet data is written into the free address management module.

11. The method according to claim 10, characterized in that, The method further includes: If the multi-channel data stream triggers cache unlinking, the address released after unlinking is written to the free address management module.

12. The method according to claim 10 or 11, characterized in that, The step of obtaining a free address from the free address management module when multiple data streams are received includes: When storing message data from multiple data streams simultaneously, a number of free addresses are arbitrated based on the number of target message data.

13. The method according to claim 10 or 11, characterized in that, The method further includes: When the target message data of the target data stream in the multi-channel data stream is corrupted, the data linked list of the target data stream is rolled back to the message header pointer position of the target message data, and the linked address corresponding to the target message data is read through the consumption address storage module.

14. The method according to claim 10 or 11, characterized in that, The method further includes: If the target message data in the target data stream is correct, then release the linked address corresponding to the target message data in the consumed address storage module.

15. A computer device, characterized in that, The computer device is provided with a data caching device as described in any one of claims 1 to 9.

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