Polymorphic ferroelectric memory and operation method thereof

Abstract

The invention belongs to the technical field of ferroelectric memory devices, and particularly relates to a ferroelectric memory for multi-state information storage and an operation method thereof. The specific electrode structure is constructed, different electric field distributions are formed in the ferroelectric material, electric domains in different areas are overturned under different electric fields, then conductive domain walls with different dip angles / lengths / numbers are formed, and due to the fact that the different dip angles / lengths / numbers of the domain walls have different conductivity, the conductivity of the ferroelectric material is improved. Therefore, different resistance states can be written under different writing voltages; stable existence of domain walls with different inclination angles / lengths / numbers is realized by applying bias voltage, so that stable storage of different resistance state information is realized; by applying a reading pulse with a relatively small voltage, the reading of polymorphic information is realized according to the magnitude of a reading current. The ferroelectric memory constructed by the invention has the advantages of multiple states, high density, rapid write-in and read and the like, and provides a new technical support for the development of neuromorphic calculation and artificial intelligence accelerators.

Description

Technical Field

[0001] This invention belongs to the field of ferroelectric storage device technology, specifically relating to a multi-state ferroelectric memory and its operation method. Background Technology

[0002] With the rapid rise of disruptive technologies such as big data and artificial intelligence, the demand for information storage and data processing is experiencing explosive growth. Firstly, the total amount of data is increasing exponentially, with the global data volume projected to reach 175 ZB by 2025. Secondly, the demand for data processing speed is also growing explosively. With the rapid development of large-scale modeling, the training and inference of large models are placing increasingly higher demands on high-bandwidth, high-capacity storage chips. Currently, computers based on the von Neumann architecture suffer from severely limited computing performance due to the separation of storage and processing units, constituting a "memory wall" problem. New data processing and storage paradigms urgently need to be developed and applied. Currently, ferroelectric memories, with their nanosecond-level operating speeds and unlimited fatigue cycles (>10), are a promising candidate for this technology. 14 Ferroelectric memories (FEMs) have attracted widespread attention and research due to their high energy efficiency and non-volatility. Among various FEMs, 1T1C-based FEMs are gradually standing out, especially HfO2 FEMs, which are currently receiving extensive research. However, since 1T1C FEMs rely on charge integration technology for information reading, the area of ​​the ferroelectric capacitor needs to be maximized to avoid misreading, hindering the miniaturization of FEMs. Furthermore, the degradation of ferroelectricity at extreme sizes and fluctuations in the threshold voltage further impede the miniaturization process of FEMs. The ferroelectric domain wall memory proposed by Jiang et al. (CN201510036526.X, CN201510036586.1, CN201610098138.9, US10403348, JP2017-562045) is based on the resistance change caused by the generation and erasure of nano-ferroelectric domain walls, solving the problem of charge integration in traditional ferroelectric memories. Furthermore, due to its self-gating characteristic, the ferroelectric domain wall memory can achieve high-density three-dimensional stacked storage, significantly improving the storage density of ferroelectric memories. However, currently, ferroelectric domain wall memories can only achieve "0" and "1" storage, not multi-state storage, which limits further improvements in storage density. Since the conductivity of ferroelectric domain walls is related to the domain wall tilt angle, domain wall length, and number of domain walls, this invention proposes a specific multi-state ferroelectric memory structure and its operation method. This allows for control of the domain wall tilt angle, domain wall length, and number of domain walls under different voltages, thereby enabling a single device to have multiple or even theoretically infinite storage states. Furthermore, it achieves nanosecond-level write speeds and excellent fatigue performance, significantly increasing the upper limit of storage density for ferroelectric domain wall memories. This is beneficial for the application of ferroelectric domain wall memories in large-scale models and artificial intelligence fields. Summary of the Invention

[0003] The purpose of this invention is to propose a ferroelectric memory with high storage density and fast read / write speed for storing polymorphic information, and its operation method, so as to provide technical support for the development of neuromorphic computing and artificial intelligence accelerators.

[0004] The multi-state ferroelectric memory provided by this invention comprises: a ferroelectric substrate, ferroelectric bumps, a first electrode, a second electrode, a first domain region, a second domain region, a first predetermined domain wall, and a second predetermined domain wall. The positional relationship of each structure is as follows: Figure 1 As shown. It should be noted that... Figure 1 This is a basic structural diagram of the multi-state ferroelectric memory, and the shapes of each structure are not specified. The polarization direction is used as an identifier; the direction in which the ferroelectric substrate is polarized is positive, and the opposite direction is negative. The first electrode is located in the positive direction of the ferroelectric substrate, and the second electrode is located in the negative direction. The area sandwiched between the first and second electrodes is a ferroelectric bump, which is a domain flipping region. A voltage is applied between the first and second electrodes to flip the domains in the shortest gap; the flipped domain region is the first domain region. The domain wall formed by the first domain region and other unflipped domains is the first preset domain wall (e.g., ...). Figure 1 (As shown by the long underline), the domains in the first domain region exhibit non-volatile characteristics. When a write voltage is applied between the first and second electrodes, more flipped domains are generated near the first domain region; this flipped region is called the second domain region. The second domain region is an extension of the first domain region, and its size changes with the write voltage; the higher the write voltage, the larger the second domain region. The domain wall formed by the second domain region and the unflipped domains is the second predetermined domain wall (e.g., ...). Figure 1 (As shown by the dashed line), the shape (tilt angle / length / number) of the second preset domain wall changes due to the influence of the write voltage, and its conductivity also changes continuously. The second preset domain wall is a key structure for the formation of polymorphism in ferroelectric memory. The domains in the second domain region can have volatile or non-volatile characteristics. When an erase operation is performed, the domains in the second domain region will flip back to their original polarization direction, and the second domain region and the second preset domain wall disappear. At this time, only the first domain region and the first preset domain wall still exist.

[0005] The operation method of the polymorphic information memory provided by this invention involves applying a voltage between the first and second electrodes to generate different electric field distributions within the ferroelectric material. Under different electric field intensities, different domain flipping regions are achieved, forming different domain wall tilt angles / lengths / numbers. These different domain wall tilt angles / lengths / numbers have different conductivity. By applying a specific DC bias voltage, domain walls with different tilt angles / lengths / numbers can all exist stably, thereby realizing the storage of polymorphic information. The specific steps are as follows:

[0006] (1) A groove region is formed by etching on a ferroelectric substrate, electrode material is filled into the groove, and electrode material in other areas outside the groove is removed by chemical mechanical polishing (CMP) technology. The area between adjacent grooves is a ferroelectric storage cell, and the electrode material on both sides contacts the ferroelectric bump to form the first electrode and the second electrode.

[0007] (2) A first preset electric field is applied between the first electrode and the second electrode, causing the domains in the first domain region of the ferroelectric material between the two electrodes to undergo polarization reversal, forming a first preset domain wall with the unreversed domains at the bottom. The domains in the first domain region have non-volatile characteristics, and their polarization direction does not change in subsequent operations. The first preset domain wall has the highest tilt angle, the shortest domain wall length, and the highest number of domain walls, representing the initial state after the polymorphic ferroelectric memory information is erased, and has the highest conductivity value. Simultaneously, the domains in the first domain region provide nucleation sites for the subsequent reversal of domains in the second domain region, significantly reducing the domain reversal nucleation energy in the second domain region.

[0008] (3) After forming the first preset domain wall, a write voltage is applied between the first and second electrodes, causing polarization reversal of the domains in the second domain region between the two electrodes, thus forming the second preset domain wall. The domains in the second domain region are volatile, therefore the formed second preset domain wall is also volatile. The tilt angle / length / number of the second preset domain wall decreases / increases / decreases with increasing write voltage. Since a smaller tilt angle / longer length / fewer number of domain walls results in poorer conductivity, the conductivity of the second preset domain wall decreases with increasing write voltage, achieving polymorphic information writing.

[0009] (4) After the second preset domain wall is formed, in order to stably maintain the written domain wall, a DC bias voltage needs to be applied between the first electrode and the second electrode, so that the tilt angle / length / number of the written second preset domain wall can be kept stable, thus realizing the preservation of polymorphic information.

[0010] (5) After writing the second preset domain wall, a read voltage is applied between the first electrode and the second electrode. Since the tilt angle / length / number of the second preset domain wall can vary with the magnitude of the write voltage, multiple conductance values ​​are formed, which in turn affect the magnitude of the read current. By obtaining the magnitude of the device read current, polymorphic information reading is realized.

[0011] (6) After the DC bias is removed, since the domains in the second domain region are volatile, the polarization direction of the domains in the second domain region will return to the initial polarization direction, causing the second preset domain wall to disappear and return to the position of the first preset domain wall, thus realizing the erasure of polymorphic information. If the domains in the second domain region are non-volatile, the above domain wall information can be erased by applying a negative voltage erase voltage, thus realizing the erasure of polymorphic information.

[0012] The multi-state ferroelectric memory operation method of this invention involves writing, reading, and erasing. Details of the operation method are as follows:

[0013] (1) Write operation: The write voltage is applied between the first electrode and the second electrode. After the write voltage is removed, the DC bias voltage is applied between the first electrode and the second electrode to retain the written information. By changing the magnitude of the write voltage, different second preset domain wall tilt angles / lengths / numbers can be created to achieve polymorphic information writing.

[0014] (2) Reading operation: The read voltage is applied between the first electrode and the second electrode. Since the tilt angle / length / number of the second preset domain walls are variable, the device has multiple conductance values. By obtaining the magnitude of the read current, the conductance value of the device can be obtained, realizing the reading of polymorphic information. After the read voltage is removed, a DC bias voltage is applied between the first electrode and the second electrode to maintain the read information.

[0015] (3) Erasure operation: Remove the DC bias voltage between the first electrode and the second electrode. Since the domains in the second domain region are volatile, the domains in the second domain region will return to the initial polarization direction, the second preset domain wall will disappear, and the domain wall will return to the position of the first preset domain wall, thus realizing the erasure of polymorphic information.

[0016] Furthermore, the domain wall tilt angle and the write voltage follow a relationship that the larger the write voltage, the smaller the domain wall tilt angle.

[0017] Furthermore, the domain wall length and the write voltage follow a relationship that the larger the write voltage, the longer the domain wall length.

[0018] Furthermore, the number of domain walls and the magnitude of the write voltage follow a relationship that the larger the write voltage, the fewer the number of domain walls.

[0019] Furthermore, the upper limit of the number of polymorphic information is fundamentally determined by the number of lattice sites where the second preset domain wall is located. Since the second preset domain wall can be formed at any lattice site in the ferroelectric material, the number of polymorphic states can theoretically approach infinity. The actual number of polymorphic information that can be written into the ferroelectric memory is limited by the number of different write voltage excitations; the more different write voltage excitations, the more polymorphic information can be realized.

[0020] Furthermore, the write voltage ranges from 0V to 30V, and the pulse width is greater than or equal to 100ps and less than or equal to 100ms.

[0021] Furthermore, the DC bias voltage is less than the minimum write voltage to ensure that the DC bias voltage does not change the tilt angle / length / number of the second preset domain walls. When the device is not performing write, erase, or read operations, the voltage difference between the first and second electrodes is maintained at the DC bias voltage level. The bias voltage is between 0V and 5V.

[0022] Furthermore, the read voltage is less than the minimum write voltage to ensure that the read voltage does not change the tilt angle / length / number of the second preset domain walls. The read voltage is greater than or equal to the DC bias voltage. The read voltage is between 0V and 10V, and the pulse width is greater than or equal to 100ps and less than or equal to 100ms.

[0023] Furthermore, the wiping voltage ranges from 0V to -30V, and the pulse width is greater than or equal to 100ps and less than or equal to 100ms.

[0024] Furthermore, before performing a write operation, an erase operation is first performed so that the polymorphic ferroelectric memory can be rewritten with information.

[0025] Furthermore, the ferroelectric material used in the ferroelectric substrate is selected from one or more of the following:

[0026] Lithium niobate, lithium tantalate, and bismuth ferrite; wherein the lithium niobate, lithium tantalate, and bismuth ferrite are single crystals or thin films, doped with MgO, Mn2O5, or Fe2O3, or blackened lithium niobate or lithium tantalate; the crystal orientations of lithium niobate and lithium tantalate include: X-cut, Z-cut, Y-cut, and oblique-cut crystals.

[0027] Furthermore, the materials of the first electrode and the second electrode include at least one of the following materials:

[0028] Tungsten, titanium, chromium, copper, nickel, aluminum, platinum, iridium, ruthenium, tantalum, niobium, tungsten nitride, titanium nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, tantalum nitride.

[0029] The beneficial effects of this invention are:

[0030] This invention provides a multi-state ferroelectric memory structure and its operation method, which can realize multiple or even theoretically infinite storage states in a single storage cell, significantly improving the storage density limit of ferroelectric domain wall memory, while ensuring that the storage cell still has nanosecond-level write speed and excellent fatigue performance. This is beneficial to meeting the requirements of large models and artificial intelligence for high-bandwidth, high-capacity storage chips. Attached Figure Description

[0031] Figure 1 This is a conceptual diagram of a polymorphic ferroelectric memory used for explaining its principles.

[0032] Figure 2 This is a schematic diagram illustrating the structural principle of a multi-state ferroelectric memory based on changing domain wall tilt angle, as described in Example 1.

[0033] Figure 3 The results of the current-voltage (IV) curve test of the multi-state characteristics of the lithium niobate ferroelectric memory in Example 1 are shown.

[0034] Figure 4 The results are the continuous electrical pulse test curves for the multi-state characteristics of the lithium niobate ferroelectric memory in Example 1.

[0035] Figure 5 The test curves of the current-time (It) of each resistive state of the multi-state characteristics of the lithium niobate ferroelectric memory in Example 1 are shown.

[0036] Figure 6 The curves show the performance of the lithium niobate ferroelectric memory in Example 1 under DC bias.

[0037] Figure 7 The results are fatigue test results of the multi-state characteristics of the lithium niobate ferroelectric memory in Example 1.

[0038] Figure 8 This is the short-circuit pulse write voltage waveform with a pulse width of 1.5ns and a voltage magnitude of 2.9V in Example 1.

[0039] Figure 9 The waveforms for current testing under a 2V read voltage after different uppercase and lowercase voltages with a 1.5ns pulse width in Example 1 are shown.

[0040] Figure 10 The result of domain wall tilt angle variation with write voltage based on phase field simulation in Example 1.

[0041] Figure 11 This is a schematic diagram of the principle of the polymorphic ferroelectric memory structure based on changing the domain wall length in Example 2.

[0042] Figure 12 This is a schematic diagram of the principle of the polymorphic ferroelectric memory structure based on changing the number of domain walls in Example 3.

[0043] In the figure, the following labels are used: 101 is the ferroelectric substrate, 102 is the first electrode, 103 is the second electrode, 104 is the first domain region, 105 is the second domain region, 106 is the first preset domain wall, and 107 is the second preset domain wall. Detailed Implementation

[0044] The present invention will be further described below with reference to the accompanying drawings and embodiments. It should be understood that the specific implementation methods described herein are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the device structure and electrical operation method proposed in this invention without inventive effort are within the scope of protection of this invention.

[0045] In the embodiments, the terms "first electrode" and "second electrode" are used to illustrate the basic principle structure. However, it should be noted that in the examples of this application, the two-electrode model is the most basic storage architecture, which has scalability and universality to achieve local flipping of electric domains with different regional shapes or different numbers.

[0046] In addition, in this embodiment, the terms "first domain region" and "second domain region" are used only to distinguish functions and roles, and do not limit their structural shape, quantity or other characteristics.

[0047] In the accompanying drawings, the thickness of layers and regions has been exaggerated for clarity, and the dimensional proportions between the parts shown do not reflect the actual dimensional proportions.

[0048] In the embodiments, the domain direction or polarization direction is given exemplarily, and terms such as "X-cut" or "Z-cut" describing the domain direction are used as examples to facilitate a detailed explanation of the principle. It should be understood that the domain direction or polarization direction is not limited to the directions shown in the embodiments of this application.

[0049] In the electrical tests of this embodiment, a finite number of different write voltages are used for demonstration purposes, but this does not represent an upper limit on the number of polymorphisms in the multi-state ferroelectric memory. It should be understood that the upper limit of the number of polymorphisms in the multi-state ferroelectric memory is fundamentally determined by the number of lattice sites where the second preset domain wall is located. Since domain walls can be formed at any lattice site in the ferroelectric material, there are infinitely many achievable polymorphic resistance values. In practice, the number of polymorphisms in the multi-state ferroelectric memory is limited by the number of different write voltage excitations; the more different write voltage excitations, the more polymorphisms can be achieved.

[0050] Example 1:

[0051] In this embodiment, a multi-state ferroelectric memory structure and its operation method based on changing the domain wall tilt angle are provided. The principle is described in [link to relevant documentation]. Figure 1As shown, a first electrode 102 and a second electrode 103 are formed in the ferroelectric substrate 101 by etching, filling electrodes, and performing a CMP process. The first electrode 102 is rectangular in shape (approximately 150 nm deep and 150 nm wide), while the second electrode is also rectangular in shape (approximately 150 nm deep and 150 nm wide), with another rectangle (approximately 10 nm deep and 100 nm wide) extending from the upper left surface.

[0052] When a first preset electric field opposite to the polarization direction of the ferroelectric substrate 101 is applied to the first electrode 102 and the second electrode 103, the domains of the first domain region 104 between the first electrode 102 and the second electrode 103 are flipped, forming a first preset domain wall 106. In subsequent operations, the domains of the first domain region 104 no longer change their polarization direction, so in a stable state, the domain wall is at the position of the first preset domain wall, and the domain wall tilt angle is at its maximum value.

[0053] Further, after forming the first preset domain wall 106, the write voltage is applied between the first electrode 102 and the second electrode 103, causing the domains of the second domain region 105 between the two electrodes to undergo polarization reversal, forming the second preset domain wall 107. By controlling the magnitude of the write voltage, different areas of domains in the second domain region 105 can be flipped. For example, as the magnitude of the write voltage increases, the domains in the second domain region will gradually flip to regions 1051, 1052, and 1053, correspondingly forming second preset domain walls 1071, 1072, and 1073, and the corresponding domain wall tilt angle gradually decreases, resulting in a gradual weakening of the conductivity of the domain walls. 1051, 1052, and 1053 represent the shapes formed by the second domain region under the three write voltages, and only represent the possible shapes formed by the second domain region. 1051, 1052, and 1053 have an inclusion relationship, that is, 1052 includes 1051, and 1053 includes both 1051 and 1052. 1071, 1072, and 1073 represent the second preset domain walls corresponding to the different shapes of the second domain regions, respectively. They only represent the possible positions of the second preset domain walls, and the domain wall tilt angles of the three are in the order 1071 > 1072 > 1073. Therefore, changing the write voltage can change the tilt angle of the second preset domain wall, thus realizing the writing of polymorphic information.

[0054] Furthermore, after the second preset domain wall 107 is formed, applying the DC bias voltage between the first electrode 102 and the second electrode 103 can stabilize the second preset domain wall and achieve polymorphic information retention.

[0055] Furthermore, after maintaining the second preset domain wall 107, the read voltage is applied between the first electrode 102 and the second electrode 103. Since different second preset domain walls have different domain wall tilt angles, different conductance values ​​of the device can be obtained by reading the current magnitude under the read voltage. By mapping the device conductance value with the weight of the stored information, polymorphic information reading can be realized.

[0056] Furthermore, after the DC bias is removed, due to the volatile nature of the ferroelectric material at the contact interface between the domains and the electrode in the second domain region, the domains in the second domain region 105 exhibit volatile characteristics as a whole. Therefore, the domains in the second domain region will automatically flip back to the initial polarization direction, the second preset domain wall 107 disappears, and the domain wall returns to the position of the first preset domain wall 106, thus realizing the erasure of polymorphic information.

[0057] Furthermore, such as Figure 2 As shown, the B1500 semiconductor parameter analyzer was used to analyze... Figure 1 The current-voltage (IV) test results of the demonstrated device show that the domain walls exhibit different conductivity after applying different write voltages, and overall, the domain wall conductivity gradually decreases as the write voltage increases.

[0058] Furthermore, such as Figure 3 As shown in the upper half, the voltage waveform edited using the Agilent 33250A arbitrary waveform generator was first applied to the device. Then, the magnitude of the write voltage was continuously changed, and the current resistance state of the device was obtained using the same read voltage. The test results are shown in the lower half. As the magnitude of the write voltage increases, the device current obtained in the read voltage shows an inverse relationship with the write voltage. This indicates that in this embodiment, the device exhibits multi-state characteristics under pulse testing.

[0059] Furthermore, in this embodiment, the stability of the device's polymorphic information retention was tested. First, the relationship between the current obtained by the device under the read voltage and time was tested, and the results are as follows: Figure 4 As shown; secondly, the changes in the device's multi-state information after maintaining the DC bias for different times were tested, and the results are as follows. Figure 5 As shown in the figure. All the above results demonstrate the stability of the device's polymorphic information over a long period.

[0060] Furthermore, the results of the device's polymorphic performance after fatigue are as follows: Figure 6 As shown, the device has a fatigue cycle greater than 10. 9 Normal writing and reading of polymorphic information can still be achieved afterwards.

[0061] Furthermore, in this embodiment, performance tests were conducted on nanosecond-level write speeds, using methods such as... Figure 7 The test waveform with a pulse width of 1.5 ns and a voltage ranging from 2.9 V to 8.5 V, shown below, is applied as the write voltage between the first and second electrodes. Subsequently, a voltage waveform with a pulse width of 1 μs and a voltage of 2 V is used as the read voltage to read the current polystate information of the device. The resulting current change is shown below. Figure 8 As shown, as the write voltage decreases, the read current gradually increases, and the polymorphic characteristics are obvious, verifying that the device still has polymorphic characteristics at the nanosecond level.

[0062] Furthermore, through phase-field simulation, the flipping region of the second domain of the device in this embodiment under different write voltages was simulated, and the results are as follows: Figure 9 As shown in the figure. The results show that as the normalized electric field gradually increases, the domain wall tilt angle gradually decreases, which is consistent with the electrical test results.

[0063] Example 2:

[0064] In this embodiment, a multi-state ferroelectric memory structure and its operation method based on changing domain wall length are provided, the principle of which is described in [reference needed]. Figure 10 As shown. By extending the lateral length of the first electrode 102 and the second electrode 103 to 2.5 μm and the depth to 150 nm, different lateral electric field distributions can be generated inside the ferroelectric material 101.

[0065] When a first preset electric field, opposite to the polarization direction of the ferroelectric substrate 101, is applied between the first electrode 102 and the second electrode 103, the domains in the first domain region 104 between the first electrode 102 and the second electrode 103 flip, forming a first preset domain wall 106. In subsequent operations, the domains in the first domain region 104 no longer change their polarization direction, so in a stable state, the domain wall is at the position of the first preset domain wall, and the domain wall length is at its minimum value.

[0066] Furthermore, by applying the write voltage between the first electrode 102 and the second electrode 103, polarization reversal of domains in different regions of the second domain region 105 can be achieved, forming different second preset domain walls 107. As the magnitude of the write voltage increases, domains within the second domain region will gradually flip to regions 1051, 1052, and 1053, correspondingly forming second preset domain walls 1071, 1072, and 1073, and the length of the corresponding domain walls gradually increases, resulting in a gradual decrease in the conductivity of the domain walls. 1051, 1052, and 1053 represent the shapes formed by the second domain region under the three write voltages, and only represent the possible shapes formed by the second domain region. There is an inclusion relationship between 1051, 1052, and 1053, that is, 1052 includes 1051, and 1053 includes both 1051 and 1052. 1071, 1072, and 1073 represent the second preset domain walls corresponding to the different shapes of the second domain regions, respectively. They only represent the possible positions of the second preset domain walls, and the domain wall tilt angles of the three are in the order 1071 > 1072 > 1073. Therefore, changing the write voltage can change the length of the second preset domain wall, thereby realizing the writing of polymorphic information.

[0067] Furthermore, after the second preset domain wall 107 is formed, applying the DC bias voltage between the first electrode 102 and the second electrode 103 can keep the length of the second preset domain wall stable, thereby achieving polymorphic information preservation.

[0068] Furthermore, after maintaining the second preset domain wall 107, the read voltage is applied between the first electrode 102 and the second electrode 103. Since different second preset domain walls have different domain wall lengths, different conductance values ​​of the device can be obtained by reading the current magnitude under the read voltage. By mapping the device conductance value with the weight of the stored information, the reading of polymorphic information can be realized.

[0069] Furthermore, after the DC bias is removed, the unsaturated polarization charges at both ends of the domains written in the second domain region form a huge depolarization field, causing the domains in the second domain region 105 to exhibit volatile characteristics. Therefore, the domains in the second domain region will automatically flip back to the initial polarization direction, the second preset domain wall 107 disappears, and the domain wall returns to position 106, realizing the erasure of polymorphic information.

[0070] Example 3:

[0071] In this embodiment, a multi-state ferroelectric memory structure and its operation method based on changing the number of domain walls and the non-volatile nature of the second domain region are provided. The principle is described in [reference needed]. Figure 11As shown. By increasing the longitudinal depth of the first electrode 102 and the second electrode 103 to 300 nm and the width to 150 nm, due to the randomness of the process, different preferential nucleation regions are formed in the contact area between the ferroelectric material and the electrode. Under the same electric field, nucleation is preferentially performed in the region with lower nucleation energy.

[0072] By applying a write voltage opposite to the polarization direction of the ferroelectric substrate 101 between the first electrode 102 and the second electrode 103, polarization reversal of domains in different regions of the second domain region 105 can be achieved, forming different numbers of second preset domain walls. As the write voltage increases, domains within the second domain region will gradually flip to regions 1051, 1052, and 1053, and correspondingly, the number of second preset domain walls gradually decreases to 5, 4, and 2, respectively. The decrease in the number of domain walls leads to a weakening of the conductivity of the domain walls. 1051, 1052, and 1053 represent the shapes formed by the second domain region under the three write voltages, and only represent the possible shapes of the second domain region. There is an inclusion relationship between 1051, 1052, and 1053, i.e., 1052 includes 1051, and 1053 includes both 1051 and 1052. Therefore, polymorphic information can be written by varying the write voltage.

[0073] Furthermore, after the second preset domain wall is formed, applying the bias voltage between the first electrode 102 and the second electrode 103 can keep the number of the second preset domain walls stable, thereby preserving polymorphic information.

[0074] Furthermore, after maintaining the second preset domain wall, the read voltage is applied between the first electrode 102 and the second electrode 103. Since the second preset domain wall has a different number of domain walls, different conductance values ​​of the device can be obtained by reading the current magnitude under the read voltage. By mapping the device conductance value with the weight of the stored information, the reading of polymorphic information can be realized.

[0075] Furthermore, since the domains in the second domain region are non-volatile at this time, after the DC bias is removed, when an erasure voltage with the same polarization direction as the ferroelectric substrate 101 is applied between the first electrode 102 and the second electrode 103, the domains in the second domain region 105 can be flipped to the initial polarization direction, the second preset domain wall disappears, the number of domain walls is zero at this time, and the erasure of polymorphic information is realized.

[0076] In summary, the multi-state ferroelectric memory structure and its operation method provided by this invention realize the writing and reading of multiple or even theoretically infinite multi-state resistance values ​​in a single device, and can achieve nanosecond-level writing speed and excellent fatigue performance. This significantly improves the theoretical storage density limit of ferroelectric memory, which is conducive to the development of ferroelectric memory into high-density, high-speed and high-energy-efficiency memory chips, and is beneficial to applications in fields such as large models, artificial intelligence and data centers.

Claims

1. A multi-state ferroelectric memory, characterized in that, include: Ferroelectric substrate, ferroelectric bump, first electrode, second electrode, first domain region, second domain region, first preset domain wall, second preset domain wall; Using polarization direction as a marker, the direction indicated by the polarization of the ferroelectric substrate is positive, and the opposite direction is negative. The first electrode is located in the positive direction of the ferroelectric substrate, and the second electrode is located in the negative direction. The area sandwiched between the first and second electrodes is a ferroelectric bump, which is a domain flipping region. Applying a voltage between the first and second electrodes causes the domains in the shortest gap to flip, and the flipped domain region is called the first domain region. The domain wall formed by the first domain region and other unflipped domains is called the first preset domain wall. The domains in the first domain region have non-volatile characteristics. Applying a write voltage between the first and second electrodes generates more flipped domains near the first domain region; this flipped region is called the second domain region. The second domain region is an extension of the first domain region, and its size changes with the write voltage; the larger the write voltage, the larger the second domain region. The domain wall formed by the second domain region and the unflipped domains is called the second preset domain wall. The shape of the second preset domain wall changes due to the influence of the write voltage, and its conductivity also changes continuously. The shape of the domain wall includes its tilt angle, length, and number. The second preset domain wall is a key structure for the formation of polymorphism in ferroelectric memory; the domains in the second domain region have volatile or non-volatile characteristics; when an erase operation is performed, the domains in the second domain region flip back to their original polarization direction, and the second domain region and the second preset domain wall disappear. At this time, only the first domain region and the first preset domain wall still exist.

2. The polymorphic information storage device according to claim 1, characterized in that, The ferroelectric material used in the ferroelectric substrate is selected from lithium niobate, lithium tantalate, and bismuth ferrite; wherein, the lithium niobate, lithium tantalate, and bismuth ferrite are single crystals or thin films, lithium niobate salts, lithium tantalate salts, or bismuth ferrite salts doped with MgO, Mn2O5, or Fe2O3, or blackened lithium niobate salts and blackened lithium tantalate salts; the crystal orientation of lithium niobate and lithium tantalate includes: X-cut, Z-cut, Y-cut, and oblique-cut crystals.

3. The polymorphic information storage device according to claim 1, characterized in that, The materials of the first electrode and the second electrode are selected from tungsten, titanium, chromium, copper, nickel, aluminum, platinum, iridium, ruthenium, tantalum, niobium, tungsten nitride, titanium nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, and tantalum nitride.

4. An operation method for a polymorphic information memory as described in any one of claims 1-3, characterized in that, The process involves applying a voltage between the first and second electrodes to generate different electric field distributions within the ferroelectric material. Under different electric field strengths, different domain flipping regions are achieved, resulting in different domain wall tilt angles, lengths, and numbers. These different domain wall tilt angles, lengths, and numbers exhibit different electrical conductivities. By applying a specific DC bias voltage, domain walls of different tilt angles, lengths, and numbers can stably exist, thereby enabling the storage of multi-state information. The specific steps are as follows: (1) A groove region is formed by etching on a ferroelectric substrate, electrode material is filled into the groove, and electrode material in other areas outside the groove is removed by chemical mechanical polishing (CMP) technology. The area between adjacent grooves is a ferroelectric storage cell, and the electrode material on both sides contacts the ferroelectric bump to form the first electrode and the second electrode. (2) A first preset electric field is applied between the first electrode and the second electrode to cause the domains in the first domain region of the ferroelectric material between the two electrodes to undergo polarization reversal, forming a first preset domain wall with the bottom non-reversed domains; the domains in the first domain region have non-volatile characteristics, and the domains in the first domain region no longer change polarization direction in subsequent operations; the first preset domain wall has the highest tilt angle, the shortest domain wall length, and the most domain walls, and is the initial state after the information of the polymorphic ferroelectric memory is erased, with the highest conductivity value; at the same time, the domains in the first domain region provide nucleation sites for the reversal of the domains in the subsequent second domain region, greatly reducing the domain reversal nucleation energy in the second domain region; (3) After the first preset domain wall is formed, a write voltage is applied between the first electrode and the second electrode to cause the domains in the second domain region between the two electrodes to undergo polarization reversal, thereby forming the second preset domain wall; the domains in the second domain region have volatile characteristics, and the formed second preset domain wall also has volatile characteristics. The second preset domain wall tilt angle, length, and number decrease, increase, and decrease accordingly as the write voltage increases. Since the smaller the domain wall tilt angle, the longer the length, and the fewer the number, the worse the domain wall conductivity, the second preset domain wall conductivity value decreases as the write voltage increases, thus realizing polymorphic information writing. (4) After the second preset domain wall is formed, in order to stably maintain the written domain wall, a DC bias voltage is applied between the first electrode and the second electrode to keep the tilt angle, length and number of the written second preset domain wall stable, thereby realizing the preservation of polymorphic information. (5) After writing the second preset domain wall, a read voltage is applied between the first electrode and the second electrode. Since the tilt angle, length and number of the second preset domain wall can vary with the magnitude of the write voltage, multiple conductance values ​​are formed, which in turn affect the magnitude of the read current. By obtaining the magnitude of the device read current, polymorphic information reading is realized. (6) After the DC bias is removed, since the domains in the second domain region are volatile, the polarization direction of the domains in the second domain region changes back to the initial polarization direction, causing the second preset domain wall to disappear and the domain wall to return to the position of the first preset domain wall, thus realizing the erasure of polymorphic information; if the domains in the second domain region are non-volatile, the above domain wall information is erased by applying a negative voltage erasure voltage, thus realizing the erasure of polymorphic information.

5. The operation method of the polymorphic information memory according to claim 4, characterized in that, The specific details of the write, read, and erase operations are as follows: (1) Write operation: Apply the write voltage between the first electrode and the second electrode. After removing the write voltage, apply the DC bias voltage between the first electrode and the second electrode to maintain the written information. By changing the magnitude of the write voltage, different second preset domain wall tilt angles, lengths, and numbers can be created to achieve polymorphic information writing. (2) Reading operation: The reading voltage is applied between the first electrode and the second electrode. Since the tilt angle, length and number of the second preset domain wall are variable, the device has multiple conductance values. By obtaining the reading current, that is, obtaining the conductance value of the device, polymorphic information reading is realized. After the reading voltage is removed, a DC bias voltage is applied between the first electrode and the second electrode to maintain the read information. (3) Erasure operation: Remove the DC bias voltage between the first electrode and the second electrode. Since the domains in the second domain region are volatile, the domains in the second domain region return to the initial polarization direction, the second preset domain wall disappears, and the domain wall returns to the position of the first preset domain wall, thus realizing the erasure of polymorphic information.

6. The operation method of the polymorphic information memory according to claim 5, characterized in that: The domain wall tilt angle and the write voltage follow a relationship that the larger the write voltage, the smaller the domain wall tilt angle. The domain wall length and the write voltage are related by the fact that the higher the write voltage, the longer the domain wall length. The number of domain walls and the write voltage are related by the following relationship: the higher the write voltage, the fewer the number of domain walls.

7. The operation method of the polymorphic information memory according to claim 3, characterized in that, The upper limit of the number of polymorphic information is determined by the number of the second preset domain wall positions at the lattice sites; the number of polymorphic information that can be written to the ferroelectric memory is limited by the number of different write voltage excitations. The more different write voltage excitations there are, the more polymorphic information can be realized.

8. The operation method of the polymorphic information memory according to claim 3, characterized in that: The write voltage ranges from 0V to 30V, and the pulse width is greater than or equal to 100ps and less than or equal to 100ms. The DC bias voltage is less than the minimum value of the write voltage to ensure that the DC bias voltage does not change the tilt angle, length, or number of the second preset domain walls; when the device is not performing write, erase, or read operations, the voltage difference between the first electrode and the second electrode is maintained at the DC bias voltage level; the bias voltage is 0V to 5V.

9. The operation method of the polymorphic information memory according to claim 3, characterized in that, The read voltage is less than the minimum value of the write voltage to ensure that the read voltage does not change the tilt angle / length / number of the second preset domain walls; the read voltage is greater than or equal to the DC bias voltage; the read voltage is 0V to 10V with a pulse width greater than or equal to 100ps and less than or equal to 100ms; the erase voltage is 0V to -30V with a pulse width greater than or equal to 100ps and less than or equal to 100ms.

10. The operation method of the polymorphic information memory according to claim 3, characterized in that, Before performing a write operation, an erase operation is first performed so that the polymorphic ferroelectric memory can be rewritten with information.

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