Preparation process and layout of power chip with cellular temperature detection function
By fabricating polycrystalline silicon Schottky diodes within the trenches of power chips, the problem of traditional methods being unable to detect local temperatures in devices has been solved, enabling real-time monitoring and accurate detection of the internal temperature of the active region of power chips.
Patent Information
- Application Number
- CN202511112814.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-09
- Publication Date
- 2025-11-14
AI Technical Summary
Traditional power chip temperature detection methods cannot effectively detect the local temperature of devices, especially in switching power supply applications.
A polycrystalline silicon Schottky diode is fabricated in the first trench of a power chip. A Schottky junction is formed by growing an oxide layer on the trench sidewall and filling it with polycrystalline silicon. The diode is formed by contacting the polycrystalline silicon with a metal to detect temperature changes in the active region of the device.
It enables real-time monitoring of the internal temperature of the active region of the power chip, isolates the influence of the switching power supply circuit, and ensures accurate detection of the overall and local junction temperature of the device.
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Figure CN120957433A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of this application belong to the field of semiconductor technology, and in particular relate to a process and layout for fabricating a power chip with cell temperature detection function. Background Technology
[0002] In switching power supply applications, it is often necessary to detect and control the temperature of power chips. Traditional temperature detection is limited to power detection or placing a diode temperature sensor near the power chip. However, the above methods cannot detect the local temperature of the device. Summary of the Invention
[0003] To address or mitigate the problems in the prior art, in a first aspect, embodiments of this application provide a process for fabricating a power chip with cell temperature detection functionality, comprising fabricating a polycrystalline silicon Schottky diode within a first trench of the chip, the process including:
[0004] A first trench is formed by etching the upper surface of the epitaxial layer, and a first oxide layer is grown on the sidewall of the first trench;
[0005] The first trench is filled with a first polycrystalline silicon.
[0006] The excess first polysilicon on the upper surface of the epitaxial layer is removed by etching, and the first polysilicon in the first trench is etched until the remaining portion of the first polysilicon in the first trench is removed.
[0007] The first trench is filled with a second polycrystalline silicon.
[0008] A second oxide layer is deposited on the upper surface of the epitaxial layer;
[0009] A first contact hole is formed in the first trench, the first contact hole penetrating the second oxide layer and extending into the second polysilicon;
[0010] The first contact hole is filled with the first metal;
[0011] A second metal is deposited on top of the first metal layer;
[0012] A third metal is deposited on top of the second metal layer, and the first and second electrodes are brought out after exposure and etching.
[0013] In a preferred embodiment of this application, the first oxide layer on the sidewall of the first trench is prepared using the same process as the second oxide layer on the sidewall of the other trenches in the active region of the chip.
[0014] In a preferred embodiment of this application, the doping concentration of the second polysilicon in the first trench is less than the doping concentration of the first polysilicon.
[0015] In a preferred embodiment of this application, the first electrode forms the positive terminal of the temperature detection pin, the second electrode is connected to the source or emitter of the chip, and the source or emitter of the chip also serves as the negative terminal of the temperature detection pin.
[0016] In a preferred embodiment of this application, the polycrystalline silicon Schottky diode structural units are spaced apart in the active region of the chip.
[0017] Secondly, embodiments of this application also provide a layout, wherein the process described in any of the first aspects is prepared according to the layout;
[0018] The map includes: a first trench region;
[0019] The first trench area is provided with a first contact hole area;
[0020] The first trench in the first trench region is filled with first polysilicon and second polysilicon sequentially from bottom to top;
[0021] The first contact hole region is used to fill the first metal, and the first metal forms a Schottky junction with the second polysilicon in the first trench region; the first contact hole region is connected to the Schottky lead-out region to lead out the positive electrode of the polysilicon Schottky diode;
[0022] A source lead-out region or an emitter lead-out region is provided outside the active region of the chip to lead out the source or emitter. The source or emitter of the chip also serves as the negative electrode of the polysilicon Schottky diode. The source lead-out region is connected to the first polysilicon.
[0023] The Schottky cathode lead-out region and the source lead-out region or emitter lead-out region are both located in the region above the first trench region.
[0024] Compared with existing technologies, this application provides a power chip fabrication process and layout with cell temperature detection functionality. By introducing a Schottky junction formed by a second polysilicon and a barrier metal, a Schottky diode is formed by direct contact between the Schottky metal and the second polysilicon with a lower doping concentration. When current flows through the active region of the device, generating heat, the lattice conducts the heat to the Schottky junction within the first trench, causing a change in the diode's barrier height and thus altering its forward voltage drop. The real-time temperature inside the active region of the device during operation can be calculated. Using the trench oxide layer as isolation for temperature detection ensures that the overall and local junction temperature detection is unaffected by the switching power supply circuit. Attached Figure Description
[0025] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:
[0026] Figure 1 This is a schematic diagram of the structure corresponding to step S01 in the embodiment of this application;
[0027] Figure 2 This is a schematic diagram of the structure corresponding to step S02 in the embodiment of this application;
[0028] Figure 3 This is a schematic diagram of the structure corresponding to step S03 in the embodiment of this application;
[0029] Figure 4 This is a schematic diagram of the structure corresponding to step S04 in the embodiment of this application;
[0030] Figure 5 This is a schematic diagram of the structure corresponding to steps S05 and S06 in the embodiments of this application;
[0031] Figure 6 This is a schematic diagram of the structure corresponding to steps S07 and S08 in the embodiments of this application;
[0032] Figure 7 This is a schematic diagram of the structure corresponding to steps S09 and S10 in the embodiments of this application;
[0033] Figure 8 This is a schematic diagram of the structure corresponding to step S11 in the embodiment of this application;
[0034] Figure 9 This is a schematic diagram of the structure corresponding to step S12 in the embodiment of this application;
[0035] Figure 10 This is a schematic diagram of the structure corresponding to step S13 in the embodiment of this application;
[0036] Figure 11 This is a schematic diagram of the structure corresponding to step S14 in the embodiment of this application;
[0037] Figure 12 This is a schematic diagram of the structure corresponding to steps S15 and S16 in the embodiments of this application;
[0038] Figure 13 This is a schematic diagram of the layout of this application;
[0039] Figure 14This is another schematic diagram of the layout structure of this application; Detailed Implementation
[0040] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.
[0041] The following section uses a shielded gate trench MOSFET chip as an example to describe in detail the fabrication process of this application.
[0042] In a first aspect, embodiments of this application provide a power chip fabrication process with cell temperature detection function, including:
[0043] Step S01: Etch the first trench 3, the second trench 4 and the third trench 2 on the upper surface of the epitaxial layer 1, and grow the first oxide layer 5 on the sidewalls of the first trench 3, the second trench 4 and the third trench 2.
[0044] It should be noted that, as Figure 1 As shown, a first trench 3, a second trench 4, and a third trench 2 are etched on the upper surface of the epitaxial layer 1. The first trench 3 is primarily for forming a Schottky junction, the second trench 4 is primarily for forming the gate, and the third trench 2 is primarily for forming the source. Furthermore, in this application, multiple first trenches 3 with Schottky junctions can be formed, which facilitates temperature detection in different regions of the entire device. In this embodiment, the first oxide layer on the sidewall of the first trench is fabricated using the same process as the second oxide layer on the sidewall of the other second trenches in the active region of the chip.
[0045] Step S02: Fill the first polysilicon 6 in the first trench 3, the second trench 4 and the third trench 2, and etch away the excess first polysilicon 6 on the upper surface of the epitaxial layer 1.
[0046] It should be noted that, as Figure 2 As shown, the first polysilicon 6 is a source polysilicon, and the source polysilicon is heavily doped.
[0047] Step S03: Etch the first polysilicon 6 in the first trench 3 until the remaining portion of the first polysilicon 6 in the first trench 3 is etched.
[0048] It should be noted that, as Figure 3As shown, after the chip surface is coated with the first photoresist 7 and exposed, the first polysilicon 6 in the first trench 3 is etched only according to the pattern transferred to the silicon surface by the mask. The first polysilicon 6 in the first trench 3 is etched until the remaining part of the first polysilicon 6 in the first trench 3 is etched. This makes it convenient to deposit a second polysilicon 8 with a lower doping concentration on the surface of the first polysilicon 6.
[0049] Step S04: Fill the first trench 3 with a second polysilicon 8;
[0050] It should be noted that, as Figure 4 As shown, the first photoresist 7 is removed, and a second polysilicon 8 is filled into the first trench 3. A Schottky diode is formed by direct contact between the Schottky metal and the lower-doped second polysilicon 8. When current flows through the active region of the device, heat is generated. The lattice conducts the heat to the Schottky junction in the first trench 3, causing a change in the barrier height of the diode and thus altering its forward voltage drop. The real-time temperature inside the active region of the device during operation can be calculated. The first polysilicon 6 in the first trench 3 is heavily doped and acts as a resistor. A first contact hole 15 is formed at the chip edge to lead out the Schottky diode cathode.
[0051] Step S05: Etch the first polysilicon 6 in the second trench 4 until the remaining portion of the first polysilicon 6 in the second trench 4 is etched.
[0052] It should be noted that, as Figure 5 As shown, by setting the second photoresist 9 for photolithography, only the first polysilicon 6 in the second trench 4 can be etched, so that the gate polysilicon can be filled in the second trench 4.
[0053] Step S06: Deposit a third oxide layer 11 in the second trench 4, and perform a thinning etching process on the second oxide layer 11;
[0054] It should be noted that, as Figure 6 As shown, the second photoresist 9 is removed, and a third oxide layer 11 is formed in the second trench 4, which can isolate the third polysilicon 10 and the first polysilicon 6.
[0055] Step S07: Fill the second trench 4 with a third polysilicon 10 and etch back the third polysilicon 10 until the top of the third polysilicon 10 is not higher than the upper surface of the epitaxial layer 1.
[0056] It should be noted that, as Figure 6 As shown, the second trench 4 is filled with a third polysilicon 10, which is a heavily doped type of polysilicon used to fabricate the gate.
[0057] Step S08: A well region 12 is formed in the epitaxial layer 1;
[0058] It should be noted that, as Figure 7 As shown, ion implantation is performed on the upper surface of the epitaxial layer 1 to form a well region 12, mainly to facilitate the formation of a PN junction in the source region.
[0059] Step S9: A first injection region 13 is formed in the well region 12 where the first trench 3 and the second trench 4 are located;
[0060] It should be noted that, as Figure 7 As shown, ion implantation is performed in the well region 12 where the first trench 3 and the second trench 4 are located to form a first implantation region 13, which is used to form the chip channel, as well as the source doped region or the emitter doped region.
[0061] Step S10: Deposit a second oxide layer 14 on the upper surface of the epitaxial layer 1;
[0062] It should be noted that, as Figure 8 As shown, the second oxide layer 14 mainly serves to provide insulation and isolation protection.
[0063] Step S11: A first contact hole 15 is formed in the first trench 3, the first contact hole 15 penetrates the second oxide layer 14 and extends into the second polysilicon 8; and metal is filled into the first contact hole 15.
[0064] It should be noted that, as Figure 9 As shown, if the cathode of the Schottky diode needs to be brought out, the first contact hole 15 needs to be etched.
[0065] Step S12: A second contact hole 16 is formed in the second trench 4, a third contact hole 17 is formed in the epitaxial layer 1, and a fourth contact hole 18 is formed in the third trench 2. The second contact hole 16 penetrates the second oxide layer 14 and extends into the third polysilicon 10. The third contact hole 17 penetrates the second oxide layer 14 and the first implantation region 13 and extends into the well region 12. The fourth contact hole 18 penetrates the second oxide layer 14 and extends into the first polysilicon 6 in the third trench.
[0066] It should be noted that, as Figure 10 As shown, the second contact hole 16, the third contact hole 17, and the fourth contact hole 18 are all etched and filled with metal in the same process flow. The second contact hole 16 is mainly for leading out the gate, while the third contact hole 17 and the fourth contact hole 18 are mainly for leading out the source.
[0067] Step S13: A second injection area 19 is formed at the bottom of the second contact hole 16, the third contact hole 17 and the fourth contact hole 18;
[0068] It should be noted that, as Figure 11 As shown, a second implantation region 19 is formed by high-dose ion implantation, which achieves high-concentration doping in the regions of the second contact hole 16, the third contact hole 17, and the fourth contact hole 18. This allows the metal in the second contact hole 16 to form ohmic contacts with the third polysilicon 10, the metal in the third contact hole 17 to form the well region 12, and the metal in the fourth contact hole 18 to form the first polysilicon 6. This reduces contact resistance and ensures the electrical reliability of the device.
[0069] Step S14, as follows Figure 12 As shown, the second contact hole 16, the third contact hole 17 and the fourth contact hole 18 are filled with a first metal, a second metal 20 is deposited on the first metal, a third metal 24 is deposited on the second metal 20, and the first electrode and the second electrode are brought out after exposure etching.
[0070] Step S15, as follows Figure 12 As shown, the first metal layer 20 is etched to form a plurality of isolation trenches 21 to separate the first electrode and the second electrode; the first electrode forms the positive electrode of the temperature detection pin, and the second electrode is connected to the source or emitter of the chip.
[0071] Step S16, as follows Figure 12 As shown, a fourth metal layer 22 is formed on the lower surface of the epitaxial layer 1 to bring out the drain electrode. It should be noted that a substrate 23 is also disposed on the lower surface of the epitaxial layer 1.
[0072] Secondly, such as Figure 13 As shown, this application provides a layout, which is prepared according to the process described in any of the first aspects;
[0073] The map includes: a first trench region 25;
[0074] The first trench area 25 is provided with a first contact hole area 26;
[0075] The first trench in the first trench region 25 is filled with first polysilicon and second polysilicon from bottom to top;
[0076] The first contact hole region 26 is used to fill the first metal, and the first metal forms a Schottky junction with the second polysilicon of the first trench region 25; the first contact hole region 26 is connected to the Schottky positive lead-out region 29 to lead out the positive electrode of the Schottky diode;
[0077] A source lead-out region or an emitter lead-out region 30 is provided outside the active region 28 of the chip to lead out the source or emitter. The source or emitter of the chip also serves as the negative electrode of the Schottky diode. The source lead-out region or emitter lead-out region 30 is connected to the first polysilicon 27.
[0078] The Schottky positive electrode lead-out region 29 and the source electrode lead-out region 30 or emitter lead-out region are both located in the region above the first trench region 25.
[0079] It should be noted that, Figure 13 The layout shown only describes the layout design related to the Schottky diode structure; the layout design related to the source and gate has been omitted.
[0080] like Figure 14 As shown, Figure 14 The diagram shows the gate and source related structures, with the gate lead-out region 31 connected to the gate metal in the second contact hole 33. Additionally, in... Figure 13 and Figure 13 The active region 28 of the wafer also has a third contact hole region 32, which is also for bringing out the source electrode. The fourth contact hole region corresponding to the fourth contact hole in the above process is not shown.
[0081] Compared with existing technologies, this application provides a power chip fabrication process and layout with cell temperature detection functionality. A Schottky diode is formed by direct contact between Schottky metal and a second polysilicon with a lower doping concentration. When current flows through the active region of the device, heat is generated. The lattice conducts this heat to the Schottky junction within the first trench, causing a change in the barrier height of the Schottky diode and thus altering its forward voltage drop. The real-time temperature inside the active region of the device during operation can be calculated. The trench oxide layer acts as an isolation layer for temperature detection, ensuring that the overall and local junction temperature detection is unaffected by the switching power supply circuit.
[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A fabrication process for a power chip with cellular temperature detection function, characterized in that, The process includes fabricating a polycrystalline silicon Schottky diode within a first trench of the chip, the process comprising: A first trench is formed by etching the upper surface of the epitaxial layer, and a first oxide layer is grown on the sidewall of the first trench; The first trench is filled with a first polycrystalline silicon. The excess first polysilicon on the upper surface of the epitaxial layer is removed by etching, and the first polysilicon in the first trench is etched until the remaining portion of the first polysilicon in the first trench is removed. The first trench is filled with a second polycrystalline silicon. A second oxide layer is deposited on the upper surface of the epitaxial layer; A first contact hole is formed in the first trench, the first contact hole penetrating the second oxide layer and extending into the second polysilicon; The first contact hole is filled with the first metal; A second metal is deposited on top of the first metal, and a third metal is deposited on top of the second metal. After exposure and etching, the first and second electrodes are brought out.
2. The power chip fabrication process with cell temperature detection function as described in claim 1, characterized in that, The first oxide layer on the sidewall of the first trench is prepared using the same process as the second oxide layer on the sidewall of the other trenches in the active region of the chip.
3. The power chip fabrication process with cell temperature detection function as described in claim 1, characterized in that, The doping concentration of the second polysilicon in the first trench is less than the doping concentration of the first polysilicon.
4. The power chip fabrication process with cell temperature detection function as described in claim 1, characterized in that, The first electrode forms the positive terminal of the temperature detection pin, and the second electrode is connected to the source or emitter of the chip. The source or emitter of the chip also serves as the negative terminal of the temperature detection pin.
5. The power chip fabrication process with cell temperature detection function as described in claim 1, characterized in that, The polycrystalline silicon Schottky diode structural units are spaced apart in the active region of the chip.
6. A layout, characterized in that, The process according to any one of claims 1 to 5 is used to prepare the layout; The map includes: a first trench region; The first trench area is provided with a first contact hole area; The first trench in the first trench region is filled with first polysilicon and second polysilicon sequentially from bottom to top; The first contact hole region is used to fill the first metal, and the first metal forms a Schottky junction with the second polysilicon in the first trench region; the first contact hole region is connected to the Schottky lead-out region to lead out the positive electrode of the polysilicon Schottky diode; A source lead-out region or an emitter lead-out region is provided outside the active region of the chip to lead out the source or emitter. The source or emitter of the chip also serves as the negative electrode of the polysilicon Schottky diode. The source lead-out region is connected to the first polysilicon. The Schottky cathode lead-out region and the source lead-out region or emitter lead-out region are both located in the region above the first trench region.