Electrostatic discharge protection structure, method for forming electrostatic discharge protection structure and photomask
By forming a photoresist layer region with gradient ion distribution on the drain of the MOS transistor, the problem of turn-on uniformity of the GGNMOS structure is solved, and the electrostatic discharge protection capability is improved.
Patent Information
- Application Number
- CN202511107335.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-07
- Publication Date
- 2025-11-14
AI Technical Summary
In the prior art, the multi-finger structure of GGNMOS causes problems with the uniformity of the electrostatic discharge protection structure, affecting its ESD protection effect.
By forming photoresist layers of different thicknesses on the drain of a MOS transistor, performing ESD ion implantation, the ion concentration in the first region is greater than that in the second region, the ion concentration in the second region is greater than that in the third region, and then performing an annealing process to form a gradient ion distribution.
Without changing the process flow or increasing costs, the opening uniformity of the electrostatic discharge protection structure was improved, thus enhancing the electrostatic discharge protection capability.
Smart Images
Figure CN120957482A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to an electrostatic discharge protection structure, a method for forming an electrostatic discharge protection structure, and a photomask. Background Technology
[0002] ESD (Electrostatic Discharge) is a phenomenon where charge transfer occurs instantaneously upon contact between two objects at different potentials, resulting in a transient high-current pulse. For integrated circuits (ICs), ESD can damage relatively fragile components, causing functional failure or reliability degradation. As the feature size of ICs continues to shrink, the harm caused by ESD becomes increasingly significant, making ESD protection solutions increasingly challenging in the design and manufacturing of IC products.
[0003] In chip design related to this technology, due to its advantages such as simple structure, low on-resistance, and complete compatibility with MOS process, the gate-grounded N-type field-effect transistor (GGNMOS) protection structure is often used as an ESD protection device.
[0004] However, in order to increase the robustness of GGNMOS, related technologies have adopted a multi-finger structure. The multi-finger structure has brought about the problem of GGNMOS turn-on uniformity. Therefore, how to solve the above-mentioned turn-on uniformity problem conveniently and at low cost is the key. Summary of the Invention
[0005] To solve the above-mentioned technical problems, the present invention provides a method for forming an electrostatic discharge protection structure, comprising:
[0006] A substrate is provided, on which a pickup region and a plurality of MOS transistors are formed, each of the MOS transistors including a gate disposed on the surface of the substrate, a source and a drain disposed in the substrate on both sides of the gate;
[0007] A patterned photoresist layer is formed on the surface of the substrate. The drain includes a first region, a second region, and a third region that are sequentially located away from the pickup region. The thickness of the photoresist layer on the third region is greater than the thickness of the photoresist layer on the second region, and the thickness of the photoresist layer on the second region is greater than the thickness of the photoresist layer on the first region.
[0008] Perform ESD ion implantation such that the ion concentration implanted in the first region is greater than the ion concentration implanted in the second region, and the ion concentration implanted in the second region is greater than the ion concentration implanted in the third region, wherein the conductivity type of the ESD ion implanted is opposite to the conductivity type of the drain electrode;
[0009] Remove the patterned photoresist layer and perform an annealing process.
[0010] Optionally, the plurality of MOS transistors are arranged in a multi-finger structure, extending along a first direction and arranged along a second direction, the second direction being orthogonal to the first direction, and the pickup area surrounds the plurality of NMOS transistors.
[0011] Optionally, the drain includes a third region located in the middle, two first regions located at both ends, and two second regions located between the first region and the third region.
[0012] Optionally, the thickness of the photoresist layer in the third region is the maximum thickness of the patterned photoresist layer. The patterned photoresist layer forms a third opening in the first region to expose the drain surface. The patterned photoresist layer forms a fourth opening in the second region, and a portion of the photoresist layer thickness is retained within the fourth opening.
[0013] Optionally, during the photolithography process of forming the patterned photoresist layer, the exposure received by the first region is greater than that received by the second region, and the exposure received by the third region is 0.
[0014] Optionally, the width of the third opening and / or the fourth opening is less than or equal to the width of the drain electrode.
[0015] Optionally, the electrostatic discharge protection structure includes a GGNMOS structure, and the ions used to perform the ESD ion implantation include P-type ions.
[0016] According to another aspect of the present invention, a photomask is also provided for forming the electrostatic discharge protection structure as described above. The photomask includes a mask pattern having a first opening and a second opening. The first opening corresponds to a first region of the drain of a MOS transistor, and the second opening corresponds to a second region of the drain of a MOS transistor. The transmittance of the first opening is greater than the transmittance of the second opening.
[0017] Optionally, the mask pattern includes an opaque layer and a semi-transparent layer, both of which expose the first opening, the opaque layer exposes the second opening, and the semi-transparent layer covers the second opening.
[0018] According to another aspect of the present invention, an electrostatic discharge protection structure is also provided, which is formed by the method described above.
[0019] In summary, this application provides an electrostatic discharge (ESD) protection structure, a method for forming an ESD protection structure, and a photomask. The method includes: providing a substrate; forming a pickup region and a plurality of MOS transistors on the substrate, each MOS transistor including a gate on the substrate surface, a source and a drain on both sides of the gate in the substrate; forming a patterned photoresist layer on the substrate surface, the drain including a first region, a second region and a third region sequentially away from the pickup region, the thickness of the photoresist layer on the third region being greater than the thickness of the photoresist layer on the second region, and the thickness of the photoresist layer on the second region being greater than the thickness of the photoresist layer on the first region; performing ESD ion implantation, such that the ion concentration implanted in the first region is greater than the ion concentration implanted in the second region, and the ion concentration implanted in the second region is greater than the ion concentration implanted in the third region, wherein the conductivity type of the ESD ion implanted is opposite to the conductivity type of the drain; removing the patterned photoresist layer and performing an annealing process. In this application, by making the thickness of the photoresist layer on the third region greater than the thickness of the photoresist layer on the second region, and the thickness of the photoresist layer on the second region greater than the thickness of the photoresist layer on the first region, the ion concentration in the first region after ESD ion implantation is greater than the ion concentration implanted in the second region, and the ion concentration implanted in the second region is greater than the ion concentration implanted in the third region. This improves the uniformity of electrostatic discharge activation of the electrostatic discharge protection structure without changing the process flow or incurring additional costs, thereby enhancing the electrostatic discharge protection capability. Attached Figure Description
[0020] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.
[0021] Figure 1 A flowchart of a method for forming an electrostatic discharge protection structure provided in an embodiment of this application;
[0022] Figures 2A_1 to 2D_2 are schematic diagrams of the corresponding steps of the method for forming an electrostatic discharge protection structure provided in the embodiments of this application;
[0023] Figure 3 This is a schematic diagram of the structure of the photomask provided in an embodiment of this application.
[0024] In the attached figures: 10-substrate; 11-P-type well region; 12-pickup region; 13-isolation structure; 20-MOS transistor; 21-drain; 22-source; 23-gate; 24-photoresist layer; D1-first region; D2-second region; D3-third region; 26-third opening; 27-fourth opening; X-first direction; Y-second direction; 28a-first ESD doped region; 28b-second ESD doped region; 31-first opening; 32-second opening; 33-opaque layer; 34-semi-transparent layer. Detailed Implementation
[0025] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0026] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.
[0027] This application provides a method for forming an electrostatic discharge protection structure.
[0028] Figure 1 A flowchart illustrating a method for forming an electrostatic discharge protection structure provided in an embodiment of this application.
[0029] like Figure 1 As shown, the method for forming an electrostatic discharge protection structure provided in this embodiment includes:
[0030] S01: Provide a substrate, on which a pickup region and a plurality of MOS transistors are formed, each of the MOS transistors including a gate disposed on the surface of the substrate, a source and a drain disposed in the substrate on both sides of the gate;
[0031] S02: A patterned photoresist layer is formed on the surface of the substrate. The drain includes a first region, a second region, and a third region that are sequentially away from the pickup region. The thickness of the photoresist layer on the third region is greater than the thickness of the photoresist layer on the second region, and the thickness of the photoresist layer on the second region is greater than the thickness of the photoresist layer on the first region.
[0032] S03: Perform ESD ion implantation, such that the ion concentration implanted in the first region is greater than the ion concentration implanted in the second region, and the ion concentration implanted in the second region is greater than the ion concentration implanted in the third region, wherein the conductivity type of the ESD ion implanted is opposite to the conductivity type of the drain electrode.
[0033] S04: Remove the patterned photoresist layer and perform an annealing process.
[0034] Figures 2A_1 to 2D_2 are schematic diagrams of the corresponding steps of the method for forming an electrostatic discharge protection structure provided in the embodiments of this application. The method for forming an electrostatic discharge protection structure provided in this embodiment will be described in detail below with reference to Figures 2A_1 to 2D_2.
[0035] First, perform step S01. Referring to Figures 2A_1 and 2A_2, a substrate 10 is provided. A pickup region 12 and a plurality of MOS transistors 20 are formed on the substrate 10. Each MOS transistor 20 includes a gate 23 disposed on the surface of the substrate 10, a source 22 disposed on both sides of the gate 23 in the substrate 10, and a drain 21.
[0036] In some examples, the electrostatic discharge protection structure to be formed in this application may be a GGNMOS structure, and the MOS transistor 20 on the substrate 10 may be an NMOS transistor 20. The substrate 10 may be at least one of the following materials: silicon, germanium, silicon germanium, silicon-on-insulator, silicon germanium-on-insulator, and germanium-on-insulator. Figure 2A_1 is a top view of the pickup area and NMOS transistor provided in the embodiment of this application, and Figure 2A_2 is a cross-sectional view of the pickup area 12 and NMOS transistor 20 provided in the embodiment of this application along the first direction X. As shown in Figures 2A_1 and 2A_2, the conductivity type of the substrate 10 may be P-type, and a P-type well region 11 is provided on the surface of the substrate 10. The pickup area 12 and several MOS transistors 20 included in the electrostatic discharge protection structure are all disposed in or on the P-type well region 11. The aforementioned plurality of NMOS transistors 20 may be arranged along the second direction Y and connected in parallel with each other. Each NMOS transistor 20 extends along the first direction X. The first direction X and the second direction Y are orthogonal on the surface of the substrate 10. Each NMOS transistor 20 may include a gate 23, a source 22 and a drain 21 disposed along the first direction X. The gate 23 is disposed on the surface of the P-type well region 11. The source 22 and the drain 21 are disposed in the P-type well regions 11 on both sides of the gate 23. The source 22 and the drain 21 are both N-type doped regions. The gate 23 of the aforementioned plurality of NMOS transistors 20 may also be connected to one end to form an interdigitated shape and led out from that end. The drain 21 of the aforementioned plurality of NMOS transistors 20 may also be connected to the other end to form an interdigitated shape and led out from that end.
[0037] In the examples shown in Figures 2A_1 and 2A_2, the pickup region 12 can be a continuous and closed ring, such as a P-type doped region surrounding the source 22 and drain 21 of the plurality of NMOS transistors 20. An isolation structure 13, such as a shallow trench isolation structure, can be provided between the pickup region 12 and the source 22 and drain 21 of the plurality of NMOS transistors 20.
[0038] In other examples of this application, depending on actual needs, the pickup area 12 located around the NMOS transistor 20 may also be a discontinuous closed ring or an unclosed semi-ring.
[0039] Next, referring to Figures 2B_1 and 2B_2, step S02 is performed to form a patterned photoresist layer 24 on the surface of the substrate 10. The drain 21 includes a first region D1, a second region D2, and a third region D3 that are sequentially located away from the pickup region 12. The thickness of the photoresist layer 24 on the third region D3 is greater than the thickness of the photoresist layer 24 on the second region D2, and the thickness of the photoresist layer 24 on the second region D2 is greater than the thickness of the photoresist layer 24 on the first region D1.
[0040] In some examples, before forming the patterned photoresist layer 24, the surface of the drain 21 may also be covered with an oxide layer as an ion implantation protection layer. In other examples, before forming the patterned photoresist layer 24, an ion protection implantation layer (e.g., an oxide layer) is formed to conformally cover the surface of the substrate 10 and the outer wall of the gate 23 structure.
[0041] Figure 2B_1 is a top view of the pickup area and NMOS transistor provided in the embodiment of this application, and Figure 2B_2 is a cross-sectional view of the pickup area and NMOS transistor provided in the embodiment of this application along a diagonal direction. As shown in Figures 2B_1 and 2B_2, the drain 21 of each of the above-mentioned NMOS transistors 20 has a first region D1, a second region D2, and a third region D3 along the first direction X (extending direction). The third region D3 is located at the middle position of the drain 21 along the first direction X, the first region D1 is located at the edge position of the drain 21 on both sides along the first direction X, the second region D2 is located between the first region D1 and the third region D3 and is connected to the first region D1 and the third region D3, and the pickup area 12 is located on both sides of the drain 21 along the first direction X. A drain 21 may include a third region D3 located in the middle, two first regions D1 located at both ends, and two second regions D2 located between the first region D1 and the third region D3. The above five regions may each occupy about 1 / 5 of the surface of the drain 21. In this context, the thickness of the photoresist layer 24 on the third region D3 is the maximum thickness of the patterned photoresist layer 24, meaning that the thickness of the photoresist layer 24 on the third region D3 is the same as the thickness of the photoresist layer 24 in other non-photolithographic regions. The patterned photoresist layer 24 forms a third opening 26 on the first region D1 to expose the surface of the drain electrode 21, meaning that the thickness of the photoresist layer 24 on the first region D1 is 0. The patterned photoresist layer 24 forms a fourth opening 27 on the second region D2, and a portion of the photoresist layer 24 is retained within the fourth opening 27. The thickness of the photoresist layer 24 within the fourth opening 27 is negatively correlated with the ion concentration of the subsequent ESD ion implantation in the second region D2.
[0042] In some examples, the cross-sectional shapes of the third opening 26 and the fourth opening 27 are the same as those of the first region D1 and the second region D2, respectively. That is, the width of the third opening 26 is the same as the width of the first region D1, and the width of the fourth opening 27 is the same as the width of the second region D2. The cross-sectional shapes of both the third opening 26 and the fourth opening 27 are rectangular. In another example, the cross-sectional shapes of the third opening 26 and the fourth opening 27 are different from those of the first region D1 and the second region D2. In other words, the width of the third opening 26 and / or the fourth opening 27 is less than or equal to the width of the corresponding first region D1 and second region D2. For example, the cross-sectional shape of the third opening 26 and / or the fourth opening 27 is trapezoidal, and the width of the trapezoid near the pickup area 12 is greater than the width away from the pickup area 12.
[0043] In one example, when a patterned photoresist layer 24 is formed on a substrate 10 using a photomask, the light transmittance of the region corresponding to the third opening 26 on the photomask is greater than that of the region corresponding to the fourth opening 27, and the region corresponding to the third region D3 on the photomask is opaque. This makes the exposure received by the first region D1 greater than that received by the second region D2, and the exposure received by the third region D3 zero. As a result, after photolithography (exposure and development), the thickness of the photoresist layer 24 on the third region D3 is greater than the thickness of the photoresist layer 24 on the second region D2, and the thickness of the photoresist layer 24 on the second region D2 is greater than the thickness of the photoresist layer 24 on the first region D1.
[0044] Next, please refer to Figure 2C Execute step S03 to perform ESD ion implantation, so that the ion concentration implanted in the first region D1 is greater than the ion concentration implanted in the second region D2, and the ion concentration implanted in the second region D2 is greater than the ion concentration implanted in the third region D3.
[0045] In some examples, the electrostatic discharge protection structure to be formed includes a GGNMOS structure, that is, the MOS transistor 20 on the substrate 10 is an NMOS transistor 20, the drain 21 in the substrate 10 can be an N-type region, and the ions for ESD ion implantation include P-type ions, such as boron ions, boron difluoride or boron trifluoride. Since the thickness of the photoresist layer 24 on the third region D3 is the maximum thickness, the concentration of P-type ions implanted in the third region D3 can be 0 or close to 0. The thickness of the photoresist layer 24 on the second region D2 is greater than the thickness of the photoresist layer 24 on the first region D1, which can make the concentration of P-type ions implanted in the second region D2 (second ESD doped region 28b) less than the ion concentration of P-type ions implanted in the first region D1 (first ESD doped region 28a).
[0046] Next, referring to Figures 2D_1 and 2D_2, perform step S04 to remove the patterned photoresist layer 24 and perform an annealing process.
[0047] Figure 2D_1 is a top view of the pickup area and NMOS transistor provided in the embodiment of this application, and Figure 2D_2 is a cross-sectional view of the pickup area and NMOS transistor provided in the embodiment of this application along the diagonal direction.
[0048] As shown in Figures 2D_1 and 2D_2, after removing the patterned photoresist layer 24, laser annealing can be used, for example, to activate the ESD ion implanted ions and reduce ion diffusion, thereby forming an electrostatic discharge protection structure (e.g., a GGNMOS structure) with a breakdown voltage gradient or approximately gradient distribution. The region near the pickup region 12 (first region D1) has the highest ion concentration during ESD ion implantation, resulting in a lower (lowest) breakdown voltage. The region far from the pickup region 12 (third region D3) has the lowest ion concentration during ESD ion implantation, resulting in a higher breakdown voltage. The region between the two (second region D2) has an ion concentration between the two during ESD ion implantation, resulting in a breakdown voltage between the two. Thus, without changing the process flow or incurring additional costs, the uniformity of electrostatic discharge activation of the electrostatic discharge protection structure can be improved, thereby enhancing the electrostatic discharge protection capability.
[0049] This application also provides a photomask.
[0050] Figure 3 This is a schematic diagram of the structure of the photomask provided in an embodiment of this application.
[0051] This application provides a photomask for forming an electrostatic discharge protection structure, i.e., forming a patterned photoresist layer for ESD ion implantation. For example... Figure 3 As shown, the photomask includes a light-transmitting substrate and a mask pattern disposed on the substrate. The mask pattern has a first opening 31 and a second opening 32. The first opening 31 corresponds to the first region D1 of the drain of the MOS transistor (i.e., corresponds to the third opening 26 of the patterned photoresist layer 24 in the aforementioned embodiment), and the second opening 32 corresponds to the second region D2 of the drain 21 of the MOS transistor 20 (i.e., corresponds to the fourth opening 27 of the patterned photoresist layer 24 in the aforementioned embodiment). The light transmittance of the first opening 31 is greater than that of the second opening 32.
[0052] In some examples, the mask pattern may include an opaque layer 33 and a semi-transparent layer 34, both of which expose the first opening 31. The opaque layer 33 exposes the second opening 32 and the semi-transparent layer 34 covers the second opening 32. At least the opaque layer 33 covers the third region D3 corresponding to the drain 21. In other words, the first opening 31 is not covered by the opaque layer 33 and the semi-transparent layer 34, the second opening 32 is only covered by the semi-transparent layer 34, and the third region D3 of the drain 21 and other non-photolithographic regions are at least covered by the opaque layer 33. The steps for forming the above-mentioned mask pattern may include, for example, the following: First, forming an opaque layer 33 to cover the surface of the substrate; then, patterning the opaque layer 33 to form a first opening 31 and a second opening 32 in the opaque layer 33 to expose the substrate surface; the opaque layer 33 covers the area corresponding to the third region D3 of the drain 21 and other non-photolithographic areas; next, forming a semi-transparent layer 34 to cover the opaque layer 33, the surface of the first opening 31 and the second opening 32; then, patterning the semi-transparent layer 34 to remove the semi-transparent layer 34 on the first opening 31 to expose the substrate surface inside the first opening 31, and retaining the semi-transparent layer 34 on the surface of the second opening 32. Of course, it is feasible to retain, partially retain or not retain the semi-transparent layer 34 on the surface of the area corresponding to the third region D3 of the drain 21 and other non-photolithographic areas.
[0053] This application also provides an electrostatic discharge protection structure.
[0054] Figure 2D_1 is a top view of the pickup area and NMOS transistor of the electrostatic discharge protection structure provided in the embodiment of this application, and Figure 2D_2 is a cross-sectional view of the pickup area and NMOS transistor of the electrostatic discharge protection structure provided in the embodiment of this application along the diagonal direction.
[0055] As shown in Figures 2D_1 and 2D_2, the electrostatic discharge protection structure provided in this embodiment can be a GGNMOS structure, which may include a substrate 10, a P-type well region 11, a pickup region 12, and a plurality of NMOS transistors 20. The P-type well region 11 is located in the substrate 10, and the pickup region 12 and the plurality of NMOS transistors 20 are disposed in the P-type well region 11. The plurality of NMOS transistors 20 may be arranged along the second direction Y and connected in parallel with each other. Each NMOS transistor 20 extends along the first direction X. The first direction X and the second direction Y are orthogonal on the surface of the substrate 10. Each NMOS transistor 20 may include a gate 23, a source 22, and a drain 21 disposed along the first direction X. The gate 23 is disposed on the surface of the P-type well region 11, and the source 22 and drain 21 are disposed in the P-type well regions 11 on both sides of the gate 23. Both the source 22 and the drain 21 are N-type doped regions.
[0056] The pickup region 12 can be a continuous and closed ring, such as a P-type doped region surrounding the source 22 and drain 21 of the plurality of NMOS transistors 20. An isolation structure 13, such as a shallow trench isolation structure, can be provided between the pickup region 12 and the source 22 and drain 21 of the plurality of NMOS transistors 20.
[0057] The drain 21 of each of the above-mentioned NMOS transistors has a first region D1, a second region D2, and a third region D3 along the first direction X (extending direction). The third region D3 is located at the middle position of the drain 21 along the first direction X. The first region D1 is located at the edge positions of the drain 21 on both sides along the first direction X. The second region D2 is located between the first region D1 and the third region D3 and is connected to the first region D1 and the third region D3. The pickup region 12 is located on both sides of the drain 21 along the first direction X. A drain 21 may include a third region D3 located in the middle, two first regions D1 located at both ends, and two second regions D2 located between the first region D1 and the third region D3. Among them, the bottom of the drain 21 of the first region D1 is provided with a P-type first ESD doped region 28a, the bottom of the drain 21 of the second region D2 is provided with a P-type second ESD doped region 28b, and the bottom of the drain 21 of the third region D3 is not provided with the above-mentioned P-type ESD doped region. Moreover, the doping concentration of the first ESD doped region 28a is greater than that of the second ESD doped region 28b.
[0058] In practical application of the above electrostatic discharge protection structure, the pickup area 12, gate 23 and source 22 are all grounded, while the drain 21 is connected to the protected circuit.
[0059] In summary, this application provides an electrostatic discharge (ESD) protection structure, a method for forming an ESD protection structure, and a photomask. The method includes: providing a substrate; forming a pickup region and a plurality of MOS transistors on the substrate, each MOS transistor including a gate on the substrate surface, a source and a drain on both sides of the gate in the substrate; forming a patterned photoresist layer on the substrate surface, the drain including a first region, a second region and a third region sequentially away from the pickup region, the thickness of the photoresist layer on the third region being greater than the thickness of the photoresist layer on the second region, and the thickness of the photoresist layer on the second region being greater than the thickness of the photoresist layer on the first region; performing ESD ion implantation, such that the ion concentration implanted in the first region is greater than the ion concentration implanted in the second region, and the ion concentration implanted in the second region is greater than the ion concentration implanted in the third region, wherein the conductivity type of the ESD ion implanted is opposite to the conductivity type of the drain; removing the patterned photoresist layer and performing an annealing process. In this application, by making the thickness of the photoresist layer on the third region greater than the thickness of the photoresist layer on the second region, and the thickness of the photoresist layer on the second region greater than the thickness of the photoresist layer on the first region, the ion concentration in the first region after ESD ion implantation is greater than the ion concentration implanted in the second region, and the ion concentration implanted in the second region is greater than the ion concentration implanted in the third region. This improves the uniformity of electrostatic discharge activation of the electrostatic discharge protection structure without changing the process flow or incurring additional costs, thereby enhancing the electrostatic discharge protection capability.
[0060] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for forming an electrostatic discharge protection structure, characterized in that, include: A substrate is provided, on which a pickup region and a plurality of MOS transistors are formed, each of the MOS transistors including a gate disposed on the surface of the substrate, a source and a drain disposed in the substrate on both sides of the gate; A patterned photoresist layer is formed on the surface of the substrate. The drain includes a first region, a second region, and a third region that are sequentially located away from the pickup region. The thickness of the photoresist layer on the third region is greater than the thickness of the photoresist layer on the second region, and the thickness of the photoresist layer on the second region is greater than the thickness of the photoresist layer on the first region. Perform ESD ion implantation such that the ion concentration implanted in the first region is greater than the ion concentration implanted in the second region, and the ion concentration implanted in the second region is greater than the ion concentration implanted in the third region, wherein the conductivity type of the ESD ion implanted is opposite to the conductivity type of the drain electrode; Remove the patterned photoresist layer and perform an annealing process.
2. The method for forming an electrostatic discharge protection structure according to claim 1, characterized in that, The plurality of MOS transistors are arranged in a multi-finger structure, extending along a first direction and arranged along a second direction, the second direction being orthogonal to the first direction, and the pickup area surrounds the plurality of NMOS transistors.
3. The method for forming an electrostatic discharge protection structure according to claim 2, characterized in that, The drain includes a third region located in the middle, two first regions located at both ends, and two second regions located between the first region and the third region.
4. The method for forming an electrostatic discharge protection structure according to claim 1, characterized in that, The thickness of the photoresist layer in the third region is the maximum thickness of the patterned photoresist layer. The patterned photoresist layer forms a third opening in the first region to expose the drain surface. The patterned photoresist layer forms a fourth opening in the second region, and a portion of the photoresist layer thickness is retained within the fourth opening.
5. The method for forming an electrostatic discharge protection structure according to claim 4, characterized in that, During the formation of the patterned photoresist layer by photolithography, the first region receives more exposure than the second region, and the third region receives zero exposure.
6. The method for forming an electrostatic discharge protection structure according to claim 4, characterized in that, The width of the third opening and / or the fourth opening is less than or equal to the width of the drain electrode.
7. The method for forming an electrostatic discharge protection structure according to claim 1, characterized in that, The electrostatic discharge protection structure includes a GGNMOS structure, and the ions used for ESD ion implantation include P-type ions.
8. A photomask, characterized in that, For forming an electrostatic discharge protection structure as described in any one of claims 1 to 7, the photomask includes a mask pattern having a first opening and a second opening, the first opening corresponding to a first region of the drain of a MOS transistor, the second opening corresponding to a second region of the drain of a MOS transistor, and the transmittance of the first opening being greater than the transmittance of the second opening.
9. The photomask according to claim 8, characterized in that, The mask pattern includes an opaque layer and a semi-transparent layer, both of which expose the first opening. The opaque layer exposes the second opening, and the semi-transparent layer covers the second opening.
10. An electrostatic discharge protection structure, characterized in that, Formed using the method described in any one of claims 1 to 7.