Interlocking stop control circuit and water treatment system

Abstract

The invention relates to an interlocking stop control circuit and a water treatment system. The interlocking stop control circuit comprises a first control circuit which is used for acquiring a liquid storage parameter of a liquid storage module in the non-oxidizing bactericide metering device and outputting a first effective signal under the condition that the liquid storage parameter is lower than a preset liquid storage value; the second control circuit is used for acquiring the single-time continuous operation duration of a metering pump in the non-oxidizing bactericide metering device and outputting a second effective signal under the condition that the single-time continuous operation duration exceeds the preset duration; and the first OR gate circuit is respectively connected with the first control circuit, the second control circuit and a driving module in the non-oxidizing bactericide metering device, and is used for outputting an interlocking stop signal to the driving module under the condition of receiving the first effective signal or the second effective signal. The interlocking stop control circuit can automatically control the metering pump to be in an interlocking stop state.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of water treatment, in particular to an interlocking stop control circuit and a water treatment system. BACKGROUND

[0002] The pre-desalination system of a thermal power plant mainly includes an ultrafiltration system and a reverse osmosis system. The ultrafiltration system and the reverse osmosis system remove suspended solids, colloidal particles and dissolved salts in water through physical barriers and pressure differences, thereby providing high-quality make-up water to ensure the normal operation of boilers and other thermal equipment. The main functions of using non-oxidizing bactericides (dosing) in the reverse osmosis water treatment process include killing or inhibiting microorganisms in water, removing organic matter and part of inorganic pollutants, and improving water quality. Non-oxidizing bactericides can destroy the cell structure, metabolic process and genetic material of microorganisms through their strong oxidizing ability, thereby achieving the purpose of killing microorganisms.

[0003] Currently, power plants manually control the amount of non-oxidizing bactericides added. The amount of non-oxidizing bactericides is manually added by the operation personnel, and the dosing time is manually controlled. When the reverse osmosis system is controlled to be put into operation, the operation personnel manually judge whether to put the non-oxidizing bactericides into operation, and the operation time is also manually judged, which increases the cost of manual operation. SUMMARY

[0004] Therefore, it is necessary to provide an interlocking stop control circuit and a water treatment system.

[0005] In a first aspect, the present application provides an interlocking stop control circuit applied to a non-oxidizing bactericide metering device, the interlocking stop control circuit comprising:

[0006] a first control circuit configured to acquire a storage parameter of a storage module in the non-oxidizing bactericide metering device, and output a first effective signal when the storage parameter is lower than a preset storage value; the storage parameter is used to represent a storage amount of non-oxidizing bactericides stored in the storage module;

[0007] a second control circuit configured to acquire a single continuous operation time length of a metering pump in the non-oxidizing bactericide metering device, and output a second effective signal when the single continuous operation time length exceeds a preset time length; the metering pump is used to pump the non-oxidizing bactericides in the storage module into a reverse osmosis system;

[0008] a first OR gate circuit connected with the first control circuit, the second control circuit and a driving module in the non-oxidizing bactericide metering device, respectively, and configured to output an interlocking stop signal to the driving module when the first effective signal or the second effective signal is received; wherein the interlocking stop signal is used to control the driving module to drive the metering pump to be in an interlocking stop state.

[0009] In one of the embodiments, the second control circuit comprises:

[0010] a first trigger circuit, configured to receive a sequence control starting feedback signal sent by the reverse osmosis system, and output a first trigger signal in a case where a level state of the sequence control starting feedback signal is a preset first level state;

[0011] a second trigger circuit, configured to receive a first running signal sent by the metering pump, and output a second trigger signal in a case where a level state of the first running signal is a preset second level state;

[0012] a first AND gate circuit, connected with the first trigger circuit and the second trigger circuit respectively, configured to output a third trigger signal in a case where the first trigger signal is received and the second trigger signal is received;

[0013] a timing circuit, connected with the first AND gate circuit, configured to start timing in a case where the third trigger signal is received, and output the second effective signal in a case where a timing duration reaches the preset duration and a second running signal sent by the reverse osmosis system is received.

[0014] In one of the embodiments, the first trigger circuit comprises:

[0015] a plurality of first flip-flops, each of the first flip-flops is configured to receive a sequence control starting feedback signal sent by a reverse osmosis system, and output a first level signal in a case where a level state of the received sequence control starting feedback signal is the preset first level state;

[0016] a second OR gate circuit, connected with the plurality of first flip-flops respectively, configured to output the first trigger signal in a case where any of the first level signals is received.

[0017] In one of the embodiments, the second trigger circuit comprises:

[0018] a third OR gate circuit, configured to receive a plurality of running signals sent by the metering pump, and output the second trigger signal in a case where a level state of any of the running signals is the preset second level state.

[0019] In one of the embodiments, the timing circuit comprises:

[0020] a timer, configured to start timing in a case where the third trigger signal is received, and output a fourth trigger signal in a case where a timing duration reaches the preset duration;

[0021] a second flip-flop connected with the timer, configured to output a second level signal in the case of receiving the fourth trigger signal;

[0022] a fourth OR gate circuit configured to receive a plurality of operation signals sent by the reverse osmosis systems, and output a fifth trigger signal in the case of receiving an operation signal of any reverse osmosis system;

[0023] a second AND gate circuit connected with the second flip-flop and the fourth OR gate circuit respectively, configured to output a sixth trigger signal in the case of receiving the second level signal and the fifth trigger signal;

[0024] a first pulse generator connected with the second AND gate circuit and the first OR gate circuit respectively, configured to output the second valid signal in the case of receiving the sixth trigger signal.

[0025] In one of the embodiments, the timing circuit further comprises:

[0026] a reset unit connected with the timer and the second flip-flop respectively, configured to obtain a world time, and output a reset signal to the timer and the second flip-flop in the case of the world time being a preset time.

[0027] In one of the embodiments, the reset unit comprises:

[0028] a time module configured to obtain the world time;

[0029] a first comparator connected with the time module, configured to obtain an hour value in the world time, and output a third level signal in the case of the hour value being a first preset numerical value;

[0030] a second comparator connected with the time module, configured to obtain a minute value in the world time, and output a fourth level signal in the case of the minute value being a second preset numerical value;

[0031] a third comparator connected with the time module, configured to obtain a second value in the world time, and output a fifth level signal in the case of the second value being a third preset numerical value;

[0032] a third AND gate circuit connected with the first comparator, the second comparator and the third comparator respectively, configured to output a sixth trigger signal in the case of receiving the third level signal, the fourth level signal and the fifth level signal;

[0033] a second pulse generator connected with the third AND gate circuit, the timer and the second flip-flop respectively, configured to output the reset signal in the case of receiving the sixth trigger signal.

[0034] In one of the embodiments, the first control circuit comprises:

[0035] at least one liquid level comparator, configured to acquire a liquid storage parameter of the liquid storage module, and output the first effective signal when the liquid storage parameter is lower than a preset liquid storage value;

[0036] a time delay device, connected with the liquid level comparator and the first OR gate respectively, configured to perform time delay processing on the first effective signal, and output the time delay processed first effective signal to the first OR gate.

[0037] In one of the embodiments, the interlock stop control circuit further comprises:

[0038] a third pulse generator, connected with the first OR gate, configured to output a third effective signal when a running state of the reverse osmosis system does not meet a start condition of the metering pump;

[0039] the first OR gate is further configured to output the interlock stop signal to the driving module when the third effective signal is received.

[0040] In a second aspect, the present application further provides a water treatment system, comprising a non-oxidizing bactericide metering device and the interlock stop control circuit provided in any of the above embodiments.

[0041] In the above interlock stop control circuit and water treatment system, the first control circuit is configured to output the first effective signal when the liquid storage parameter is lower than the preset liquid storage value, the second control circuit is configured to output the second effective signal when the single continuous running time length of the metering pump exceeds the preset time length, and the first OR gate is configured to output the interlock stop signal to the driving module when the first effective signal or the second effective signal is received, so that the metering pump is automatically put into interlock stop when the non-oxidizing bactericide solution tank is in a low liquid level or the single continuous running time length of the metering pump exceeds the preset time length, and the labor cost is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0043] Figure 1 a schematic diagram of the interlock stop control circuit provided in an embodiment;

[0044] Figure 2 a schematic diagram of a second control circuit provided for an embodiment;

[0045] Figure 3 a schematic diagram of an interlock stop control circuit provided for another embodiment;

[0046] Figure 4 a schematic diagram of a reset unit provided for an embodiment.

[0047] BRIEF DESCRIPTION OF DRAWINGS

[0048] 100 - first control circuit, 110 - liquid level comparator, 120 - fourth AND gate circuit, 130 - delayer, 200 - second control circuit, 210 - first trigger circuit, 211 - first flip-flop, 212 - second OR gate circuit, 220 - second trigger circuit, 221 - third OR gate circuit, 230 - first AND gate circuit, 240 - timing circuit, 241, timer, 242 - second flip-flop, 243 - fourth OR gate circuit, 244 - second AND gate circuit, 245 - first pulse generator, 246 - reset unit, 2461 - first comparator, 2462 - second comparator, 2463 - third comparator, 2464 - third AND gate circuit, 2465 - second pulse generator, 300 - first OR gate circuit, 400 - third pulse generator. DETAILED DESCRIPTION

[0049] For the purposes of this application, reference will be made to the accompanying drawings in which embodiments of the application are shown. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0051] It is to be understood that the terms "first", "second", and the like, used herein do not connote any hierarchy or order. Such terms are used merely to distinguish one element from another. For example, a first OR gate circuit could be termed a second OR gate circuit, and similarly, a second OR gate circuit could be termed a first OR gate circuit, without departing from the scope of the application. The first OR gate circuit and the second OR gate circuit are both OR gate circuits, but they are not the same OR gate circuit.

[0052] It can be understood that "at least one" means one or more, and "multiple" means two or more. "At least part of the element" means part or all of the element.

[0053] As used herein, the singular forms "a", "an" and "the" can include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprise / comprising" or "have / having" or the like specifies the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in the specification includes any and all combinations of the related listed items.

[0054] In one embodiment, the present application provides an interlock stop control circuit which can be applied to a non-oxidizing biocide metering device. As shown in Figure 1 The interlock stop control circuit includes a first control circuit 100, a second control circuit 200 and a first OR gate circuit 300.

[0055] The first control circuit 100 is configured to obtain a storage parameter of a storage module in the non-oxidizing biocide metering device, and output a first valid signal when the storage parameter is lower than a preset storage value. The storage parameter is used to represent the storage amount of the non-oxidizing biocide in the storage module. For example, the storage module can be a solution tank in the non-oxidizing biocide metering device for storing the non-oxidizing biocide, and the storage parameter can be a liquid level value of the solution tank. The preset storage value can be a storage capacity corresponding to a liquid level of 0.5 meters of the solution tank, or can also be a liquid level value of 0.5 meters.

[0056] The second control circuit 200 is configured to obtain a single continuous running time of a metering pump in the non-oxidizing biocide metering device, and output a second valid signal when the single continuous running time exceeds a preset time. The metering pump is configured to pump the non-oxidizing biocide in the storage module into a reverse osmosis system. For example, the preset time can be 30 minutes.

[0057] The first OR gate circuit 300 is connected with the first control circuit 100, the second control circuit 200 and a driving module in the non-oxidizing biocide metering device, respectively. The first OR gate circuit 300 is configured to output an interlock stop signal to the driving module when receiving the first valid signal or the second valid signal. The interlock stop signal is used to control the driving module to drive the metering pump to be in an interlock stop state.

[0058] In the embodiment of the present application, by setting the first control circuit 100 to output the first effective signal when the liquid storage parameter is lower than the preset liquid storage value, setting the second control circuit 200 to output the second effective signal when the single continuous running time length of the metering pump exceeds the preset time length, and setting the first OR gate circuit 300 to output the interlocking stop signal to the driving module when the first effective signal or the second effective signal is received, the metering pump is automatically put into interlocking stop when the non-oxidizing sterilizing agent solution tank is at a low liquid level or the single continuous running time length of the metering pump exceeds the preset time length, thereby reducing the labor cost.

[0059] In one embodiment, as shown in FIG. 2, the second control circuit 200 includes a first trigger circuit 210, a second trigger circuit 220, a first AND gate circuit 230, and a timing circuit 240. Figure 2

[0060] The first trigger circuit 210 is configured to receive a sequence control start feedback signal sent by the reverse osmosis system, and output a first trigger signal when the level state of the sequence control start feedback signal is a preset first level state. The sequence control start feedback signal in the preset first level state indicates that the reverse osmosis system starts the metering pump in a sequence control manner. Exemplarily, the preset first level state can be a high level state.

[0061] The second trigger circuit 220 is configured to receive a first running signal sent by the metering pump, and output a second trigger signal when the level state of the first running signal is a preset second level state. The first running signal in the preset second level state indicates that the metering pump is in a running state. Exemplarily, the preset second level state can be a high level state.

[0062] The first AND gate circuit 230 is connected with the first trigger circuit 210 and the second trigger circuit 220. The first AND gate circuit 230 is configured to output a third trigger signal when the first trigger signal is received and the second trigger signal is received.

[0063] The timing circuit 240 is connected with the first AND gate circuit 230, and is configured to start timing when the third trigger signal is received, and output the second effective signal when the timing time length reaches a preset time length and a second running signal sent by the reverse osmosis system is received.

[0064] In one embodiment, as shown in FIG. 2, the first trigger circuit 210 includes a plurality of first flip-flops 211 and a second OR gate circuit 212. Figure 3

[0065] ​​Each first trigger 211 is configured to receive a sequential start-up feedback signal sent by a reverse osmosis system, and output a first-level signal when the level of the received sequential start-up feedback signal is a preset first-level state. For example, the first-level signal can be a high-level signal.

[0066] The second OR gate circuit 212 is connected to a plurality of first flip-flops 211 respectively, and can be used to output a first trigger signal when any first level signal is received.

[0067] In one embodiment, the second trigger circuit 220 includes a third OR gate circuit 221. The third OR gate circuit 221 can be used to receive operating signals sent by multiple metering pumps, and output a second trigger signal when the level state of any operating signal is a preset second level state.

[0068] In one embodiment, such as Figure 3 As shown, the timing circuit 240 includes a timer 241, a second flip-flop 242, a fourth OR gate circuit 243, a second AND gate circuit 244, and a first pulse generator 245.

[0069] Timer 241 is used to start timing when a third trigger signal is received, and to output a fourth trigger signal when the timing duration reaches a preset duration.

[0070] The second flip-flop 242 is connected to the timer 241 and can be used to output a second-level signal upon receiving a fourth trigger signal. For example, the second-level signal can be a high-level signal.

[0071] The fourth OR gate circuit 243 can be used to receive operating signals sent by multiple reverse osmosis systems, and output a fifth trigger signal when an operating signal from any reverse osmosis system is received.

[0072] The second AND gate 244 is connected to the second flip-flop 242 and the fourth OR gate 243 respectively, and can be used to output a sixth trigger signal when a second level signal and a fifth trigger signal are received.

[0073] The first pulse generator 245 is connected to the second AND gate circuit 244 and the first OR gate circuit 300 respectively, and can be used to output a second valid signal when the sixth trigger signal is received.

[0074] In one embodiment, such as Figure 3As shown, the timing circuit 240 further comprises a reset unit 246. The reset unit 246 is connected with the timer 241 and the second flip-flop 242 respectively, and is configured to obtain a world time, and output a reset signal to the timer 241 and the second flip-flop 242 when the world time is a preset time. The world time can be obtained through a Beidou satellite communication. Exemplarily, the preset time can be zero o'clock. By setting the reset unit 246, the cumulative running time of the metering pump can be limited to the set time.

[0075] Further, as shown in FIG. 2, the reset unit 246 comprises a time module, a first comparator 2461, a second comparator 2462, a third comparator 2463, a third AND gate circuit 2464, and a second pulse generator 2465. Figure 4

[0076] The time module is configured to obtain the world time.

[0077] The first comparator 2461 is connected with the time module, and is configured to obtain an hour value in the world time, and output a third level signal when the hour value is a first preset value. Exemplarily, the first preset value can be zero, and the third level signal can be a high level signal.

[0078] The second comparator 2462 is connected with the time module, and is configured to obtain a minute value in the world time, and output a fourth level signal when the minute value is a second preset value. Exemplarily, the second preset value can be zero, and the fourth level signal can be a high level signal.

[0079] The third comparator 2463 is connected with the time module, and is configured to obtain a second value in the world time, and output a fifth level signal when the second value is a third preset value. Exemplarily, the third preset value can be zero, and the fifth level signal can be a high level signal.

[0080] The third AND gate circuit 2464 is connected with the first comparator 2461, the second comparator 2462, and the third comparator 2463 respectively, and is configured to output a sixth trigger signal when the third level signal, the fourth level signal, and the fifth level signal are received.

[0081] The second pulse generator 2465 is connected with the third AND gate circuit 2464, the timer 241, and the second flip-flop 242 respectively, and is configured to output the reset signal when the sixth trigger signal is received. The reset signal is configured to reset the timer 241 and the second flip-flop 242, so that the timer 241 stops timing and the second flip-flop 242 stops outputting the signal.

[0082] In one embodiment, as shown in FIG. 2, the reset unit 246 comprises a time module, a first comparator 2461, a second comparator 2462, a third comparator 2463, a third AND gate circuit 2464, and a second pulse generator 2465. Figure 3 ​As shown, the first control circuit 100 comprises at least one liquid level comparator 110 and a delay timer 130.

[0083] The liquid level comparator 110 can be configured to acquire a liquid storage parameter of the liquid storage module, and output a first valid signal when the liquid storage parameter is lower than a preset liquid storage value.

[0084] The delay timer 130 is connected with the liquid level comparator 110 and the first OR gate circuit 300 respectively, and can be configured to perform delay processing on the first valid signal and output the first valid signal after delay processing to the first OR gate circuit 300.

[0085] In one embodiment, as shown in FIG. 1, the first control circuit 100 comprises a plurality of liquid level comparators 110. Figure 3 As shown in FIG. 2, when the first control circuit 100 comprises a plurality of liquid level comparators 110, the first control circuit 100 further comprises a fourth AND gate circuit 120. The fourth AND gate circuit 120 is connected with the plurality of liquid level comparators 110 respectively, and is configured to output the first valid signal to the delay timer 130 when the outputs of the plurality of liquid level comparators 110 are all the first valid signal.

[0086] In one embodiment, as shown in FIG. 1, the first control circuit 100 comprises a plurality of liquid level comparators 110. Figure 3 As shown in FIG. 3, the interlock stop control circuit further comprises a third pulse generator 400. The third pulse generator 400 is connected with the first OR gate circuit 300, and is configured to output a third valid signal when the running state of the reverse osmosis system does not meet the start condition of the metering pump. The start condition of the metering pump can include that the reverse osmosis system is in operation, the water flow of the reverse osmosis system is normal, and the reverse osmosis system is not in a flushing state.

[0087] The first OR gate circuit 300 is further configured to output an interlock stop signal to the driving module when the third valid signal is received.

[0088] In one embodiment, the present application further provides a water treatment system comprising a non-oxidizing biocide metering device and the interlock stop control circuit provided in any of the above embodiments.

[0089] In one embodiment, the water treatment system further comprises a sequential start control circuit and a sequential stop control circuit. The sequential start control circuit can output a sequential start signal to the driving module to instruct the driving module to control the metering pump to start sequentially when the system meets the start condition of the metering pump. The sequential stop control circuit can output a sequential stop signal to the driving module to instruct the driving module to control the metering pump to stop sequentially when the reverse osmosis system is in a flushing state.

[0090] In the description of the specification, the description of the terms "some embodiments", "other embodiments", etc. means that the particular feature, structure, material, or characteristic being described is included in at least one embodiment or example of the application. The illustrative descriptions in this specification are not necessarily to be construed as indicating that all embodiments or examples of the application include the described feature, structure, material or characteristic.

[0091] The technical features of the above-described embodiments can be combined in any manner, and for brevity, not all possible combinations of the technical features in the above-described embodiments are described, but it should be considered that any combination of the technical features is within the scope of the present application as long as the combination does not result in a contradiction.

[0092] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the present application. It should be noted that for those skilled in the art, some modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. An interlock stop control circuit, characterized by comprising: The application is applied to a non-oxidizing sterilization agent metering device, and the interlock stop control circuit comprises: a first control circuit, configured to acquire a storage parameter of a storage module in the non-oxidizing sterilization agent metering device, and output a first effective signal when the storage parameter is lower than a preset storage value; the storage parameter is used to represent a storage amount of the non-oxidizing sterilization agent in the storage module; a second control circuit, configured to acquire a single continuous running time length of a metering pump in the non-oxidizing sterilization agent metering device, and output a second effective signal when the single continuous running time length exceeds a preset time length; the metering pump is used to pump the non-oxidizing sterilization agent in the storage module into a reverse osmosis system; a first OR gate circuit, connected with the first control circuit, the second control circuit and a driving module in the non-oxidizing sterilization agent metering device respectively, configured to output an interlock stop signal to the driving module when the first effective signal or the second effective signal is received; wherein the interlock stop signal is used to control the driving module to drive the metering pump to be in an interlock stop state.

2. An interlock stop control circuit according to claim 1, characterised in that, The second control circuit comprises: a first trigger circuit, configured to receive a sequence control start feedback signal sent by the reverse osmosis system, and output a first trigger signal when a level state of the sequence control start feedback signal is a preset first level state; a second trigger circuit, configured to receive a first running signal sent by the metering pump, and output a second trigger signal when a level state of the first running signal is a preset second level state; a first AND gate circuit, connected with the first trigger circuit and the second trigger circuit respectively, configured to output a third trigger signal when the first trigger signal is received and the second trigger signal is received; a timing circuit, connected with the first AND gate circuit, configured to start timing when the third trigger signal is received, and output the second effective signal when a timing time length reaches the preset time length and a second running signal sent by the reverse osmosis system is received.

3. An interlock stop control circuit according to claim 2, wherein, The first trigger circuit comprises: a plurality of first flip-flops, each of the first flip-flops is configured to receive a sequence control start feedback signal sent by the reverse osmosis system, and output a first level signal when a level state of the received sequence control start feedback signal is the preset first level state; a second OR gate circuit, connected with the plurality of first flip-flops respectively, configured to output the first trigger signal when any of the first level signals is received.

4. The interlock stop control circuit of claim 2, wherein, The second trigger circuit comprises: a third OR gate circuit, configured to receive a plurality of running signals sent by the metering pump, and output the second trigger signal when a level state of any of the running signals is the preset second level state.

5. The interlock stop control circuit of claim 2, wherein, The timing circuit comprises: a timer, configured to start timing when the third trigger signal is received, and output a fourth trigger signal when a timing time length reaches the preset time length. a second flip-flop connected with the timer, configured to output a second level signal in the case of receiving the fourth trigger signal; a fourth OR gate circuit configured to receive a plurality of operation signals sent by the reverse osmosis systems, and output a fifth trigger signal in the case of receiving any operation signal of the reverse osmosis systems; a second AND gate circuit connected with the second flip-flop and the fourth OR gate circuit respectively, configured to output a sixth trigger signal in the case of receiving the second level signal and the fifth trigger signal; a first pulse generator connected with the second AND gate circuit and the first OR gate circuit respectively, configured to output the second active signal in the case of receiving the sixth trigger signal.

6. An interlock stop control circuit according to claim 5, wherein, The timing circuit further comprises: a reset unit connected with the timer and the second flip-flop respectively, configured to obtain a world time, and output a reset signal to the timer and the second flip-flop in the case of the world time being a preset time.

7. An interlock stop control circuit according to claim 6, characterised in that, The reset unit comprises: a time module configured to obtain the world time; a first comparator connected with the time module, configured to obtain an hour value in the world time, and output a third level signal in the case of the hour value being a first preset numerical value; a second comparator connected with the time module, configured to obtain a minute value in the world time, and output a fourth level signal in the case of the minute value being a second preset numerical value; a third comparator connected with the time module, configured to obtain a second value in the world time, and output a fifth level signal in the case of the second value being a third preset numerical value; a third AND gate circuit connected with the first comparator, the second comparator and the third comparator respectively, configured to output a sixth trigger signal in the case of receiving the third level signal, the fourth level signal and the fifth level signal; a second pulse generator connected with the third AND gate circuit, the timer and the second flip-flop respectively, configured to output the reset signal in the case of receiving the sixth trigger signal.

8. An interlock stop control circuit according to any one of claims 1-7, characterized in that, The first control circuit comprises: at least one liquid level comparator configured to obtain a liquid storage parameter of the liquid storage module, and output the first active signal in the case of the liquid storage parameter being lower than a preset liquid storage value; a delay timer connected with the liquid level comparator and the first OR gate circuit respectively, configured to perform delay processing on the first active signal, and output the first active signal after delay processing to the first OR gate circuit.

9. An interlock stop control circuit according to any one of claims 1-7, characterized in that, The interlock stop control circuit further comprises: a third pulse generator connected with the first OR gate circuit, configured to output a third active signal in the case of the running state of the reverse osmosis system not satisfying the start condition of the metering pump; The first OR gate is further configured to output the interlock stop signal to the driving module in the case of receiving the third active signal.

10. A water treatment system characterized by, The interlock stop control circuit comprises a non-oxidizing bactericide metering device and the interlock stop control circuit according to any one of claims 1-9.

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