Compensation method and platform for adaptive reference clock of solid state disk

Abstract

The invention relates to the technical field of solid state disk testing, in particular to a compensation method and platform for a self-adaptive reference clock of a solid state disk. Comprising the following steps: S1, running a built-in application software calling script of the solid state disk, and performing PCIe configuration space detection in an initialization stage; s2, enabling an L1.2 function; s3, constructing a platform library, and obtaining host side parameters; s4, platform feature register detection is carried out; s5, calling the script by the application software, and responding to the SSD equipment to enter an L1.2 state; s6, starting a dynamic compensation process after acquiring the parameters of the host side; and S7, the compensation effectiveness is verified through low-power-consumption switching of the LTSSM state machine. Compared with the prior art, aiming at systematic faults caused by system clock recovery differences brought by different CPUs when the SSD is switched in the L1.2 low-power-consumption state, cross-platform time sequence compatibility is effectively improved through self-adaptive dynamic compensation by means of application software of the SSD.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solid state disk testing, in particular to a compensation method and platform for adaptive reference clock of a solid state disk. BACKGROUND

[0002] In a low-power state, turning off most modules in the link can make the PCIe terminal device, such as a solid state disk, consume almost no energy, which can greatly improve the endurance of mobile devices such as laptops.

[0003] With the continuous application of PCIe low-power technology, the differences in clock recovery mechanisms of different CPU manufacturers have led to increasingly significant system compatibility problems. There are significant differences in the clock recovery time of Intel, AMD, and domestic CPUs when exiting the L1.2 state. For example, the clock recovery time of a certain AMD processor is measured to be 14μs, which is much lower than the PCIe specification value of 150μs. This time difference causes the SSD device to receive the link training signal before completing the T_power_on initialization, thereby causing a series of system failures. These failures include: 1. The SSD PHY layer receives the link training signal before completing the voltage stabilization detection.

[0004] 2. The system misjudges the device trigger blue screen, such as clock watchdog timeout error.

[0005] 3. Data verification failure: due to timing problems, the data verification code is incorrect during data transmission.

[0006] It is found through measurement that there are significant differences in the clock recovery of mainstream CPU platforms: for example, AMD platform: Ryzen 5500U measured recovery time 14μs, which is 90.7% shorter than the specified value of 150μs. For example, Intel platform: Xeon 8480+ measured recovery time 32μs±5μs. For example, domestic platform: Feiteng S5000 series recovery time 80-120μs.

[0007] These differences make the existing firmware of SSD manufacturers unable to adapt to the timing characteristics of multiple platforms, highlighting some technical deficiencies. For example, firmware design defects: the existing SSD firmware only designs the delay according to the PCIe specification value, without fully considering the actual performance differences of different CPU manufacturers. For example, lack of state awareness: the SSD device cannot real-time sense the progress of CPU clock recovery, resulting in ineffective timing adjustment. SUMMARY

[0008] The application provides a solid state disk adaptive reference clock compensation method and platform to overcome the deficiencies of the prior art, based on the clock synchronization problem of a solid state disk device (SSD) in an L1.2 low power state with different CPU platforms under a PCIe link, and proposes a dynamic sensing and compensation scheme.

[0009] To achieve the above-mentioned purpose, a solid state disk adaptive reference clock compensation method is designed, including the following steps: S1, running a solid state disk self-contained application software calling script, performing PCIe configuration space detection in the initialization stage; S2, enabling L1.2 function; S3, constructing a platform library to obtain host parameters; S4, performing platform feature register detection; S5, application software calling script, responding to the SSD device entering the L1.2 state; S6, after obtaining the host parameters, starting the dynamic compensation process; S7, verifying the compensation effectiveness through the LTSSM state machine low power switching.

[0010] The specific method of step S1 is as follows: S11, locating the Capability chain table pointer: the script reads the device PCIe Capability pointer and locates to the Power Management Capability structure; S12, basic PM Capability detection: reading the PM Capability structure, confirming that the PMCSR register supports the L1.2 sub-state; S13, locating the extended PM Capability and obtaining the SSD end parameters: through the PCIe configuration space, the extended power management capability structure of Cap ID=0x1E is located, the T_POWERON_SCALE / VALUE field is analyzed, and the SSD device theoretical recovery time T_power_on is obtained, T_power_on is the theoretical time required for the SSD itself to recover to the normal state from the L1.2 state.

[0011] The specific method of step S2 is as follows: S21, ASPM low power strategy configuration: setting the ASPM field of the link control register to L0s+L1 enabled, and verifying that L1.2 is a sub-state support bit; setting the PCI-PM L1.2 Enable=1 in the PCI-PM control register, confirming that both devices support the L1.2 sub-state; S22, LTR threshold setting: configure the delay tolerance report register according to the theoretical recovery time T_power_on of SSD, set the maximum acceptable exit delay to match the T_power_on value.

[0012] The specific method of step S3 is as follows: S31, extract platform feature parameters by CPUID and PCH register: S32, generate a database by using the extracted data and store it in the application software provided with the solid state disk, and construct a low power consumption strategy library of the platform.

[0013] In step S31, the parameters include processor manufacturer code obtained by CPUID instruction, CPU microarchitecture version obtained by SMBIOS Type4 record, and L1.2 reference timing extracted from PCH register by configuration space access.

[0014] In step S4, the platform feature register of Intel platform is detected: the script reads the PM_CFG4 register of PCH to obtain the theoretical recovery time T_power_on value of the host end.

[0015] In step S4, the platform feature register of AMD platform is detected: the script reads the PM_CTRL register of FCH to obtain the theoretical recovery time T_power_on value of the host end.

[0016] The specific method of step S6 is as follows: S61, when the theoretical recovery time T_power_on or T_SSD_min of the host end changes, recalculate T_hold and update the register, and trigger the script to start the dynamic compensation process; S62, real-time parameter acquisition: S621, read the PCIe device PMCSR register to obtain the current power state; S622, obtain T_SSD_min through the PHY register; S623, extract the actual timing from the CPU feature register; S63: dynamic compensation calculation: S631, ensure that T_hold covers the worst case host end power recovery time T_power_on and SSD response delay T_SSD_min; S632, select the manufacturer's preset fault tolerance parameter β coefficient; S633, calculate the compensation value: T_hold =max( T_SSD_min, T_power_on× β+2μs). S64, register write, write the compensation value calculated in step S63 to the host PCIe controller and PHY registers: S641, modify the PCIe controller register; S642: synchronize the PHY timing update; Wherein T hold represents the hold time, covering the worst-case timing; T SSD_min represents the shortest time that the CLKREQ# signal must maintain stable when the SSD switches in the low-power state.

[0017] In step S7, it is confirmed whether the actual recovery time of the host reference clock is less than T hold. If the actual recovery time is less than T hold, the link is normal, and L1.2 exits the trigger; if the actual recovery time is greater than T hold, secondary compensation is triggered and the beta coefficient is updated, and L1.2 exit verification is performed again until the actual recovery time is less than T hold, the link is normal, and the test is exited.

[0018] To achieve the above object, a platform for a solid state disk adaptive reference clock compensation method is designed, comprising: A PC platform for providing a multi-platform adaptive solid state disk reference clock compensation method verification environment; A PC host platform processor for executing a computer program; A PC platform Linux operating system for managing and scheduling computer hardware and data resources; Application software for storing feature library data, providing customers with solid state disks, and serving as an entry for calling scripts; Test scripts for PCIe configuration space query; L1.2 function enablement; platform feature library establishment; platform feature judgment; control register pull-up / pull-down CLKREQ# signal sending; real-time parameter acquisition, dynamic compensation parameter writing; test result report; PC platform memory, providing an environment for the operation of the PC platform operating system and the test script; The solid state disk to be tested.

[0019] Compared with the prior art, the present application aims at the systematic failure caused by the difference in system clock recovery of different CPUs when the SSD switches in the L1.2 low-power state, and uses the SSD self-contained application software to realize effective improvement of cross-platform timing compatibility through adaptive dynamic compensation. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The flowchart of the present application. DETAILED DESCRIPTION

[0021] The present application will be further described below with reference to the accompanying drawings.

[0022] AsFigure 1 As shown, the compensation method of the solid state disk adaptive reference clock in the embodiment includes the following steps: S1, running the application software calling script of the solid state disk to detect the PCIe configuration space in the initialization stage; S2, enabling the L1.2 function; S3, constructing the platform library to obtain the host end parameter; S4, detecting the platform feature register; S5, the application software calling script responds to the SSD device entering the L1.2 state; S6, after obtaining the host end parameter, starting the dynamic compensation process; S7, verifying the compensation effectiveness through the low power switching of the LTSSM state machine.

[0023] The specific method of step S1 is as follows: S11, positioning the Capability chain table pointer: the script reads the PCIe Capability pointer of the device, and positions to the Power Management Capability structure through the pointer offset by 0x34; S12, basic PM Capability detection: reading the PM Capability structure, Cap ID=0x01, confirming that the PMCSR register supports the L1.2 substate; S13, positioning the extended PM Capability, Cap ID=0x1E, obtaining the SSD end parameter: positioning the extended power management capability structure of Cap ID=0x1E through the PCIe configuration space, analyzing the T_POWERON_SCALE / VALUE field, and obtaining the theoretical recovery time T_power_on of the SSD device from L1.2 to the normal state. T_power_on is the theoretical time required for the SSD itself to recover to the normal state from L1.2.

[0024] In step S12, set Bit[5]=1.

[0025] The specific method of step S2 is as follows: S21, ASPM low power strategy configuration: setting the ASPM field of the link control register to L0s+L1 enabled, and verifying the L1.2 as a substate support bit; setting the PCI-PM L1.2 Enable=1 in the PCI-PM control register, and confirming that both devices support the L1.2 substate; S22, LTR threshold setting: configuring the delay tolerance report register according to the theoretical recovery time T_power_on of the SSD, and setting the maximum acceptable exit delay to match the T_power_on value.

[0026] The specific method of step S3 is as follows: S31, platform characteristic parameters are extracted by CPUID and PCH registers; S32, a database is generated by using the extracted data and is stored in an application software of a solid state disk, and a low-power consumption strategy library of the platform is constructed.

[0027] In step S31, the parameters include that a processor manufacturer code is obtained by a script called by an application software through a CPUID instruction, a CPU microarchitecture version is obtained by the script reading an SMBIOS Type4 record, and L1.2 reference timing is extracted by the script accessing a PCH register from a configuration space.

[0028] In specific use, the application can be applied in different types of CPU platforms, when applied in an Intel platform, in step S4, platform characteristic register detection is performed on the Intel platform: a PM_CFG4 register of the PCH is read by a script, and a theoretical recovery time T_power_on value of a host end is obtained. In the embodiment, a bit field corresponding to the PM_CFG4 register is Bus 0, Device 0x1F, and Offset 0xE4. When applied in an AMD platform, in step S4, platform characteristic register detection is performed on the AMD platform: a PM_CTRL register of the FCH is read by a script, and the theoretical recovery time T_power_on value of the host end is obtained.

[0029] In step S5, the Intel platform is taken as an example in the embodiment, CLKREQ# is forcibly pulled high through the PM_CFG register of the PCH, so that the SSD device enters the L1.2 state.

[0030] The specific method of step S6 is as follows: S61, when the theoretical recovery time T_power_on or T_SSD_min of the host end changes, T_hold is recalculated and the register is updated, and a script is started to trigger a dynamic compensation process; S62, real-time parameter acquisition: S621, a PCIe device PMCSR register is read to obtain a current power supply state; S622, a T_SSD_min value is obtained through a PHY register; and S623, actual timing is extracted from a CPU characteristic register; S63, dynamic compensation calculation: S631, it is ensured that T_hold covers the host end power supply recovery time T_power_on and the SSD response delay T_SSD_min in the worst case; S632, a manufacturer preset fault tolerance parameter β coefficient is selected according to a manufacturer; and S633, a compensation value is calculated: T_hold =max( T_SSD_min, T_power_on × β + 2us). The fault tolerance parameter β=1.2 for the Intel platform, 1.8 for the AMD platform, and 1.0 for the domestic platform. S64, Register write: Write the compensation value calculated in step S63 to the host PCIe controller and PHY register; S641, Modify PCIe controller register; S642: Synchronously update PHY timing.

[0031] Where T_hold represents the hold time, covering the worst-case timing; T_SSD_min represents the shortest time that the CLKREQ# signal must remain stable when the SSD switches to a low-power state, ensuring that the internal circuitry of the SSD completes the state switch and avoiding data loss or link errors due to insufficient timing.

[0032] In step S7, it is confirmed whether the actual recovery time of the host reference clock is less than T_hold. If the actual recovery time is less than T_hold, the link is normal and L1.2 exit trigger is triggered. If the actual recovery time is greater than T_hold, secondary compensation is triggered and the β coefficient is updated. L1.2 exit verification is performed again until the actual recovery time is less than T_hold, the link is normal, and the test is exited.

[0033] In step S7, it is confirmed that the actual recovery time of the host reference clock is less than T_hold, ensuring that the internal power recovery time of the SSD device, i.e., T_power_on, has been completely exhausted when it exits L1.2, and then the host is allowed to resume REFCLK, so as to avoid link training failure or data error due to timing conflicts.

[0034] The platform for the aforementioned solid-state drive adaptive reference clock compensation method includes: A PC platform is provided as a verification environment for a multi-platform adaptive solid-state drive reference clock compensation method. PC host platform processor, used to execute computer programs; The PC platform uses the Linux operating system to manage and schedule computer hardware, software, and data resources. Application software, used to store feature library data, is provided to customers along with the solid-state drive and serves as the entry point for calling scripts; Test scripts are used for: PCIe configuration space query; L1.2 function enable; platform feature library establishment; platform feature judgment; control register sending high / low CLKREQ# signal; real-time parameter acquisition and dynamic compensation parameter writing; test result report; PC platform memory provides an environment for the PC platform operating system and the test script to run; The solid-state drive under test.

[0035] The application provides a self-adaptive dynamic compensation mechanism through application software of a solid state disk, and significantly improves cross-platform compatibility of PCIe low-power state switching. A feature recognition unit detects platform types through a CPUID instruction in real time, belongs to which of Intel, AMD and domestic products, automatically matches an optimal compensation parameter beta coefficient, and solves the adaptation problem of a traditional fixed threshold scheme under different platforms.

Claims

1. A compensation method for an adaptive reference clock in a solid-state drive, characterized in that: Includes the following steps: S1 runs the application software that comes with the solid-state drive and calls the script to perform PCIe configuration space detection during the initialization phase; S2 enables L1.2 functionality; S3: Build the platform library and obtain host parameters; S4, perform platform feature register detection; S5, the application software calls the script to respond to the SSD device entering the L1.2 state; S6, after obtaining the host parameters, start the dynamic compensation process; S7 verifies the effectiveness of compensation through low-power switching of the LTSSM state machine.

2. The compensation method for an adaptive reference clock in a solid-state drive according to claim 1, characterized in that: The specific method of step S1 is as follows: S11, Locate the Capability linked list pointer: The script reads the device PCIe Capability pointer and locates the PowerManagement Capability structure; S12, Basic PM Capability Detection: Read the PM Capability structure and confirm that the PMCSR register supports the L1.2 sub-state; S13, Locate the extended PM Capability and obtain SSD-side parameters: Locate the extended power management capability structure of Cap ID=0x1E through the PCIe configuration space, parse the T_POWERON_SCALE / VALUE field, and obtain the theoretical recovery time T_power_on of the SSD device. T_power_on is the theoretical time required for the SSD itself to recover from L1.2 to the normal state.

3. The compensation method for an adaptive reference clock in a solid-state drive according to claim 1, characterized in that: The specific method for step S2 is as follows: S21, ASPM low-power policy configuration: Set the ASPM field of the link control register to L0s+L1 enable, and verify that L1.2 is a sub-state support bit; set PCI-PM L1.2 Enable=1 in the PCI-PM control register to confirm that both devices support L1.2 sub-state; S22, LTR Threshold Setting: Configure the latency tolerance report register based on the SSD's theoretical recovery time T_power_on, and set the maximum acceptable exit latency to match the T_power_on value.

4. The compensation method for an adaptive reference clock in a solid-state drive according to claim 1, characterized in that: The specific method for step S3 is as follows: S31, platform feature parameter extraction is obtained through CPUID and PCH registers: S32 uses extracted data to generate a database stored in the application software that comes with the solid-state drive, and builds the platform's low-power strategy library.

5. The compensation method for an adaptive reference clock in a solid-state drive according to claim 4, characterized in that: In step S31, the parameters include the application software calling the script to obtain the processor manufacturer code through the CPUID instruction, the script reading the SMBIOS Type4 record to obtain the CPU microarchitecture version, and the script accessing the PCH register from the configuration space to extract the L1.2 reference timing.

6. The compensation method for an adaptive reference clock in a solid-state drive according to claim 1, characterized in that: In step S4, platform characteristic register detection is performed on the Intel platform: the script reads the PM_CFG4 register of the PCH to obtain the theoretical recovery time T_power_on value of the host.

7. The compensation method for an adaptive reference clock in a solid-state drive according to claim 1, characterized in that: In step S4, platform characteristic register detection is performed on the AMD platform: the script reads the PM_CTRL register of FCH to obtain the theoretical recovery time T_power_on value of the host side.

8. The compensation method for an adaptive reference clock in a solid-state drive according to claim 1, characterized in that: The specific method for step S6 is as follows: S61, when the theoretical recovery time T_power_on or T_SSD_min on the host changes, recalculate T_hold and update the register, triggering the script to start the dynamic compensation process; S62, Real-time Parameter Acquisition: S621, Read the PCIe device PMCSR register to obtain the current power status; S622, Obtain T_SSD_min through the PHY register; S623, Extract the actual timing from the CPU feature register; S63: Dynamic Compensation Calculation S631, ensure that T_hold covers the worst-case host power recovery time T_power_on and SSD response latency T_SSD_min; S632, select the manufacturer's preset fault tolerance parameter β coefficient according to the manufacturer; S633, calculate the compensation value: T_hold = max( T_SSD_min, T_power_on × β + 2μs); S64, Register write: Write the compensation value calculated in step S63 to the host PCIe controller and PHY register; S641, Modify PCIe controller register; S642: Synchronously update PHY timing; Where T_hold represents the hold time, covering the worst-case timing; T_SSD_min represents the shortest time that the CLKREQ# signal must remain stable when the SSD switches to a low-power state.

9. The compensation method for an adaptive reference clock in a solid-state drive according to claim 1, characterized in that: In step S7, it is confirmed whether the actual recovery time of the host reference clock is less than T_hold. If the actual recovery time is less than T_hold, the link is normal and L1.2 exits the trigger. If the actual recovery time is greater than T_hold, a secondary compensation is triggered and the β coefficient is updated. The L1.2 exit verification is performed again until the actual recovery time is less than T_hold, the link is normal, and the test is exited.

10. A platform for a compensation method of an adaptive reference clock for a solid-state drive according to any one of claims 1 to 9, characterized in that: include: A PC platform is provided as a verification environment for a multi-platform adaptive solid-state drive reference clock compensation method. PC host platform processor, used to execute computer programs; The PC platform uses the Linux operating system to manage and schedule computer hardware, software, and data resources. Application software, used to store feature library data, is provided to customers along with the solid-state drive and serves as the entry point for calling scripts; Test scripts are used for PCIe configuration space query; L1.2 function enabling; platform feature library establishment; platform feature judgment; The control register sends a high / low CLKREQ# signal; real-time parameter acquisition and dynamic compensation parameter writing; test result reporting; PC platform memory provides an environment for the PC platform operating system and the test script to run; The solid-state drive under test.

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