An adapter device and method compatible with different mcio connector pin definitions

Abstract

The application relates to an adapter device and method compatible with different MCIO connector pin definitions, which comprises a first MCIO port, a mainboard clock generator, a second MCIO port, a backboard processor, a backboard clock expander and a module connection port. The clock generator is arranged on the mainboard and connected with the first MCIO port. The first MCIO port is connected with the second MCIO port through a standard MCIO cable. The backboard processor is arranged on the backboard of a server and connected with the second MCIO port. The backboard clock expander is arranged on the backboard of the server and used for expanding a clock port. The module connection port is arranged on the backboard of the server and used for connecting a downstream module. The second MCIO port and the backboard clock expander are respectively connected with the module connection port. The application is compatible with the different MCIO connector pin definitions of OCSP and MGX under the premise of using the standard MCIO cable of the hard disk backboard.

Description

Technical Field

[0001] This invention belongs to the field of servers, and specifically relates to an adapter and method compatible with different MCIO connector pin definitions. Background Technology

[0002] With the gradual development of modular servers, the entire server machine has been decoupled into different modules such as CPU motherboard, power supply backplane, fan backplane, and hard drive backplane. This reduces the interdependence between different modules and facilitates independent replacement and maintenance of each module. To further achieve complete compatibility and replacement of each module, the server industry has seen the emergence of two major server design specifications: Intel OCSP and Nvidia MGX. These specifications not only set requirements for system architecture and overall size but also impose strict constraints on the interface definitions involving the interconnection of different modules.

[0003] Taking the interconnection between the CPU motherboard and the hard drive backplane as an example, the MCIO connector is one such definition. However, because the two major specifications define the MCIO connector differently, even if there are two hard drive backplanes that meet different specifications but have completely identical structural dimensions, they are not functionally compatible.

[0004] Current technology typically involves designing two different hard drive backplanes to adapt to these two specifications. However, this approach has the following drawbacks:

[0005] 1) Redesign and production are required, which increases overall costs and extends the R&D cycle.

[0006] 2) If other standards emerge in the future, resulting in an increase in the types of backplanes, the maintenance difficulty will become increasingly greater, and different backplanes will be easily confused.

[0007] 3) Changing the standard MCIO cable pin definition means that MCIO cables of every length need to be redesigned, which increases costs and makes it easier to make mistakes during assembly and maintenance. Summary of the Invention

[0008] This invention provides an adapter and method compatible with different MCIO connector pin definitions, aiming to solve at least one of the technical problems existing in the prior art.

[0009] The technical solution of this invention relates to an adapter device compatible with different MCIO connector pin definitions, used to be compatible with the different MCIO connector pin definitions based on the Open Common Server Platform (OCSP) specification and the Modular GPU Acceleration Platform (MGX) specification.

[0010] The adapter compatible with different MCIO connector pin definitions is installed within the server, which includes at least a motherboard and a backplane. The adapter compatible with different MCIO connector pin definitions includes:

[0011] The first MCIO port is located on the server's motherboard.

[0012] A motherboard clock generator, wherein the clock generator is mounted on the motherboard and connected to the first MCIO port;

[0013] The second MCIO port is located on the backplane of the server, and the first MCIO port and the second MCIO port are connected via a standard MCIO cable;

[0014] A backplane processor is disposed on the backplane of the server and is connected to the second MCIO port;

[0015] A backplane clock extender is used to extend the clock port, and the backplane clock extender is installed on the backplane of the server;

[0016] A module connection port is used to connect downstream modules. The module connection port is set on the backplane of the server. The second MCIO port and the backplane clock extender are respectively connected to the module connection port.

[0017] Furthermore, based on the OCSP or MGX specification, each of the second MCIO ports is provided with an adapter pin for connection to the backplane processor. This adapter pin is used to simultaneously adapt to both the OCSP and MGX specifications. For each of the second MCIO ports, the adapter pin includes:

[0018] Pins A11, A12, A26, A27, A29, A30, B9, B26, and B27.

[0019] Furthermore, the adapter pin is connected to the backplane processor, and the port type of the adapter pin is set to bidirectional inout.

[0020] Furthermore, pins A11 and A12 in the adapter pins are used by the backplane processor to perform logic processing and output to the external circuit.

[0021] Furthermore, the motherboard is provided with at least a central processing unit (CPU), a management controller (BMC), and a motherboard processor for basic logic control of the motherboard, wherein the CPU and the motherboard processor are respectively connected to the first MCIO port;

[0022] The backplate includes at least one or more of a hard drive backplate, a power supply backplate, and a fan backplate. When the backplate is a hard drive backplate, the module connection port is a hard drive connector.

[0023] The number of the first MCIO port and the second MCIO port are equal and at least one, and the corresponding first MCIO port and second MCIO port are connected through a standard MCIO cable;

[0024] The backplane processor is a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), or a microprocessor;

[0025] The backplane clock extender is used to extend the input clock signal REFCLK_P / N of at least one MCIO connector, and the backplane clock extender is connected to at least one MCIO input clock signal.

[0026] Furthermore, the backplate also includes:

[0027] The project serial number acquisition module is used to indicate whether the current connection method is based on the Open Common Server Platform (OCSP) specification or the Modular GPU Acceleration Platform (MGX) specification. The project serial number acquisition module is one or a combination of IIC communication acquisition module and hardware control acquisition module.

[0028] Furthermore, after obtaining the project serial number ID, the backplane processor determines whether the current connection method is based on the OCSP or MGX specification, and then locks the specific pin definition for each adapter pin.

[0029] If the corresponding adapter pin is an input pin, it is assigned to the corresponding function variable of the backplane processor. If the adapter pin is an output pin, the logic variable generated inside the backplane processor is output to this pin, and finally output to the target device through the second MCIO port.

[0030] Furthermore, this invention proposes an adaptation method compatible with different MCIO connector pin definitions, applied to an adaptation device compatible with different MCIO connector pin definitions. The adaptation device includes a first MCIO port and a second MCIO port connected via a standard MCIO cable, a central processing unit (CPU) and a motherboard clock generator connected to the first MCIO port, a backplane processor, a backplane clock extender, and a module connection port connected to the second MCIO port. The adaptation method for compatible with different MCIO connector pin definitions includes the following steps:

[0031] S100: Upon power-up, the backplane processor obtains the project serial number ID and uses the project serial number ID to determine whether the current connection is based on the Open Common Server Platform (OCSP) specification or the Modular GPU Acceleration Platform (MGX) specification.

[0032] S200. If the current connection is based on the Open Common Server Platform (OCSP) specification, define the adapter pins as PERST0#, PRSNT0#, PERST1#, PRSNT1#, HP_SMB_CLK, HP_SMB_DAT, N / C, N / C and HP_SMB_ALERT# in sequence.

[0033] S300. If the current connection is based on the Modular GPU Acceleration Platform (MGX) specification, define the adapter pins as PERST0#, PRSNT0#, N / C, N / C, N / C, N / C, HP_SMB_ALERT#, HP_SMB_DAT and HP_SMB_CLK in sequence.

[0034] S400: When the adapter pin is an input pin, the pin level value is assigned to the corresponding functional module. When the adapter pin is an output pin, the pin level value is output to the external circuit through the backplane processor.

[0035] Furthermore, step S100 includes:

[0036] S110. When the project serial number acquisition module is an IIC communication-based acquisition module, the backplane processor communicates with the management controller BMC set on the motherboard through the IIC protocol. The management controller BMC writes the current project serial number ID into the register of the IIC Slave module of the backplane processor through the IIC protocol.

[0037] S120. When the project serial number acquisition module is a hardware control-based acquisition module, the backplane processor obtains the current project serial number ID by querying the level signal of the jumper cap or DIP switch set on the motherboard or backplane.

[0038] S130. When the project serial number acquisition module includes an IIC communication-based acquisition module and a hardware control-based acquisition module, the backplane processor performs a bitwise AND operation on the two acquired project serial number IDs and outputs the final project serial number ID.

[0039] Furthermore, the present invention also proposes a computer-readable storage medium storing program instructions thereon, which, when executed by a processor, implement the aforementioned adaptation method compatible with different MCIO connector pin definitions.

[0040] Compared with existing technologies, the present invention has the following characteristics:

[0041] This invention proposes an adapter and method compatible with different MCIO connector pin definitions. Under the premise of using standard MCIO cables on the hard drive backplane, it is not only compatible with different MCIO connector pin definitions of OCSP and MGX, but also has good compatibility with new MCIO definitions that may appear in the future. Ultimately, it achieves the goal of one backplane being compatible with multiple models such as OCSP and MGX. Attached Figure Description

[0042] Figure 1 A schematic diagram of the structure of an adapter device to be compatible with different MCIO connector pin definitions.

[0043] Figure 2 A schematic diagram of the pin definitions for MCIO in OCSP and MGX compatibility.

[0044] Figure 3 A schematic diagram of one embodiment of an adapter device for compatibility with different MCIO connector pin definitions.

[0045] Figure 4 This is a schematic diagram showing a hard drive backplane with multiple MCIO connectors, where the sideband of each MCIO needs to be connected to the CPLD.

[0046] Figure 5 A schematic diagram showing a backplane clock extender that connects only one input when expanding multiple hard drive connectors.

[0047] Figure 6 This is a schematic diagram of an embodiment for obtaining a project serial number based on an IIC communication acquisition module.

[0048] Figure 7A flowchart illustrating the adaptation method for compatibility with different MCIO connector pin definitions.

[0049] Figure 8 A flowchart illustrating one embodiment of an adaptation method for compatibility with different MCIO connector pin definitions. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] The following will provide a clear and complete description of the concept, specific structure, and technical effects of the present invention in conjunction with the embodiments and accompanying drawings, so as to fully understand the purpose, solution, and effects of the present invention.

[0052] It should be noted that, unless otherwise specified, when a feature is referred to as "fixed" or "connected" to another feature, it can be directly fixed or connected to the other feature, or indirectly fixed or connected to the other feature. The singular forms "a," "described," and "the" used herein are also intended to include the plural forms, unless the context clearly indicates otherwise. Furthermore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and not for limiting the invention. The term "and / or" as used herein includes any combination of one or more of the associated listed items.

[0053] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from each other. For example, a first element may also be referred to as a second element without departing from the scope of this disclosure, and similarly, a second element may also be referred to as a first element. Any and all instances or exemplary language (“e.g.,” “such as,” etc.) used herein are intended only to better illustrate embodiments of the invention and, unless otherwise required, do not impose a limitation on the scope of the invention. Furthermore, the industry term “pose” as used herein refers to the position and orientation of an element relative to a spatial coordinate system.

[0054] Reference Figures 1 to 8This invention provides an adapter compatible with different MCIO connector pin definitions, used to accommodate the different MCIO connector pin definitions based on the Open Common Server Platform (OCSP) specification and the Modular GPU Acceleration Platform (MGX) specification.

[0055] The adapter compatible with different MCIO connector pin definitions is installed within the server, which includes at least a motherboard and a backplane. The adapter compatible with different MCIO connector pin definitions includes:

[0056] The first MCIO port is located on the server's motherboard.

[0057] A motherboard clock generator, wherein the motherboard clock generator is mounted on the motherboard and connected to the first MCIO port;

[0058] The second MCIO port is located on the backplane of the server, and the first MCIO port and the second MCIO port are connected via a standard MCIO cable;

[0059] A backplane processor is disposed on the backplane of the server and is connected to the second MCIO port;

[0060] A backplane clock extender is used to extend the clock port, and the backplane clock extender is installed on the backplane of the server;

[0061] A module connection port is used to connect downstream modules. The module connection port is set on the backplane of the server. The second MCIO port and the backplane clock extender are respectively connected to the module connection port.

[0062] Compared with existing technologies, the present invention has the following characteristics:

[0063] This invention proposes an adapter and method compatible with different MCIO connector pin definitions. Under the premise of using standard MCIO cables on the hard drive backplane, it is not only compatible with different MCIO connector pin definitions of OCSP and MGX, but also has good compatibility with new MCIO definitions that may appear in the future. Ultimately, it achieves the goal of one backplane being compatible with multiple models such as OCSP and MGX.

[0064] Furthermore, based on the OCSP or MGX specification, each of the second MCIO ports is provided with an adapter pin for connection to the backplane processor. This adapter pin is used to simultaneously adapt to both the OCSP and MGX specifications. For each of the second MCIO ports, the adapter pin includes:

[0065] Pins A11, A12, A26, A27, A29, A30, B9, B26, and B27.

[0066] Specifically, when drawing the hard drive backplane schematic, for the first MCIO port and the second MCIO port, refer to Tables 1 to 3 and... Figure 2 Table 1 is the MCIO definition table based on the OCSP specification, and Table 2 is the MCIO definition table based on the MGX specification.

[0067] The MCIO connector is designed according to the pin definitions in Table 3. Except for pins A11 (Sideband0), A12 (Sideband1), A26 (Sideband2), A27 (Sideband3), A29 (Sideband4), A30 (Sideband5), B9 (Sideband6), B26 (Sideband7), and B27 (Sideband8), the other pins are consistent with the OCSP and MGX specifications.

[0068] Table 1:

[0069]

[0070] Table 2:

[0071]

[0072] Table 3:

[0073]

[0074] Furthermore, the adapter pin is connected to the backplane processor, and the port type of the adapter pin is set to bidirectional inout.

[0075] Furthermore, pins A11 and A12 in the adapter pins are used by the backplane processor to perform logic processing and output to the external circuit.

[0076] Furthermore, refer to Figure 3 The motherboard is provided with at least a central processing unit (CPU), a management controller (BMC), and a motherboard processor for basic logic control of the motherboard. The CPU and the motherboard processor are respectively connected to the first MCIO port.

[0077] The backplate includes at least one or more of a hard drive backplate, a power supply backplate, and a fan backplate. When the backplate is a hard drive backplate, the module connection port is a hard drive connector.

[0078] The number of the first MCIO port and the second MCIO port are equal and at least one, and the corresponding first MCIO port and second MCIO port are connected through a standard MCIO cable;

[0079] The backplane processor is a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), or a microprocessor;

[0080] The backplane clock extender is used to extend the input clock signal REFCLK_P / N of at least one MCIO connector, and the backplane clock extender is connected to at least one MCIO input clock signal.

[0081] Specifically, refer to Figure 3 and Figure 4 Connect all 9 Sideband signals of MCIO in Table 1 to the backplane processor (backplane CPLD logic device). If there are multiple MCIO connectors on the hard drive backplane, the Sideband of each MCIO needs to be connected to the CPLD.

[0082] Reference Figure 5 Because the MGX specification defines only one 100MHz clock signal per MCIO, but in practice, one MCIO connects to two hard drives, requiring two sets of clock signals, a Clock Buffer (an independent clock extension chip, selectable in different specifications such as 4-Output / 8-Output, etc.) needs to be used on the hard drive backplane to extend the input clock. The Clock Buffer's input is connected to the REFCLK_P / N provided by MCIO1 (Pin B11 / B12 of the MCIO1 connector), and its output is connected to the hard drive connector. If there are multiple MCIO connectors on the hard drive backplane, the input clock signal pins of the other MCIOs can be left unconnected.

[0083] Furthermore, the backplate also includes:

[0084] The project serial number acquisition module is used to indicate whether the current connection method is based on the Open Common Server Platform (OCSP) specification or the Modular GPU Acceleration Platform (MGX) specification. The project serial number acquisition module is one or a combination of IIC communication acquisition module and hardware control acquisition module.

[0085] Furthermore, after obtaining the project serial number ID, the backplane processor determines whether the current connection method is based on the OCSP or MGX specification, and then locks the specific pin definition for each adapter pin.

[0086] If the corresponding adapter pin is an input pin, it is assigned to the corresponding function variable of the backplane processor. If the adapter pin is an output pin, the logic variable generated inside the backplane processor is output to this pin, and finally output to the target device through the second MCIO port.

[0087] Furthermore, this invention proposes an adaptation method compatible with different MCIO connector pin definitions, applied to an adaptation device compatible with different MCIO connector pin definitions. The adaptation device includes a first MCIO port and a second MCIO port connected via a standard MCIO cable, a central processing unit (CPU) and a motherboard clock generator connected to the first MCIO port, a backplane processor, a backplane clock extender, and a module connection port connected to the second MCIO port. (Refer to...) Figure 7 and Figure 8 The adaptation method for compatibility with different MCIO connector pin definitions includes the following steps:

[0088] S100: Upon power-up, the backplane processor obtains the project serial number ID and uses the project serial number ID to determine whether the current connection is based on the Open Common Server Platform (OCSP) specification or the Modular GPU Acceleration Platform (MGX) specification.

[0089] S200. If the current connection is based on the Open Common Server Platform (OCSP) specification, define the adapter pins as PERST0#, PRSNT0#, PERST1#, PRSNT1#, HP_SMB_CLK, HP_SMB_DAT, N / C, N / C and HP_SMB_ALERT# in sequence.

[0090] S300. If the current connection is based on the Modular GPU Acceleration Platform (MGX) specification, define the adapter pins as PERST0#, PRSNT0#, N / C, N / C, N / C, N / C, HP_SMB_ALERT#, HP_SMB_DAT and HP_SMB_CLK in sequence.

[0091] S400: When the adapter pin is an input pin, the pin level value is assigned to the corresponding functional module. When the adapter pin is an output pin, the pin level value is output to the external circuit through the backplane processor.

[0092] Furthermore, step S100 includes:

[0093] S110. When the project serial number acquisition module is an IIC communication-based acquisition module, the backplane processor communicates with the management controller BMC set on the motherboard through the IIC protocol. The management controller BMC writes the current project serial number ID into the register of the IIC Slave module of the backplane processor through the IIC protocol.

[0094] S120. When the project serial number acquisition module is a hardware control-based acquisition module, the backplane processor obtains the current project serial number ID by querying the level signal of the jumper cap or DIP switch set on the motherboard or backplane.

[0095] S130. When the project serial number acquisition module includes an IIC communication-based acquisition module and a hardware control-based acquisition module, the backplane processor performs a bitwise AND operation on the two acquired project serial number IDs and outputs the final project serial number ID.

[0096] Specifically, refer to Figure 6 Regarding the acquisition of the Project Serial Number ID (Project_ID), the hardware must choose one of the following two methods. In some embodiments, both methods are reserved.

[0097] Method 1: Connect a set of BMC management I2C signals to the CPLD, and the BMC directly writes the current ID into the register of the I2C Slave module inside the CPLD;

[0098] Method 2: Connect a set of hardware signals to the CPLD, and externally control the jumper cap or DIP switch to achieve the conversion of different IDs.

[0099] For method one, after power-on, the BMC writes the current project ID (corresponding to) to the CPLD on the hard drive backplane via I2C. Figure 6(SMB_BMC_SCL and SMB_BMC_SDA). For method two, the hardware ID (corresponding to) is obtained by inputting signals to the CPLD through hardware jumpers / DIP switches on the hard drive backplane. Figure 6 (HW_ID0 to HW_ID7 in the dataset).

[0100] Users can choose one of the two methods to obtain Project_ID based on their actual situation. If both methods are reserved, the CPLD code will eventually perform a bitwise AND operation on the two obtained IDs and output the final Project_ID.

[0101] Referring to Table 4, the MCIO Pin definition on the CPU motherboard side of the hard drive backplane interconnection is confirmed by the obtained project ID to determine whether the OCSP specification or the MGX specification is used.

[0102] Table 4:

[0103]

[0104] After confirming the specific functions of Sideband0 to 8 based on the specification definition, if it is an input signal, it is assigned to the corresponding function variable of the CPLD; if it is an output signal, the value of the logic variable generated inside the CPLD is output to this signal, and finally output to the target device via MCIO.

[0105] It is important to note that the Sideband0 through 8 ports should all be set to bidirectional inout. Additionally, if multiple MCIO connectors exist, the Sideband0 through 8 signals for each MCIO should be handled in a similar manner.

[0106] For example, if the project ID obtained by the CPLD upon power-up indicates that the current MCIO Pin definition is OCSP, then the function of Sideband0 at this time is to input the PCIe reset signal of hard disk 0 to the CPLD. In the CPLD, Sideband0 should be assigned to the relevant internal module that controls the PCIe reset of hard disk 0.

[0107] Furthermore, the present invention also proposes a computer-readable storage medium storing program instructions thereon, which, when executed by a processor, implement the aforementioned adaptation method compatible with different MCIO connector pin definitions.

[0108] Part of the code is as follows:

[0109] module top (

[0111] Input wire cpld_clk, / / Input, cpld 25M clock

[0112] input wire Rst_n, / / Input, cpld reset signal

[0113] input wire [7:0] Hw_ID, / / Input, hardware ID signal

[0114] inout wire SMB_BMC_SCL, / / BMC SMBus clock signal

[0115] inout wire SMB_BMC_SDA, / / BMC SMBus data signal

[0116] inout wire Sideband0, / / Input / output, connects to MCIO pin A11

[0117] inout wire Sideband1, / / Input / output, connect to MCIO pin A12

[0118] inout wire Sideband2, / / Input / output, connects to MCIO pin A26

[0119] inout wire Sideband3, / / Input / output, connects to MCIO pin A27

[0120] inout wire Sideband4, / / Input / output, connects to MCIO pin A29

[0121] Inout wire Sideband5, / / Input / Output, connects to MCIO Pin A30

[0122] In / out wire Sideband6, / / Input / Output, connects to MCIO Pin B9

[0123] Inout wire Sideband7, / / Input / Output, connects to MCIO Pin B26

[0124] inout wire Sideband8 / / Input / output, connects to MCIO pin B27 );

[0126] localparam OCSP = 8'd0;

[0127] localparam MGX = 8'd1;

[0128] wire [7:0] Project_ID;

[0129] wire [7:0] wReg_ID;

[0130] wire SMB_HP_SCL, SMB_HP_SDA, HP_SMB_ALERT;

[0131] wire PERST0_N, PRSNT0_N,PERST1_N, PRSNT1_N;

[0132] wire wOESDA_EXP1; / / Hot-swap module HP_SDA output, 1: HP_SDA output high impedance, 0: HP_SDA output low impedance

[0133] / / ***********Core Code*********** / /

[0134] assign Project_ID = wReg_ID & Hw_ID; / / Get the current Project_ID to confirm the MCIOPin definition specification

[0135] assign SMB_HP_SCL = (Project_ID == OCSP) ? Sideband4 : ((Project_ID == MGX) ? Sideband8 : Sideband2); / / Confirm hot-swap module input signals HP_SCL, OCSP:Sideband4, MGX:Sideband8, others:Sideband2

[0136] assign SMB_HP_SDA = (Project_ID == OCSP) ? Sideband5 : ((Project_ID == MGX) ? Sideband7 : Sideband3); / / Confirm hot-swap module input signals HP_SDA, OCSP:Sideband5, MGX:Sideband7, others:Sideband3

[0137] assign Sideband5 = (Project_ID == OCSP) ? (wOESDA_EXP1 ? 1'bz : 1'b0): PRSNT1_N; / / Assign a value to Sideband5 when it is for output, OCSP: HP_SDA output, others: hard disk in place

[0138] assign Sideband7 = (Project_ID == MGX) ? (wOESDA_EXP1 ? 1'bz : 1'b0): PRSNT1_N; / / Assign a value to Sideband7 when it is for output, MGX: HP_SDA output, others: hard disk in place

[0139] assign Sideband8 = (Project_ID == MGX) ? 1'bz : HP_SMB_ALERT; / / Sideband8 is assigned a value when outputting, MGX: N / C, others: HP_SMB_ALERT

[0140] assign Sideband6 = (Project_ID == MGX) ? HP_SMB_ALERT : 1'bz; / / Sideband6 is assigned a value for output, MGX: HP_SMB_ALERT, others: N / C

[0141] assign Sideband1 = (Project_ID == MGX) ? (PRSNT0_N && PRSNT1_N) : PRSNT0_N; / / Sideband1 is assigned a value when outputting; MGX: either disk 0 or disk 1 is active; others: disk 0 is active.

[0142] assign Sideband3 = (Project_ID == MGX) ? 1'bz : ((Project_ID == OCSP)? PRSNT1_N : (wOESDA_EXP1? 1'bz : 1'b0)); / / Sideband3 is assigned a value when outputting, MGX: N / C, OCSP: Hard disk 1 is in place, others: HP_SDA output

[0143] assign PERST0_N = (Project_ID == OCSP) ? Sideband0 : (PRSNT0_N ? 1'b0: Sideband0); / / Confirm the hard disk control module output signal: Hard disk 0 reset signal, OCSP: Sideband0, others: determine based on the presence signal of hard disk 0.

[0144] assign PERST1_N = (Project_ID == OCSP) ? Sideband2 : (PRSNT1_N ? 1'b0: Sideband0); / / Confirm the hard disk control module output signal: Hard disk 1 reset signal, OCSP: Sideband2, others: judged based on the presence signal of hard disk 1.

[0145] The following two modules are a general-purpose PCA9555 module and an I2C Slave module. Both are general-purpose modules; only the top-level code is listed to aid understanding of the logic above.

[0146] / / PCA9555 module, parses the SMB_HP_SCL / SDA signals used to manage hard drive hot-swapping.

[0147] PCA9555 mIO_exp (

[0148] .iModule_Address(7'b0100000), / / ADDR = 7'h20 ->8'h40

[0149] .iClk(cpld_clk),

[0150] .iRst(Rst_n),

[0151] .iSCL(SMB_HP_SCL),

[0152] .iSDA(SMB_HP_SDA),

[0153] .onSDAOE(wOESDA_EXP1),

[0154] .onIntOE(HP_SMB_ALERT) );

[0156] / / I2C Slave module, used to receive the Project_ID transmitted from the BMC to the CPLD

[0157] IIC_Slave IIC_Slave_inst (

[0159] .iClk(cpld_clk),

[0160] .iRst(Rst_n),

[0161] .iModule_Address(7'h68),

[0162] .iSCL(SMB_BMC_SCL),

[0163] .iSDA(SMB_BMC_SDA),

[0164] .oReg_ID(wReg_ID) );

[0166] endmodule

[0167] It should be understood that the method steps in the embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium. The method can use standard programming techniques. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if necessary, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Furthermore, for this purpose, the program can run on a programmed application-specific integrated circuit (ASIC).

[0168] Furthermore, the procedures described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The procedures described herein (or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions, and may be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The computer program comprises a plurality of instructions executable by one or more processors.

[0169] Furthermore, the method can be implemented in any suitable type of computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or in communication with charged particle tools or other imaging devices, etc. Aspects of the invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it is readable by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein. Furthermore, the machine-readable code, or portions thereof, can be transmitted via wired or wireless networks. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media comprises instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. When programmed according to the methods and techniques described in the invention, the invention may also include the computer itself.

[0170] A computer program can be applied to input data to perform the functions described herein, thereby transforming the input data to generate output data stored in non-volatile memory. The output information can also be applied to one or more output devices, such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including specific visual depictions of physical and tangible objects generated on the display.

[0171] The above description is merely a preferred embodiment of the present invention. The present invention is not limited to the above-described embodiments. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention, as long as they achieve the technical effects of the present invention by the same means, should be included within the scope of protection of the present invention. Within the scope of protection of the present invention, the technical solutions and / or implementation methods can have various modifications and variations.

Claims

1. An adapter device compatible with different MCIO connector pin definitions, used to be compatible with the different MCIO connector pin definitions based on open general server platform specifications and modular flexible architecture computing platform specifications, characterized in that, The adapter compatible with different MCIO connector pin definitions is installed within the server, which includes at least a motherboard and a backplane. The adapter compatible with different MCIO connector pin definitions includes: The first MCIO port is located on the server's motherboard. A motherboard clock generator, wherein the clock generator is mounted on the motherboard and connected to the first MCIO port; The second MCIO port is located on the backplane of the server, and the first MCIO port and the second MCIO port are connected via a standard MCIO cable; A backplane processor is disposed on the backplane of the server and is connected to the second MCIO port; A backplane clock extender for extending clock ports, the backplane clock extender being mounted on the backplane of the server; A module connection port is used to connect to downstream modules. The module connection port is set on the backplane of the server. The second MCIO port and the backplane clock extender are respectively connected to the module connection port. The back plate also includes: The project serial number acquisition module is used to indicate whether the current connection method is based on the open general server platform specification or the modular and flexible architecture computing platform specification. The project serial number acquisition module is one or a combination of two of the IIC communication acquisition module and the hardware control method acquisition module. After obtaining the project serial number ID, the backplane processor determines whether the current connection method is based on the OCSP or MGX specification, and then locks the specific pin definition for each adapter pin. If the corresponding adapter pin is an input pin, it is assigned to the corresponding function variable of the backplane processor. If the adapter pin is an output pin, the logic variable generated inside the backplane processor is output to this pin, and finally output to the target device through the second MCIO port.

2. The adapter device compatible with different MCIO connector pin definitions according to claim 1, characterized in that, Based on the OCSP or MGX specification, each of the second MCIO ports is provided with an adapter pin for connection to the backplane processor. This adapter pin is used to adapt to both the OCSP and MGX specifications simultaneously. For each of the second MCIO ports, the adapter pin includes: Pins A11, A12, A26, A27, A29, A30, B9, B26, and B27.

3. The adapter device compatible with different MCIO connector pin definitions according to claim 2, characterized in that, The adapter pin is connected to the backplane processor, and the port type of the adapter pin is set to bidirectional inout.

4. The adapter device compatible with different MCIO connector pin definitions according to claim 2, characterized in that, Among the adapter pins, pins A11 and A12 are used by the backplane processor to perform logic processing and output to the external circuit.

5. The adapter device compatible with different MCIO connector pin definitions according to claim 1, characterized in that, The motherboard is provided with at least a central processing unit (CPU), a management controller (BMC), and a motherboard processor for basic logic control of the motherboard. The CPU and the motherboard processor are respectively connected to the first MCIO port. The backplate includes at least one or more of a hard drive backplate, a power supply backplate, and a fan backplate. When the backplate is a hard drive backplate, the module connection port is a hard drive connector. The number of the first MCIO port and the second MCIO port are equal and at least one, and the corresponding first MCIO port and second MCIO port are connected through a standard MCIO cable; The backplane processor is a complex programmable logic device, a field-programmable gate array, or a microprocessor; The backplane clock extender is used to extend the input clock signal REFCLK_P / N of at least one MCIO connector, and the backplane clock extender is connected to at least one MCIO input clock signal.

6. An adaptation method compatible with different MCIO connector pin definitions, applied to an adaptation device compatible with different MCIO connector pin definitions, wherein the adaptation device includes a first MCIO port and a second MCIO port connected via a standard MCIO cable, a central processing unit (CPU) and a motherboard clock generator connected to the first MCIO port, a backplane processor, a backplane clock extender, and a module connection port connected to the second MCIO port, characterized in that... The aforementioned adaptation method for compatibility with different MCIO connector pin definitions includes the following steps: S100: After power-on, the backplane processor obtains the project serial number ID and determines whether the current connection is based on the Open General Server Platform Specification or the Modular Flexible Architecture Computing Platform Specification. Step S100 includes: S110. When the project serial number acquisition module is an IIC communication-based acquisition module, the backplane processor communicates with the management controller BMC set on the motherboard through the IIC protocol. The management controller BMC writes the current project serial number ID into the register of the IIC Slave module of the backplane processor through the IIC protocol. S120. When the project serial number acquisition module is a hardware control-based acquisition module, the backplane processor obtains the current project serial number ID by querying the level signal of the jumper cap or DIP switch set on the motherboard or backplane. S130. When the project serial number acquisition module includes an IIC communication-based acquisition module and a hardware control-based acquisition module, the backplane processor will perform a bitwise AND operation on the two acquired project serial number IDs and output the final project serial number ID. S200. If the current connection is based on the Open General Server Platform Specification, the adapter pins are defined sequentially as PERST0#, PRSNT0#, PERST1#, PRSNT1#, HP_SMB_CLK, HP_SMB_DAT, N / C, N / C and HP_SMB_ALERT#. S300. If the current connection is based on the modular flexible architecture computing platform specification, the adapter pins are defined sequentially as PERST0#, PRSNT0#, N / C, N / C, N / C, N / C, HP_SMB_ALERT#, HP_SMB_DAT and HP_SMB_CLK. S400: When the adapter pin is an input pin, the pin level value is assigned to the corresponding functional module. When the adapter pin is an output pin, the pin level value is output to the external circuit through the backplane processor.

7. A computer-readable storage medium having program instructions stored thereon, characterized in that, When the program instructions are executed by the processor, the adaptation method as described in claim 6, which is compatible with different MCIO connector pin definitions, is implemented.

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