Thermal impedance parameter extraction method, wafer temperature acquisition method, device and equipment

Abstract

The invention relates to a thermal impedance parameter extraction method, a wafer temperature acquisition method, a device and equipment. Comprising the steps of building a finite element simulation model of the automatic control system; building a semi-physical simulation model of the automatic control system; setting simulation conditions of the semi-physical simulation model; according to the simulation condition, performing semi-physical simulation by using a semi-physical simulation model to obtain first simulation data, the first simulation data comprising first loss data of the target power semiconductor; inputting the first loss data into a finite element simulation model, and performing finite element simulation to obtain second simulation data; and determining a thermal impedance parameter of the target radiator according to the first simulation data and the second simulation data. Therefore, the first loss data is obtained through semi-physical simulation, and the first loss data can truly reflect the transient heating condition of the target power semiconductor, so that the accuracy of the obtained thermal impedance parameter of the target radiator is higher.

Description

Technical Field

[0001] This application relates to the field of power electronics, and in particular to methods for extracting thermal impedance parameters, methods for obtaining wafer temperature, apparatus and equipment. Background Technology

[0002] In automatic control systems, power semiconductor devices are the core switching components. During normal operation, as heat dissipation increases, the temperature of the power semiconductor wafers rises, leading to drift in their electrical parameters and reducing their lifespan. Therefore, selecting a suitable heat sink plays a crucial role in protecting power semiconductors. The thermal resistance parameter of a heat sink is a core indicator for measuring its heat dissipation capacity.

[0003] Currently, the main method for extracting the thermal impedance parameters of heat sinks is through finite element simulation. Specifically, a finite element simulation model is built using computer modeling, simulation boundary conditions are set, and finally, simulation is performed based on the simulation boundary conditions to obtain the thermal impedance parameters of the heat sink.

[0004] However, finite element simulation cannot perfectly and accurately simulate dynamic factors in real-world environments, such as the transient heating of power semiconductors. Therefore, the accuracy of the thermal impedance parameters of heat sinks obtained through finite element simulation is relatively low. Summary of the Invention

[0005] This application provides a method for extracting thermal impedance parameters, a method for obtaining wafer temperature, an apparatus, and a device, aiming to solve the technical problem of low accuracy of thermal impedance parameters of heat sinks obtained through finite element simulation.

[0006] In a first aspect, embodiments of this application provide a method for extracting thermal impedance parameters. The automatic control system includes a target heat sink and a target power semiconductor. The target heat sink is used to dissipate heat from the target power semiconductor and includes:

[0007] Construct a finite element simulation model of the automatic control system;

[0008] Construct a hardware-in-the-loop simulation model of the automatic control system;

[0009] The simulation conditions of the hardware-in-the-loop simulation model are set, wherein the case temperature of the target power semiconductor is set to a preset case temperature value.

[0010] Based on the simulation conditions, a hardware-in-the-loop simulation is performed using the hardware-in-the-loop simulation model to obtain first simulation data, which includes first loss data of the target power semiconductor.

[0011] The first loss data is input into the finite element simulation model, and finite element simulation is performed to obtain the second simulation data;

[0012] The thermal impedance parameters of the target heat sink are determined based on the first simulation data and the second simulation data.

[0013] Optionally, the second simulation data includes a first thermal impedance parameter of the target heat sink, and determining the thermal impedance parameter of the target heat sink based on the first simulation data and the second simulation data includes:

[0014] Determine whether the extraction of the thermal impedance parameters of the target heat sink has been completed based on the first simulation data and the second simulation data;

[0015] If so, the first thermal resistance parameter shall be used as the thermal resistance parameter of the target heat sink;

[0016] If not, input the first thermal impedance parameter into the hardware-in-the-loop simulation model and perform hardware-in-the-loop simulation to obtain third simulation data; the third simulation data includes the second loss data of the target power semiconductor; input the second loss data into the finite element simulation model and perform finite element simulation to obtain fourth simulation data; determine the thermal impedance parameter of the target heat sink based on the third simulation data and the fourth simulation data.

[0017] Optionally, the first simulation data further includes the first junction temperature and the first case temperature of the target power semiconductor, and the second simulation data further includes the second junction temperature and the second case temperature of the target power semiconductor. The step of determining whether the extraction of the thermal impedance parameters of the target heat sink has been completed based on the first simulation data and the second simulation data includes:

[0018] Calculate the difference between the first junction temperature and the second junction temperature to obtain the first difference;

[0019] Calculate the difference between the first shell temperature and the second shell temperature to obtain the second difference;

[0020] Based on the first difference and the second difference, it is determined whether the extraction of the thermal impedance parameters of the target heat sink has been completed.

[0021] Optionally, the construction of the finite element simulation model of the automatic control system includes:

[0022] A physical model of the target power semiconductor is constructed based on its junction-to-case thermal impedance parameters, wafer distribution diagram, and wafer size information.

[0023] The finite element simulation model is constructed based on the distribution status information of all heating power devices in the automatic control system, the material information of all heating power devices, and the physical model.

[0024] Optionally, the construction of the hardware-in-the-loop simulation model of the automatic control system includes:

[0025] The hardware-in-the-loop simulation model is built based on the datasheet of the target power semiconductor in the automatic control system and the electrical parameters of the automatic control system.

[0026] Secondly, this application also provides a method for obtaining wafer temperature. The automatic control system includes a target heat sink and a target power semiconductor. The target heat sink is used to dissipate heat from the target power semiconductor, including: obtaining the thermal resistance parameters of the target power semiconductor.

[0027] The thermal resistance parameters of the target heat sink are obtained by the method described in any of the first aspects;

[0028] A Foster thermal network model is constructed based on the thermal impedance parameters of the target power semiconductor and the target heat sink.

[0029] Obtain the loss data of the target power semiconductor;

[0030] The loss data is input into the Foster thermal network model to obtain the temperature change curve of the target power semiconductor.

[0031] Optionally, the thermal impedance parameters of the target power semiconductor include the junction-case thermal impedance parameters of the target power semiconductor, and the step of constructing a Foster thermal network model based on the thermal impedance parameters of the target power semiconductor and the thermal impedance parameters of the target heat sink includes:

[0032] Construct a shell thermal impedance network based on the aforementioned shell thermal impedance parameters;

[0033] Construct a thermal impedance network for the target heat sink based on its thermal impedance parameters.

[0034] The junction thermal impedance network is connected in series with the heat sink thermal impedance network to form the Foster thermal network model.

[0035] Optionally, obtaining the loss data of the target power semiconductor includes:

[0036] Construct a hardware-in-the-loop simulation model of the automatic control system;

[0037] The hardware-in-the-loop simulation model is used to perform hardware-in-the-loop simulation to obtain the loss data of the target power semiconductor.

[0038] Thirdly, embodiments of this application also provide a thermal impedance parameter extraction apparatus, which includes a unit for performing the above-described method.

[0039] Fourthly, embodiments of this application also provide a wafer temperature acquisition device, which includes a unit for performing the above-described method.

[0040] Fifthly, embodiments of this application also provide a computer device, which includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-described method.

[0041] Sixthly, embodiments of this application also provide a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the above-described method.

[0042] This application provides a method for extracting thermal impedance parameters, a method for obtaining wafer temperature, an apparatus, and a device. The automatic control system includes a target heat sink and a target power semiconductor. The target heat sink is used to dissipate heat from the target power semiconductor. The method includes: constructing a finite element simulation model of the automatic control system; constructing a hardware-in-the-loop simulation model of the automatic control system; setting simulation conditions for the hardware-in-the-loop simulation model, wherein the case temperature of the target power semiconductor is set to a preset case temperature value; performing hardware-in-the-loop simulation using the hardware-in-the-loop simulation model according to the simulation conditions to obtain first simulation data, the first simulation data including first loss data of the target power semiconductor; inputting the first loss data into the finite element simulation model and performing finite element simulation to obtain second simulation data; and determining the thermal impedance parameters of the target heat sink based on the first simulation data and the second simulation data. Therefore, this application constructs a hardware-in-the-loop simulation model and performs hardware-in-the-loop simulation to obtain the first loss data of the target power semiconductor. Then, the first loss data is input into the finite element simulation model and performed finite element simulation to obtain the second simulation data; finally, the thermal impedance parameters of the target heat sink are determined based on the first simulation data and the second simulation data. Therefore, it can be seen that the first loss data is obtained through hardware-in-the-loop simulation, and the first loss data can truly reflect the transient heating state of the target power semiconductor, thus making the thermal impedance parameters of the target heat sink obtained through finite element simulation highly accurate. Attached Figure Description

[0043] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0046] Figure 1a This is one of the flowcharts illustrating a method for extracting thermal impedance parameters provided in an embodiment of this application;

[0047] Figure 1b A schematic diagram of the finite element simulation model of a 5.5KW frequency converter system provided for an embodiment of this application;

[0048] Figure 2 A second schematic flowchart illustrating a method for extracting thermal impedance parameters provided in this application embodiment;

[0049] Figure 3 A schematic flowchart illustrating a method for obtaining wafer temperature provided in an embodiment of this application;

[0050] Figure 4a A schematic diagram of the structure of a Foster thermal network model provided in an embodiment of this application;

[0051] Figure 4b A comparison chart of power semiconductor wafer temperature profiles provided for embodiments of this application;

[0052] Figure 5 A schematic block diagram of a thermal impedance parameter extraction device provided in an embodiment of this application;

[0053] Figure 6 A schematic block diagram of a wafer temperature acquisition device provided in an embodiment of this application;

[0054] Figure 7 A computer device provided in an embodiment of this application. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0056] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0057] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0058] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0059] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0060] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrases "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0061] To address the issue of low accuracy in the thermal impedance parameters of heat sinks obtained through finite element simulation in existing technologies, this application provides a thermal impedance parameter extraction device that can improve the accuracy of thermal impedance parameters of heat sinks obtained through finite element simulation.

[0062] Figure 1a This is one of the flowcharts illustrating a method for extracting thermal impedance parameters provided in this application. In one embodiment, the automatic control system includes a target heat sink and a target power semiconductor, wherein the target heat sink is used to dissipate heat from the target power semiconductor, and the method includes:

[0063] S1. Build a finite element simulation model of the automatic control system.

[0064] In one embodiment, constructing the finite element simulation model of the automatic control system includes:

[0065] S11. Build a physical model of the target power semiconductor based on its junction-to-case thermal impedance parameters, wafer distribution diagram, and wafer size information.

[0066] In this embodiment, junction-to-shell thermal impedance parameters, wafer distribution diagrams, and wafer size information can be obtained from the datasheet of the target power semiconductor.

[0067] The embodiments of this application can use simulation tools to build a physical model of the target power semiconductor.

[0068] S12. Based on the distribution status information of all heating power devices in the automatic control system, the material information of all heating power devices, and the physical model, build a finite element simulation model.

[0069] The distribution status information includes, but is not limited to, the location information, electrical connection method, and mechanical connection method of the heating power devices in the automatic control system. Material information includes, but is not limited to, the core functional material information of the heating power devices. Heating power devices include, but are not limited to, resistors, capacitors, IGBTs, and field-effect transistors. It should be noted that the material information of the components can be obtained from the component datasheets in this application's embodiments. For example, when the automatic control system is a 5.5kW frequency converter system, such as... Figure 1b As shown, Figure 1b This is a schematic diagram of the finite element simulation model of a 5.5KW frequency converter system provided in this application embodiment.

[0070] S2. Build a semi-physical simulation model of the automatic control system.

[0071] In one embodiment, the construction of the hardware-in-the-loop simulation model of the automatic control system includes:

[0072] S21. Based on the datasheet of the target power semiconductor in the automatic control system and the electrical parameters of the automatic control system, build a hardware-in-the-loop simulation model.

[0073] The electrical parameters of the automatic control system include, but are not limited to, output voltage, output current, and rated power.

[0074] S3. Set the simulation conditions for the hardware-in-the-loop simulation model.

[0075] The simulation conditions involve setting the case temperature of the target power semiconductor to a preset case temperature value. This preset case temperature value was obtained by the applicant based on empirical data. Different automatic control systems correspond to different preset case temperature values. For example, when the automatic control system is a 5.5kW frequency converter system, the preset case temperature value is 85℃.

[0076] S4. Based on the simulation conditions, perform a hardware-in-the-loop simulation using a hardware-in-the-loop simulation model to obtain the first simulation data.

[0077] The first simulation data includes the first loss data of the target power semiconductor. This first loss data includes switching losses and conduction losses. Switching losses include turn-on losses and turn-off losses.

[0078] It should be noted that there is no fixed execution order between S1 and S2-S4. For example, S2 can be executed first, followed by S1, or S3 can be executed first, followed by S1. This application does not impose any restrictions on this.

[0079] S5. Input the first loss data into the finite element simulation model and perform finite element simulation to obtain the second simulation data.

[0080] It should be noted that, under ambient temperature, the first loss data is input into the finite element simulation model and simulation is performed to obtain the second simulation data.

[0081] S6. Determine the thermal impedance parameters of the target heat sink based on the first simulation data and the second simulation data.

[0082] The thermal impedance parameters of the target heat sink are obtained through hardware-in-the-loop simulation and finite element simulation in this embodiment.

[0083] This application provides a method for extracting thermal impedance parameters. The automatic control system includes a target heat sink and a target power semiconductor. The target heat sink is used to dissipate heat from the target power semiconductor. The method includes: constructing a finite element simulation model of the automatic control system; constructing a hardware-in-the-loop simulation model of the automatic control system; setting simulation conditions for the hardware-in-the-loop simulation model, wherein the case temperature of the target power semiconductor is set to a preset case temperature value; performing hardware-in-the-loop simulation using the hardware-in-the-loop simulation model according to the simulation conditions to obtain first simulation data, the first simulation data including first loss data of the target power semiconductor; inputting the first loss data into the finite element simulation model and performing finite element simulation to obtain second simulation data; and determining the thermal impedance parameters of the target heat sink based on the first simulation data and the second simulation data. Therefore, this application constructs a hardware-in-the-loop simulation model and performs hardware-in-the-loop simulation to obtain the first loss data of the target power semiconductor. Then, the first loss data is input into the finite element simulation model and performed finite element simulation to obtain the second simulation data; finally, the thermal impedance parameters of the target heat sink are determined based on the first simulation data and the second simulation data. Therefore, it can be seen that the first loss data is obtained through hardware-in-the-loop simulation, and the first loss data can truly reflect the transient heating state of the target power semiconductor, thus making the thermal impedance parameters of the target heat sink obtained through finite element simulation highly accurate.

[0084] Please see Figure 2 , Figure 2 This is a second schematic flowchart illustrating a method for extracting thermal impedance parameters provided in this application. In one embodiment, the second simulation data includes a first thermal impedance parameter of the target heat sink, and determining the thermal impedance parameter of the target heat sink based on the first simulation data and the second simulation data includes:

[0085] S61. Determine whether the extraction of thermal impedance parameters of the target heat sink has been completed based on the first simulation data and the second simulation data; if yes, execute S62; otherwise, execute S63-S65.

[0086] In one embodiment, the first simulation data further includes the first junction temperature and the first case temperature of the target power semiconductor, and the second simulation data further includes the second junction temperature and the second case temperature of the target power semiconductor. The step of determining whether the extraction of the thermal impedance parameters of the target heat sink has been completed based on the first simulation data and the second simulation data includes:

[0087] S611. Calculate the difference between the first junction temperature and the second junction temperature to obtain the first difference.

[0088] For example, if the first junction temperature is 89℃ and the second junction temperature is 87℃, then the first difference is 2℃.

[0089] S612. Calculate the difference between the first shell temperature and the second shell temperature to obtain the second difference.

[0090] For example, if the first shell temperature is 95℃ and the second shell temperature is 90℃, then the second difference is 5℃.

[0091] It should be noted that you can execute S612 first, and then execute S611.

[0092] S613. Determine whether the extraction of the thermal impedance parameters of the target heat sink has been completed based on the first difference and the second difference.

[0093] Specifically, it is determined whether the first difference is within a first preset range. If so, it is determined whether the second difference is within a second preset range. If so, the extraction of the thermal impedance parameters of the target heat sink is completed. The first and second preset ranges are obtained by the applicant based on experimental experience. For example, the first preset range can be (0-1)℃, and the second preset range can be (0, 2.2)℃. The extraction of the thermal impedance parameters of the target heat sink is completed only when both the first and second differences are within the first and second preset ranges.

[0094] S62. Use the first thermal resistance parameter as the thermal resistance parameter of the target heat sink.

[0095] Specifically, when the thermal impedance parameters of the target heat sink are extracted, the first impedance parameter is used as the thermal impedance parameter of the target heat sink.

[0096] S63. Input the first thermal impedance parameter into the hardware-in-the-loop simulation model and perform hardware-in-the-loop simulation to obtain the third simulation data.

[0097] In this process, when the thermal impedance parameters of the target heat sink are not extracted, the first thermal impedance parameters are input into the hardware-in-the-loop simulation model and a hardware-in-the-loop simulation is performed to obtain the third simulation data. The third simulation data includes the second loss data of the target power semiconductor. The third simulation data is identical to the first simulation data. Further details are omitted here.

[0098] S64. Input the second loss data into the finite element simulation model and perform finite element simulation to obtain the fourth simulation data.

[0099] The second loss data is the same as the first loss data, and the fourth simulation data is the same as the second simulation data. Further details will not be elaborated upon here.

[0100] S65. Determine the thermal impedance parameters of the target heat sink based on the third and fourth simulation data.

[0101] S65 is the same as S6. This application will not repeat it here.

[0102] It should be noted that S63-S65 can be executed once or multiple times. The extraction of the thermal impedance parameters of the target heat sink is only completed when the first difference is within the first preset range and the second difference is within the second preset range. At this point, the execution of S63-S65 ends.

[0103] Please see Figure 3 , Figure 3 This is a flowchart illustrating a method for acquiring wafer temperature according to an embodiment of this application. In one embodiment, the method is applied to an automatic control system, which includes a target heat sink and a target power semiconductor. The target heat sink is used to dissipate heat from the target power semiconductor, including:

[0104] S301. Obtain the thermal impedance parameters of the target power semiconductor.

[0105] The thermal impedance parameters of the target power semiconductor can be obtained from the datasheet of the target power semiconductor.

[0106] S302. Obtain the thermal resistance parameters of the target heat sink.

[0107] The thermal impedance parameters of the target heat sink are obtained using any of the thermal impedance parameter extraction methods described above. Further details are omitted here.

[0108] It should be noted that S302 can be executed first, followed by S301.

[0109] S303. Construct the Foster thermal network model based on the thermal impedance parameters of the target power semiconductor and the target heat sink.

[0110] like Figure 4a As shown, Figure 4a This is a schematic diagram of a Foster thermal network model provided in an embodiment of this application. In one embodiment, the thermal impedance parameter of the target power semiconductor includes the junction-case thermal impedance parameter of the target power semiconductor. The step of constructing the Foster thermal network model based on the thermal impedance parameters of the target power semiconductor and the thermal impedance parameters of the target heat sink includes:

[0111] S3031. Construct a junction thermal resistance network based on the junction thermal resistance parameters.

[0112] S3032. Construct a thermal impedance network for the target heat sink based on its thermal impedance parameters.

[0113] It should be noted that S3031 can be executed first, followed by S3032.

[0114] S3033. Connect the junction thermal resistance network and the heat sink thermal resistance network in series to form the Foster thermal network model.

[0115] The following is a detailed introduction to S3031-S3033.

[0116] The embodiments of this application can obtain the junction-case thermal impedance parameters from the datasheet of the target power semiconductor. The junction-case thermal impedance network consists of resistors and capacitors. The heat sink thermal impedance network also consists of resistors and capacitors. Finally, the junction-case thermal impedance network and the heat sink thermal impedance network are connected in series to form the Foster thermal network model.

[0117] S304. Obtain the loss data of the target power semiconductor.

[0118] Loss data includes: switching losses and conduction losses. Switching losses include turn-on losses and turn-off losses.

[0119] In one embodiment, acquiring the loss data of the target power semiconductor includes:

[0120] S3041. Construct a semi-physical simulation model of the automatic control system;

[0121] S3042. Use a hardware-in-the-loop simulation model to perform hardware-in-the-loop simulation and obtain the loss data of the target power semiconductor.

[0122] It should be noted that S3041 and S3042 will be described in detail below.

[0123] This application embodiment obtains the loss data of the target power semiconductor by building a hardware-in-the-loop (HIL) simulation model and performing HIL simulation. For example, when the automatic control system is a 5.5kW frequency converter system, it takes approximately 6 minutes for the chip of the power module of the 5.5kW frequency converter to change from ambient temperature to a stable temperature. Therefore, the HIL simulation is run for 6-7 minutes, and the loss data of the target power semiconductor is exported.

[0124] It should be noted that there is no fixed execution order between S304 and S301-S303. For example, S304 can be executed first, followed by S301.

[0125] S305. Input the loss data into the Foster thermal network model to obtain the temperature change curve of the target power semiconductor.

[0126] The loss data refers to the heat source power. In this embodiment, the multilayer structure of the target power semiconductor is abstracted as a parallel combination of thermal resistance-thermal capacitance network units. Next, this embodiment establishes thermal resistance-thermal capacitance equivalent circuits based on the thermal resistance-thermal capacitance network units. Finally, this embodiment applies a thermal balance equation to each thermal capacitance equivalent circuit to calculate the wafer temperature of the target power semiconductor.

[0127] Please see Figure 4b , Figure 4b This is a comparison chart of power semiconductor wafer temperature curves provided in the embodiments of this application. The Foster thermal network model is built based on the thermal impedance parameters of the target heat sink, which are obtained through any of the aforementioned thermal impedance parameter extraction methods. Therefore, the Foster network model built based on the thermal impedance parameters of the target heat sink more accurately reflects the actual operating conditions of the target power semiconductor, thus making the target power semiconductor wafer temperature obtained through this Foster network model closer to the measured wafer temperature of the target power semiconductor.

[0128] This application provides a method for obtaining wafer temperature. The automatic control system includes a target heat sink and a target power semiconductor. The target heat sink is used to dissipate heat from the target power semiconductor. The method includes: obtaining the thermal impedance parameters of the target power semiconductor; obtaining the thermal impedance parameters of the target heat sink, wherein the thermal impedance parameters of the target heat sink are obtained using any of the thermal impedance parameter extraction methods described above; constructing a Foster thermal network model based on the thermal impedance parameters of the target power semiconductor and the target heat sink; obtaining loss data of the target power semiconductor; and inputting the loss data into the Foster thermal network model to obtain a temperature change curve of the target power semiconductor. Therefore, the thermal impedance parameters of the target heat sink are obtained using any of the thermal impedance parameter extraction methods described above. Thus, the Foster network model constructed based on the thermal impedance parameters of the target heat sink more accurately reflects the actual operating conditions of the target power semiconductor, resulting in higher accuracy of the wafer temperature of the target power semiconductor obtained through this Foster network model.

[0129] See Figure 5 , Figure 5 This is a schematic block diagram of a thermal impedance parameter extraction device provided in an embodiment of this application. Corresponding to the above thermal impedance parameter extraction method, this application also provides a thermal impedance parameter extraction device. This thermal impedance parameter extraction device includes a unit for performing the above thermal impedance parameter extraction method, and can be configured in a desktop computer, tablet computer, laptop computer, or other terminal. Specifically, the automatic control system includes a target heat sink and a target power semiconductor, the target heat sink being used to dissipate heat from the target power semiconductor, and the device includes:

[0130] The first construction unit 501 is used to build the finite element simulation model of the automatic control system;

[0131] The second construction unit 502 is used to build a semi-physical simulation model of the automatic control system;

[0132] Setting unit 503 is used to set the simulation conditions of the semi-physical simulation model, wherein the simulation conditions are to set the case temperature of the target power semiconductor to a preset case temperature value.

[0133] The first simulation unit 504 is used to perform a hardware-in-the-loop simulation using the hardware-in-the-loop simulation model according to the simulation conditions, and obtain first simulation data, wherein the first simulation data includes the first loss data of the target power semiconductor.

[0134] The second simulation unit 505 is used to input the first loss data into the finite element simulation model and perform finite element simulation to obtain the second simulation data.

[0135] The determining unit 506 is used to determine the thermal impedance parameters of the target heat sink based on the first simulation data and the second simulation data.

[0136] In one embodiment, the second simulation data includes a first thermal impedance parameter of the target heat sink, and the determining unit 506 is specifically used to determine whether the extraction of the thermal impedance parameter of the target heat sink has been completed based on the first simulation data and the second simulation data;

[0137] If so, the first thermal resistance parameter shall be used as the thermal resistance parameter of the target heat sink;

[0138] If not, input the first thermal impedance parameter into the hardware-in-the-loop simulation model and perform hardware-in-the-loop simulation to obtain third simulation data; the third simulation data includes the second loss data of the target power semiconductor; input the second loss data into the finite element simulation model and perform finite element simulation to obtain fourth simulation data; determine the thermal impedance parameter of the target heat sink based on the third simulation data and the fourth simulation data.

[0139] In one embodiment, the first simulation data further includes the first junction temperature and the first case temperature of the target power semiconductor, and the second simulation data further includes the second junction temperature and the second case temperature of the target power semiconductor. The determining unit 506 is specifically used to calculate the difference between the first junction temperature and the second junction temperature to obtain a first difference.

[0140] Calculate the difference between the first shell temperature and the second shell temperature to obtain the second difference;

[0141] Based on the first difference and the second difference, it is determined whether the extraction of the thermal impedance parameters of the target heat sink has been completed.

[0142] In one embodiment, the first building unit 501 is specifically used to build a physical model of the target power semiconductor based on the junction-case thermal impedance parameters, wafer distribution pattern and wafer size information of the target power semiconductor;

[0143] The finite element simulation model is constructed based on the distribution status information of all heating power devices in the automatic control system, the material information of all heating power devices, and the physical model.

[0144] In one embodiment, the second building unit 502 is specifically used to build the hardware-in-the-loop simulation model based on the datasheet of the target power semiconductor in the automatic control system and the electrical parameters of the automatic control system.

[0145] See Figure 6 , Figure 6 This is a schematic block diagram of a wafer temperature acquisition device provided in an embodiment of this application. Corresponding to the above wafer temperature acquisition method, this application also provides a wafer temperature acquisition device. The wafer temperature acquisition device includes a unit for performing the above wafer temperature acquisition method, and the wafer temperature acquisition device can be configured in a desktop computer, tablet computer, laptop computer, or other terminal. Specifically, the wafer temperature acquisition device includes:

[0146] The first acquisition unit 601 is used to acquire the thermal impedance parameters of the target power semiconductor.

[0147] The second acquisition unit 602 is used to acquire the thermal impedance parameters of the target heat sink, wherein the thermal impedance parameters of the target heat sink are obtained by the thermal impedance parameter extraction method described in any of the above aspects.

[0148] The third building unit 603 is used to build a Foster thermal network model based on the thermal impedance parameters of the target power semiconductor and the thermal impedance parameters of the target heat sink.

[0149] The third acquisition unit 604 is used to acquire the loss data of the target power semiconductor;

[0150] The input unit 605 is used to input the loss data into the Foster thermal network model to obtain the temperature change curve of the target power semiconductor.

[0151] In one embodiment, the thermal impedance parameter of the target power semiconductor includes the junction-case thermal impedance parameter of the target power semiconductor, and the third building unit 603 is specifically used to build a junction-case thermal impedance network according to the junction-case thermal impedance parameter.

[0152] Construct a thermal impedance network for the target heat sink based on its thermal impedance parameters.

[0153] The junction thermal impedance network is connected in series with the heat sink thermal impedance network to form the Foster thermal network model.

[0154] In one embodiment, the third acquisition unit 604 is specifically used to build a semi-physical simulation model of the automatic control system;

[0155] The hardware-in-the-loop simulation model is used to perform hardware-in-the-loop simulation to obtain the loss data of the target power semiconductor.

[0156] like Figure 7 As shown, this application provides a computer device including a processor 71, a communication interface 72, a memory 73, and a communication bus 74. The processor 71, the communication interface 72, and the memory 73 communicate with each other through the communication bus 74. The memory 73 is used to store computer programs.

[0157] In one embodiment of this application, when the processor 71 executes the program stored in the memory 73, it implements a thermal impedance parameter extraction method or a wafer temperature acquisition method provided in any of the foregoing method embodiments.

[0158] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program may be stored in a storage medium, which is a computer-readable storage medium. The computer program is executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0159] Therefore, embodiments of this application also provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of a thermal impedance parameter extraction method or a wafer temperature acquisition method as provided in any of the foregoing method embodiments.

[0160] The storage medium is a physical, non-transient storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), magnetic disk, or optical disk, or any other physical storage medium capable of storing program code. The computer-readable storage medium can be non-volatile or volatile.

[0161] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0162] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0163] The steps in the methods of this application embodiment can be adjusted, merged, or deleted according to actual needs. The units in the apparatus of this application embodiment can be merged, divided, or deleted according to actual needs. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0164] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0165] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0166] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Since these modifications and variations fall within the scope of the claims and their equivalents, this application also intends to include these modifications and variations.

[0167] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for extracting thermal impedance parameters, characterized in that, The automatic control system includes a target heat sink and a target power semiconductor, wherein the target heat sink is used to dissipate heat from the target power semiconductor, and the method includes: Construct a finite element simulation model of the automatic control system; Construct a hardware-in-the-loop simulation model of the automatic control system; The simulation conditions of the hardware-in-the-loop simulation model are set, wherein the case temperature of the target power semiconductor is set to a preset case temperature value. Based on the simulation conditions, a hardware-in-the-loop simulation is performed using the hardware-in-the-loop simulation model to obtain first simulation data, which includes first loss data of the target power semiconductor. The first loss data is input into the finite element simulation model, and finite element simulation is performed to obtain the second simulation data; The thermal impedance parameters of the target heat sink are determined based on the first simulation data and the second simulation data.

2. The method according to claim 1, characterized in that, The second simulation data includes a first thermal impedance parameter of the target heat sink. Determining the thermal impedance parameter of the target heat sink based on the first simulation data and the second simulation data includes: Determine whether the extraction of the thermal impedance parameters of the target heat sink has been completed based on the first simulation data and the second simulation data; If so, the first thermal resistance parameter shall be used as the thermal resistance parameter of the target heat sink; If not, input the first thermal impedance parameter into the hardware-in-the-loop simulation model and perform hardware-in-the-loop simulation to obtain third simulation data, the third simulation data including the second loss data of the target power semiconductor; input the second loss data into the finite element simulation model and perform finite element simulation to obtain fourth simulation data; determine the thermal impedance parameter of the target heat sink based on the third simulation data and the fourth simulation data.

3. The method according to claim 1 or 2, characterized in that, The first simulation data also includes the first junction temperature and the first case temperature of the target power semiconductor, and the second simulation data also includes the second junction temperature and the second case temperature of the target power semiconductor. The step of determining whether the extraction of the thermal impedance parameters of the target heat sink has been completed based on the first simulation data and the second simulation data includes: Calculate the difference between the first junction temperature and the second junction temperature to obtain the first difference; Calculate the difference between the first shell temperature and the second shell temperature to obtain the second difference; Based on the first difference and the second difference, it is determined whether the extraction of the thermal impedance parameters of the target heat sink has been completed.

4. The method according to claim 1 or 2, characterized in that, The construction of the finite element simulation model of the automatic control system includes: A physical model of the target power semiconductor is constructed based on its junction-to-case thermal impedance parameters, wafer distribution diagram, and wafer size information. The finite element simulation model is constructed based on the distribution status information of all heating power devices in the automatic control system, the material information of all heating power devices, and the physical model.

5. The method according to claim 1 or 2, characterized in that, The construction of the hardware-in-the-loop simulation model of the automatic control system includes: The hardware-in-the-loop simulation model is built based on the datasheet of the target power semiconductor in the automatic control system and the electrical parameters of the automatic control system.

6. A method for obtaining wafer temperature, characterized in that, The automatic control system includes a target heat sink and a target power semiconductor, wherein the target heat sink is used to dissipate heat from the target power semiconductor, including: Obtain the thermal impedance parameters of the target power semiconductor; The thermal resistance parameters of the target heat sink are obtained by the method described in any one of claims 1 to 5; A Foster thermal network model is constructed based on the thermal impedance parameters of the target power semiconductor and the target heat sink. Obtain the loss data of the target power semiconductor; The loss data is input into the Foster thermal network model to obtain the temperature change curve of the target power semiconductor.

7. The method according to claim 6, characterized in that, The thermal impedance parameters of the target power semiconductor include the junction-case thermal impedance parameters of the target power semiconductor. The step of constructing a Foster thermal network model based on the thermal impedance parameters of the target power semiconductor and the thermal impedance parameters of the target heat sink includes: Construct a shell thermal impedance network based on the aforementioned shell thermal impedance parameters; Construct a thermal impedance network for the target heat sink based on its thermal impedance parameters. The junction thermal impedance network is connected in series with the heat sink thermal impedance network to form the Foster thermal network model.

8. The method according to claim 6 or 7, characterized in that, The step of acquiring the loss data of the target power semiconductor includes: Construct a hardware-in-the-loop simulation model of the automatic control system; The hardware-in-the-loop simulation model is used to perform hardware-in-the-loop simulation to obtain the loss data of the target power semiconductor.

9. A thermal impedance parameter extraction device, characterized in that, The automatic control system includes a target heat sink and a target power semiconductor, wherein the target heat sink is used to dissipate heat from the target power semiconductor, and the device includes: The first construction unit is used to build the finite element simulation model of the automatic control system; The second construction unit is used to build a semi-physical simulation model of the automatic control system; The setting unit is used to set the simulation conditions of the hardware-in-the-loop simulation model, wherein the simulation conditions are to set the case temperature of the target power semiconductor to a preset case temperature value. The first simulation unit is used to perform a hardware-in-the-loop simulation using the hardware-in-the-loop simulation model according to the simulation conditions, and to obtain first simulation data, wherein the first simulation data includes the first loss data of the target power semiconductor. The second simulation unit is used to input the first loss data into the finite element simulation model and perform finite element simulation to obtain the second simulation data. The determining unit is used to determine the thermal impedance parameters of the target heat sink based on the first simulation data and the second simulation data.

10. A computer device, characterized in that, The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method as described in any one of claims 1 to 8.

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