Display panel and driving method thereof

Abstract

The invention provides a display panel and a driving method thereof, the display panel comprises a voltage detector and a time schedule controller, the voltage detector is used for generating a control signal according to a magnitude relationship between a to-be-detected voltage signal and a preset value, the to-be-detected voltage signal is used for driving a source driver to transmit a working voltage of a data signal to a plurality of sub-pixels, and the to-be-detected voltage signal is used for driving a plurality of sub-pixels. The time schedule controller is used for controlling whether the source electrode driver outputs the data signal or not according to the control signal, so that the blank screen phenomenon caused by the fact that the to-be-detected voltage signal is subjected to large current pumping when the value of the to-be-detected voltage signal does not reach the preset value during startup is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to the manufacturing of display device, and more particularly to a display panel and a driving method thereof. BACKGROUND

[0002] With the development of display technology, the visibility and information amount of large-size display panel meet the larger needs of users.

[0003] Among them, with the increase of panel size, the current generated by the analog voltage required to drive the panel to work also increases. In the stage of starting the PMIC (Power Management IC, power management chip), if the initial stage of generating the above-mentioned analog voltage continuously provides a larger current to the panel, it will cause the boost of the above-mentioned analog voltage to not reach the set target voltage, and the PMIC will start the UVP (Under Voltage Protection, under voltage protection) protection when it detects that the above-mentioned analog voltage is in low voltage for a long time, which will cause the panel to display black screen.

[0004] Therefore, the existing large-size display panel has a black screen phenomenon when starting, which needs to be improved. SUMMARY

[0005] The purpose of the present application is to provide a display panel and a driving method thereof to improve the black screen phenomenon of large-size display panel when starting.

[0006] The present application provides a display panel, comprising:

[0007] a panel body comprising a plurality of sub-pixels;

[0008] a source driver electrically connected to the panel body and configured to transmit a data signal to the plurality of sub-pixels;

[0009] a voltage detector configured to obtain a to-be-detected voltage signal and generate a control signal according to the to-be-detected voltage signal, wherein the to-be-detected voltage signal is used to provide a working voltage to the source driver so that the source driver transmits the data signal to the plurality of sub-pixels;

[0010] a timing controller electrically connected between the voltage detector and the source driver and configured to control whether the source driver outputs the data signal according to the control signal, so as to control whether the value of the to-be-detected voltage signal rises.

[0011] In some embodiments, the voltage detector is configured to control the value of the control signal to be a first value when the value of the to-be-detected voltage signal is greater than or equal to a preset value, and the first value is used to control the source driver to output the data signal.

[0012] The voltage detector is configured to control the control signal to have a second value when the value of the voltage to be detected is less than the preset value, the second value being configured to control the source driver to not output the data signal so as to increase the value of the voltage to be detected.

[0013] In some embodiments, the timing controller is configured to generate a data latch signal according to the control signal, and the source driver is configured to control whether to output the data signal according to a value of the data latch signal.

[0014] In some embodiments, further comprising:

[0015] A power manager configured to transmit a first voltage signal to the timing controller, the first voltage signal being configured to drive the timing controller to generate the data latch signal.

[0016] In some embodiments, the power manager is further electrically connected to the source driver and configured to transmit the voltage to be detected to the source driver, and the voltage detector is electrically connected to the power manager or the source driver to obtain the voltage to be detected.

[0017] In some embodiments, the voltage detector comprises:

[0018] A first input terminal configured to load the voltage to be detected;

[0019] A second input terminal configured to load a second voltage signal;

[0020] An output terminal electrically connected to the timing controller and configured to output the control signal;

[0021] The voltage detector is configured to generate the control signal according to the voltage to be detected and the second voltage signal.

[0022] In some embodiments, the voltage detector comprises:

[0023] An input unit comprising a first resistor, a second resistor and a first node, the first resistor being electrically connected between the first input terminal and the first node, and the second resistor being electrically connected between a ground and the first node;

[0024] An output unit comprising a third resistor, a switching element and a second node, the third resistor being electrically connected between the second input terminal and the second node, a control terminal of the switching element being electrically connected to the first node, a first terminal of the switching element being electrically connected to the second node, and a second terminal of the switching element being electrically connected to the ground.

[0025] The application further provides a driving method of the display panel, comprising:

[0026] obtaining a to-be-detected voltage signal, and generating a control signal according to the to-be-detected voltage signal, the to-be-detected voltage signal being used to provide a working voltage to a source driver so that the source driver transmits a data signal to a plurality of sub-pixels;

[0027] controlling whether the source driver outputs the data signal according to the control signal, so as to control whether the value of the to-be-detected voltage signal rises.

[0028] In some embodiments, the step of generating the control signal according to the to-be-detected voltage signal comprises:

[0029] judging whether the value of the to-be-detected voltage signal is greater than or equal to a preset value;

[0030] if the value of the to-be-detected voltage signal is greater than or equal to the preset value, controlling the value of the generated control signal to be a first value;

[0031] if the value of the to-be-detected voltage signal is less than the preset value, controlling the value of the generated control signal to be a second value;

[0032] the step of controlling whether the source driver outputs the data signal according to the control signal, so as to control whether the value of the to-be-detected voltage signal rises, comprises:

[0033] judging whether the value of the control signal is the first value;

[0034] if the value of the control signal is the first value, controlling the source driver to output the data signal, so as to control the value of the to-be-detected voltage signal to rise;

[0035] judging whether the value of the control signal is the second value;

[0036] if the value of the control signal is the second value, controlling the source driver not to output the data signal, so as to control the value of the to-be-detected voltage signal to rise.

[0037] In some embodiments, the step of controlling the source driver to output the data signal comprises:

[0038] controlling the value of a generated latch signal to be a third value, so as to control the source driver to output the data signal;

[0039] the step of controlling the source driver not to output the data signal comprises:

[0040] The value of the generated latch signal is controlled to be a fourth value to control the source driver to not output the data signal.

[0041] The present application provides a display panel and a driving method thereof. A voltage detector is arranged to generate a control signal according to a voltage signal to be detected, which is used to drive the source driver to transmit the data signal to the plurality of sub-pixels. A timing controller is arranged to be electrically connected between the voltage detector and the source driver, and is used to control the source driver to output or not to output the data signal according to the control signal, so as to control whether the value of the voltage signal to be detected is increased, thereby avoiding the phenomenon of black screen caused by drawing a large current from the voltage signal to be detected when the value of the voltage signal to be detected does not reach a preset value at the start of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0042] The present application will be further described below with reference to the drawings. It is noted that the drawings described below are only used to explain some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts on the basis of the drawings.

[0043] Figure 1 and Figure 2 The architecture diagram of the display panel provided by the embodiment of the present application.

[0044] Figure 3 The waveform diagram of part of the signals of the display panel provided by the embodiment of the present application.

[0045] Figures 4 to 7 The flowchart of the driving method of the display panel provided by the embodiment of the present application. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0047] In the description of the present application, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In addition, it should be noted that the drawings provided are only relatively close to the structures of the present application, some details not closely related to the application are omitted, the purpose is to simplify the drawings and make the application points clear, and not to indicate that the actual device is exactly the same as the drawings. Figure 1 The drawings are not intended to limit the actual device.

[0048] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The phrase appears at various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily independent or alternative embodiments to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0049] The present application provides a display panel, which can include but is not limited to the following embodiments and combinations of the following embodiments.

[0050] In some embodiments, in combination with Figure 1 and Figure 2 As shown in the figure, the display panel 100 includes: a panel body 10 including a plurality of sub-pixels P; a source driver 20 electrically connected to the panel body 10 for transmitting a data signal data to a plurality of the sub-pixels P; a voltage detector 30 for acquiring a to-be-detected voltage signal AVDD and generating a control signal AVDD_ready according to the size relationship between the to-be-detected voltage signal AVDD and a preset value, the to-be-detected voltage signal AVDD being used to provide a working voltage (the voltage value of which can be greater than or equal to the preset value) to the source driver 20 to make the source driver 20 transmit the data signal data to a plurality of the sub-pixels P; a timing controller 40 electrically connected between the voltage detector 30 and the source driver 20 for controlling whether the source driver 20 outputs the data signal data according to the control signal AVDD_ready.

[0051] Wherein, the display panel 100 can be but is not limited to an organic self-luminous display panel, an inorganic self-luminous direct-view display panel or a liquid crystal display panel, the display panel 100 can further include a gate driver 50, which can be a gate driving circuit located on the substrate of the above-mentioned panel body 10 or a chip (only the latter is exemplified in the figure) provided independently of the above-mentioned panel body 10, for the sake of description, Figure 1 The gate driver 50 can be a gate driving circuit located on the substrate of the above-mentioned panel body 10 or a chip (only the latter is exemplified in the figure) provided independently of the above-mentioned panel body 10, for the sake of description,Figure 1 For example, the sub-pixels P can be arranged in n rows and m columns (n and m are positive integers).

[0052] Specifically, the panel body 10 can further include a plurality of gate lines (GL1 to GLn) electrically connected to the gate driver 50 and a plurality of data lines (DL1 to DLm) electrically connected to the source driver 20. The gate driver 50 generates a plurality of gate signals gate corresponding to the plurality of rows of sub-pixels P, each of the gate lines (one of GL1 to GLn) is electrically connected to a corresponding row of sub-pixels P to transmit a corresponding gate signal gate to the corresponding row of sub-pixels P, each of the gate signals gate includes a gate active pulse for controlling the corresponding pixel group 201 to be turned on, and the plurality of gate active pulses are arranged in sequence on the time axis, so that the corresponding plurality of pixel groups 201 are turned on in sequence; each of the data lines (one of DL1 to DLm) is electrically connected to a corresponding column of sub-pixels P to transmit a corresponding data signal data generated by the source driver 20 to the corresponding column of sub-pixels P, each of the data signals data includes a plurality of data voltages corresponding to the plurality of sub-pixels P in the column, and the plurality of data signals data corresponding to the plurality of columns of sub-pixels P are matched so that when each of the pixel groups 201 is turned on, the plurality of data voltages corresponding to the plurality of sub-pixels P in the pixel group 201 can be transmitted to the corresponding plurality of sub-pixels P through the plurality of data lines (DL1 to DLm) respectively.

[0053] Further, as shown in Figure 1 and Figure 2 The display panel 100 further includes a power manager 60 electrically connected to the source driver 20 for transmitting the to-be-detected voltage signal AVDD to the source driver 20, and the voltage detector 30 is electrically connected to the power manager 60 or the source driver 20 for obtaining the to-be-detected voltage signal AVDD.

[0054] Specifically, the source driver 20 can include a buffer, and the to-be-detected voltage signal AVDD can be transmitted to the source driver 20 as the working voltage of the buffer, and the buffer in the working state can output a corresponding data signal data to a corresponding one of the data lines (DL1 to DLm) according to the signal (related to the data signal data) at the input end of the buffer, and the size of the to-be-detected voltage signal AVDD can affect the current size at the output end of the buffer.

[0055] It should be noted that when the display panel 100 is powered on, the to-be-detected voltage AVDD provided by the power manager 60 needs to be gradually increased to the target value so that the current at the output end of the buffer is large enough to better input the data signal data into the panel body 10. This process is called large-current extraction of the to-be-detected voltage signal AVDD. As a result, the amplitude of the to-be-detected voltage signal AVDD cannot be raised, and after the power manager 60 detects that the amplitude of the detection signal AVDD is low, the UVP is triggered so that the to-be-detected voltage signal AVDD is no longer output, causing the subsequent data signal data to be unable to be transmitted into the panel body 10, resulting in a black screen.

[0056] It can be understood that in the embodiment, the voltage detector 30 is electrically connected to the corresponding node or pin in the power manager 60 or the source driver 20 to obtain the to-be-detected voltage signal AVDD, and the control signal AVDD_ready generated accordingly is transmitted to the timing controller 40. The timing controller 40 can control whether the source driver 20 outputs the data signal data according to the control signal AVDD_ready, that is, control the size of the current required by the output end of the buffer in the current source driver 20, thereby controlling whether to “extract large current from the to-be-detected voltage signal AVDD” and whether the value of the to-be-detected voltage signal AVDD is not raised, avoiding the phenomenon of black screen caused by extracting large current from the to-be-detected voltage signal AVDD when the value of the to-be-detected voltage signal AVDD is low when powered on.

[0057] Specifically, in combination with the embodiments shown in Figure 1 and Figure 2 , the voltage detector 30 is configured to control the value of the control signal AVDD_ready to be a first value when the value of the to-be-detected voltage signal AVDD is greater than or equal to the preset value, and the first value is used to control the source driver 20 to work to output the data signal data (at this time, the value of the to-be-detected voltage signal AVDD can be unchanged, increased, or decreased); the voltage detector 30 is configured to control the value of the control signal AVDD_ready to be a second value when the value of the to-be-detected voltage signal AVDD is less than the preset value, and the second value is used to control the source driver 20 not to work to not output the data signal data.

[0058] Based on the above discussion, when the display panel 100 is powered on, the value of the voltage signal AVDD to be detected is considered to be less than the preset value. At this time, the voltage detector 30 can generate a control signal AVDD_ready with the second value, further controlling the source driver 20 not to output the data signal data. Therefore, it can avoid "draining a large current from the voltage signal AVDD to be detected", so the value of the voltage signal AVDD to be detected can continue to rise. Furthermore, when the value of the voltage signal AVDD to be detected rises to be greater than or equal to the preset value, the voltage detector 30 can generate a control signal AVDD_ready with the first value, further controlling the source driver 20 to output the data signal data. At this time, even if "draining a large current from the voltage signal AVDD to be detected", since the value of the voltage signal AVDD to be detected is already large enough, it can be considered that its value will not be less than the preset value again. Thus, the display panel 100 can display the image normally.

[0059] The aforementioned preset value can be greater than or equal to 80% of the maximum value of the voltage signal AVDD to be detected. Of course, it can also be set according to the fluctuation of the voltage signal AVDD to be detected when "a large current is drawn from the voltage signal AVDD to be detected" in the display panel 100.

[0060] In some embodiments, combined with Figures 1 to 3 As shown, the timing controller 40 is used to generate a data latch signal TP based on the control signal AVDD_ready, and the source driver 20 is used to control whether to output the data signal data based on the value of the data latch signal TP. Wherein, as Figure 3 As shown, the data latch signal TP can include multiple data latch pulses p. Each data latch pulse p can be used to control multiple buffers of the source driver 20 to transmit multiple corresponding data voltages (corresponding to multiple sub-pixels P in the same row) to multiple data lines respectively. Therefore, under the action of multiple data latch pulses p, multiple rows of sub-pixels P are sequentially loaded with the corresponding data voltages. That is, based on whether the value of the data latch signal TP is the amplitude of the data latch pulse p, the source driver 20 can be controlled to output data voltages.

[0061] Based on the above discussion, it can be assumed that the source driver 20 begins inputting the data signal data to the panel body 10 when the value of the data latch signal TP first reaches the amplitude of the data latch pulse p. Therefore, in this embodiment, the control signal AVDD_ready can be used to control the value of the generated data latch signal TP, thereby allowing the source driver 20 to control whether to output the data signal data based on the value of the data latch signal TP, and thus causing the value of the voltage signal AVDD to be detected to rise.

[0062] In some embodiments, combined withFigures 1 to 3 As shown, the power manager 60 is also configured to transmit a first voltage signal VDD to the timing controller 40, where the first voltage signal VDD is used to drive the timing controller 40 to generate the data latch signal TP. The first voltage signal VDD can include a first sub-voltage signal VDD1, a second sub-voltage signal VDD2 and a third sub-voltage signal VDD3, all of which can be constant voltage signals, and the amplitudes of the three sub-voltage signals can be 3.3V, 1.8V and 1.2V respectively. The data latch signal TP can be generated according to at least one of the three sub-voltage signals.

[0063] Of course, the power manager 60 can also transmit a half voltage signal HAVDD (if the display panel 100 is a liquid crystal display panel), a gamma voltage Gamma Voltage and the second sub-voltage signal VDD2 to the source driver 20. When the display panel 100 is a liquid crystal display panel, the half voltage signal HAVDD can be used as a common voltage, and the source driver 20 can generate a data voltage corresponding to each sub-pixel P according to the gray scale value of the sub-pixel P and the gamma voltage Gamma Voltage.

[0064] In combination with the above, under the action of the external input signal VIN, the power manager 60 can transmit the first voltage signal VDD (including but not limited to the first sub-voltage signal VDD1, the second sub-voltage signal VDD2 and the third sub-voltage signal VDD3) to the timing controller 40 to control its operation, and transmit the third voltage signal (including but not limited to the to-be-detected voltage signal AVDD, the half voltage signal HAVDD, the gamma voltage Gamma Voltage and the second sub-voltage signal VDD2) to the source driver 20 to control its operation.

[0065] In some embodiments, as shown, Figure 2 As shown, the voltage detector 30 includes a first input terminal configured to load the to-be-detected voltage signal AVDD, a second input terminal configured to load a second voltage signal (which can be the first sub-voltage signal VDD1 described above), and an output terminal electrically connected to the timing controller 40 and configured to output the control signal AVDD_ready. The voltage detector 30 is configured to generate the control signal AVDD_ready according to the to-be-detected voltage signal AVDD and the second voltage signal.

[0066] The value of the to-be-detected voltage signal AVDD and the value of the second voltage signal both affect the value of the generated control signal AVDD_ready. Here, the value of the second voltage signal is considered to be stable, so the value of the control signal AVDD_ready can be determined according to the value of the to-be-detected voltage signal AVDD, thereby playing a role in detecting the value of the to-be-detected voltage signal AVDD. In this embodiment, the amplitude of the second voltage signal is not limited, and the second voltage signal can also be a constant high voltage signal generated by the power manager 60 (as long as it can be detected as a logic high level by the timing controller 40). For example, the second voltage signal can be, but is not limited to, the first sub-voltage signal VDD1, the second sub-voltage signal VDD2, or the third sub-voltage signal VDD3.

[0067] Specifically, as shown in FIG. 3, the voltage detector 30 includes an input unit and an output unit. Figure 2 The input unit includes a first resistor R1, a second resistor R2, and a first node A. The first resistor R1 is electrically connected between the first input end and the first node A. The second resistor R2 is electrically connected between the ground and the first node A. The output unit includes a third resistor R3, a switch element Q1, and a second node B. The third resistor R3 is electrically connected between the second input end and the second node B. The control end of the switch element Q1 is electrically connected to the first node A. The first end of the switch element Q1 is electrically connected to the second node B. The second end of the switch element Q1 is electrically connected to the ground.

[0068] For ease of description, based on the above circuit connection mode, the switch element Q1 is taken as an example of an NMOS tube. The gate g of the NMOS tube can be electrically connected to the first node A. The source s of the NMOS tube can be grounded. The drain d of the NMOS tube can be electrically connected to the second node B. The resistances of the first resistor R1, the second resistor R2, and the third resistor R3 can be determined according to the functional requirements and settings of the voltage detector 30, in combination with FIG. 3. Figure 2 and Figure 3 As shown in FIG. 3, the following analysis can be made.

[0069] At the t1 moment when the display panel 100 is powered on, the first sub-voltage signal VDD1 and the second sub-voltage signal VDD2 generated by the power manager 60 can quickly reach the corresponding amplitudes. However, the value of the to-be-detected voltage signal AVDD is less than the preset value (for example, 80% of the maximum value of the to-be-detected voltage signal AVDD). It can be considered that the voltage of the first node A is small, causing the NMOS tube (switch element Q1) to be cut off. At this time, the second node B is electrically connected to the second input end (loaded with the second voltage signal) through the third resistor R3. Here, the second voltage signal is considered to be stable, so the value of the control signal AVDD_ready can be determined according to the value of the to-be-detected voltage signal AVDD, thereby playing a role in detecting the value of the to-be-detected voltage signal AVDD. Figure 2For example, when the second voltage signal is taken as the first sub-voltage signal VDD1, the value of the control signal AVDD_ready output to the timing controller 40 is large (i.e. the second value, for example, close to 3.3V), at this time, the timing controller 40 can recognize the high level, so that the data latch signal TP generated by the timing controller 40 is not in the data latch pulse p, so that the source driver 20 does not output the data signal data, so as not to draw large current from the to-be-detected voltage signal AVDD, so that the value of the to-be-detected voltage signal AVDD can continue to rise from the t2 moment after the t1 moment;

[0070] When the value of the to-be-detected voltage signal AVDD is greater than or equal to the preset value (for example, 80% of the maximum value of the to-be-detected voltage signal AVDD) at the t3 moment, it can be considered that the voltage of the first node A is large enough to make the NMOS tube (switching element Q1) conduct, at this time, the second node B is electrically connected to the ground through the switching element Q1, so that the value of the control signal AVDD_ready output to the timing controller 40 is small (i.e. the first value, for example, the logic low level), at this time, the data latch signal TP generated by the timing controller 40 is in the data latch pulse p, so that the source driver 20 outputs the data signal data, in the process of detecting the control signal AVDD_ready signal and controlling the source driver 20 to output, the to-be-detected voltage signal AVDD has been raised to the maximum value, at this time, even if the to-be-detected voltage signal AVDD is drawn large current, since the value of the to-be-detected voltage signal AVDD is large and stable enough, it can be considered that the value will not be less than the preset value again, at this time, the display panel 100 can display the picture normally.

[0071] In order to better illustrate the above display panel, the application further provides a driving method of the display panel, which can include but is not limited to the following embodiments and combinations of the following embodiments.

[0072] In some embodiments, as shown in Figure 4 The driving method of the display panel can include but is not limited to the following steps and combinations of the following steps.

[0073] S1, obtaining a to-be-detected voltage signal, and generating a control signal according to the size relationship between the to-be-detected voltage signal and a preset value, the to-be-detected voltage signal being used to provide a working voltage to a source driver so that the source driver transmits a data signal to a plurality of sub-pixels.

[0074] As discussed above, at the start of the display panel 100, the voltage to be detected AVDD provided by the power manager 60 needs to be gradually increased to the target value so that the current at the output end of the buffer is large enough to better input the data signal data into the panel body 10. This process is called drawing a large current on the voltage to be detected signal AVDD. As a result, the amplitude of the voltage to be detected signal AVDD cannot be increased, and after the power manager 60 detects that the amplitude of the detection signal AVDD is low, the UVP is triggered so that the voltage to be detected signal AVDD is no longer output. As a result, the subsequent data signal data cannot be transmitted into the panel body 10, resulting in a black screen.

[0075] In some embodiments, the execution subject of step S1 can be the voltage detector 30. The voltage detector 30 can be electrically connected to the power manager 60 or the source driver 20 to continuously obtain the voltage to be detected signal AVDD from the start of the power-on, and control the value of the control signal AVDD_ready generated by the voltage detector 30 in real time according to the value of the voltage to be detected signal AVDD.

[0076] The specific details of step S1 can be referred to the related description above.

[0077] S2, controlling whether the source driver outputs the data signal according to the control signal, to control whether the value of the voltage to be detected signal increases.

[0078] In some embodiments, the execution subject of step S2 can be the timing controller 40. The timing controller 40 can be electrically connected between the voltage detector 30 and the source driver 20, to control whether the value of the voltage to be detected signal AVDD increases in real time according to the value of the control signal AVDD_ready.

[0079] In some embodiments, as shown in FIG. 1, the step of “generating a control signal according to the voltage to be detected signal” in step S1 can include but is not limited to the following steps: Figure 5

[0080] S11, determining whether the value of the voltage to be detected signal is greater than or equal to the preset value;

[0081] If the value of the voltage to be detected signal is greater than or equal to the preset value, the following step is performed:

[0082] S12, controlling the value of the generated control signal to be a first value;

[0083] If the value of the voltage to be detected signal is less than the preset value, the following step is performed:

[0084] S13, controlling the value of the generated control signal to be a second value.

[0085] ​As discussed above, the execution subject of steps S11-S13 can be the voltage detector 30. The voltage detector 30 can control the value of the generated control signal AVDD_ready to be the first value or the second value according to the value of the to-be-detected voltage signal AVDD.

[0086] The specific details of steps S11-S13 can refer to the related description above.

[0087] Correspondingly, as shown in FIG. 2, step S2 can include but is not limited to the following steps: Figure 6

[0088] S21, determining whether the value of the control signal is the first value;

[0089] If the value of the control signal is the first value, execute:

[0090] S22, controlling the source driver to work to output the data signal;

[0091] If not, execute:

[0092] S23, determining whether the value of the control signal is the second value;

[0093] If the value of the control signal is the second value, execute:

[0094] S24, controlling the source driver not to work to not output the data signal, to control the value of the to-be-detected voltage signal to rise.

[0095] As discussed above, the execution subject of steps S21-S24 can be the timing controller 40. The timing controller 40 can be used to determine whether the value of the control signal AVDD_ready is the first value or the second value to control the source driver 20 to output or not to output the data signal data, thereby controlling whether the value of the to-be-detected voltage signal AVDD rises in real time.

[0096] The specific details of steps S21-S24 can refer to the related description above.

[0097] In some embodiments, as shown in FIG. 2, step S22 can include but is not limited to the following steps: Figure 7

[0098] S221, controlling the generated latch signal to be the third value, to control the source driver to work to not output the data signal;

[0099] Similarly, step S24 can include but is not limited to the following steps:

[0100] ​​S241, controlling the value of the generated latch signal to be a fourth value, to control the source driver to not work to not output the data signal, to control the value of the to-be-detected voltage signal to rise.

[0101] As discussed above, the execution subject of steps S221 and S241 can be the timing controller 40 described above, which can control the value of the latch signal TP generated by the timing controller 40 to be the third value or the fourth value in real time according to the value of the control signal AVDD_ready being the first value or the second value, and further control the source driver 20 to output or not output the data signal data, thereby controlling whether the value of the to-be-detected voltage signal AVDD rises in real time.

[0102] The specific details of steps S221 and S241 can refer to the related description above.

[0103] The present application provides a display panel and a driving method thereof, based on a source driver electrically connected to the panel main body for transmitting a data signal to a plurality of sub-pixels, a voltage detector is arranged to generate a control signal according to the to-be-detected voltage signal, the to-be-detected voltage signal is used to drive the source driver to transmit the data signal to a plurality of sub-pixels, and a timing controller is arranged to be electrically connected between the voltage detector and the source driver, for controlling whether the source driver outputs the data signal according to the control signal, to control whether the value of the to-be-detected voltage signal rises, thereby avoiding the phenomenon of black screen caused by drawing a large current on the to-be-detected voltage signal when the value of the to-be-detected voltage signal does not reach a preset value when starting up.

[0104] The display panel and the driving method thereof provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples in this paper, and the above description of the embodiments is only used to help understand the technical solutions and the core ideas of the present application; those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized by, The panel body comprises a plurality of sub-pixels. An electrode driver is electrically connected to the panel body and is configured to transmit a data signal to the plurality of sub-pixels. A voltage detector is configured to obtain a to-be-detected voltage signal and generate a control signal according to a size relationship between the to-be-detected voltage signal and a preset value, the to-be-detected voltage signal being configured to provide a working voltage for the electrode driver to transmit the data signal to the plurality of sub-pixels. A timing controller is electrically connected between the voltage detector and the electrode driver and is configured to control the electrode driver to output or not to output the data signal according to the control signal. When the to-be-detected voltage signal is greater than or equal to the preset value, the voltage detector is configured to control the control signal to have a first value, the first value being configured to control the electrode driver to work to output the data signal.

2. The display panel of claim 1, wherein, When the to-be-detected voltage signal is less than the preset value, the voltage detector is configured to control the control signal to have a second value, the second value being configured to control the electrode driver to not work to output the data signal. The timing controller is configured to generate a data latch signal according to the control signal, and the electrode driver is configured to control whether to output the data signal according to a value of the data latch signal.

3. The display panel of claim 1, wherein, Further comprising:

4. The display panel of claim 3, wherein, A power manager is configured to transmit a first voltage signal to the timing controller, the first voltage signal being configured to drive the timing controller to generate the data latch signal. Further comprising:

5. The display panel of claim 1, wherein, A power manager is electrically connected to the electrode driver and is configured to transmit the to-be-detected voltage signal to the electrode driver, and the voltage detector is electrically connected to the power manager or the electrode driver to obtain the to-be-detected voltage signal. The voltage detector comprises:

6. The display panel of any one of claims 1 to 5, wherein, A first input terminal is configured to load the to-be-detected voltage signal. A second input terminal is configured to load a second voltage signal. An output terminal is electrically connected to the timing controller and is configured to output the control signal. The voltage detector is configured to generate the control signal according to the to-be-detected voltage signal and the second voltage signal. The voltage detector comprises:

7. The display panel of claim 6, wherein, An input unit comprises a first resistor, a second resistor and a first node, the first resistor being electrically connected between the first input terminal and the first node, and the second resistor being electrically connected between the ground and the first node. An output unit comprises a third resistor, a switching element and a second node, the third resistor being electrically connected between the second input terminal and the second node, a control terminal of the switching element being electrically connected to the first node, a first terminal of the switching element being electrically connected to the second node, and a second terminal of the switching element being electrically connected to the ground. The voltage detector is configured to obtain a to-be-detected voltage signal and generate a control signal according to a size relationship between the to-be-detected voltage signal and a preset value, the to-be-detected voltage signal being configured to provide a working voltage for the electrode driver to transmit the data signal to the plurality of sub-pixels.

8. A driving method of a display panel, characterized by, The timing controller is configured to control the electrode driver to output or not to output the data signal according to the control signal. ​ ​ 9. The driving method of a display panel according to claim 8, wherein The step of generating the control signal according to the size relationship between the to-be-detected voltage signal and the preset value comprises: judging whether the value of the to-be-detected voltage signal is greater than or equal to the preset value; if the value of the to-be-detected voltage signal is greater than or equal to the preset value, controlling the value of the generated control signal to be a first value; if the value of the to-be-detected voltage signal is less than the preset value, controlling the value of the generated control signal to be a second value; The step of controlling whether the source driver outputs the data signal according to the control signal to control whether the value of the to-be-detected voltage signal rises comprises: judging whether the value of the control signal is the first value; if the value of the control signal is the first value, controlling the source driver to work to output the data signal; judging whether the value of the control signal is the second value; if the value of the control signal is the second value, controlling the source driver not to work to not output the data signal.

10. The driving method of a display panel according to claim 9, wherein The step of controlling the source driver to work to output the data signal comprises: controlling the value of the generated latch signal to be a third value to control the source driver to work to output the data signal; The step of controlling the source driver not to work to not output the data signal comprises: controlling the value of the generated latch signal to be a fourth value to control the source driver not to work to not output the data signal.

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