Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device. The array substrate comprises a substrate; a plurality of sub-pixels; a plurality of grid lines and a plurality of data lines, the grid lines and the data lines intersect, and the sub-pixels are located at positions limited by two adjacent grid lines and two adjacent data lines; each sub-pixel comprises a pixel driving circuit and a light-emitting device which are connected; the pixel driving circuit comprises a driving module and a first control module. The pixel driving circuit further comprises an auxiliary anode, the auxiliary anode is located between the anode and the substrate, and the auxiliary anode is electrically connected with the anode. The first power supply signal line comprises a first part and a second part which are electrically connected, the first part of the first power supply signal line and the first control signal line are arranged on the same layer, and the second part of the first power supply signal line and the auxiliary anode are arranged on the same layer. And the problem of signal crosstalk of two adjacent sub-pixels is solved.

Description

[0001] This application is a divisional application based on the invention patent filed on January 4, 2023, with application number 202380000009.X and entitled "An Array Substrate, Display Panel and Display Device". Technical Field

[0002] This application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0003] Micro-LED (Micro Light-Emitting Diode) display devices are micro-displays that have emerged in recent years, with silicon-based OLED micro-displays being one type. Silicon-based OLED micro-displays not only enable active pixel addressing but also allow for the fabrication of pixel driving circuits and other structures on silicon substrates, which facilitates size reduction and weight reduction. Summary of the Invention

[0004] The embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, embodiments of this application provide an array substrate, comprising:

[0006] Substrate;

[0007] Multiple sub-pixels arranged in an array on the substrate;

[0008] The system comprises multiple gate lines and multiple data lines, wherein the gate lines and data lines intersect, and the sub-pixel is located at a position defined by two adjacent gate lines and two adjacent data lines; the sub-pixel includes an electrically connected pixel driving circuit and a light-emitting device; wherein the pixel driving circuit includes:

[0009] The driving module is electrically connected to the first node, the second node, and the anode of the light-emitting device, respectively. It is configured to conduct the path between the second node and the anode under the control of the voltage of the first node, and to generate a current in the path for emitting light from the light-emitting device; the second node is coupled to the first power signal line.

[0010] The first control module is electrically connected to the first control signal line, the second power signal line and the anode of the light-emitting device, and is configured to transmit the second power signal transmitted by the second power signal line to the anode under the control of the first control signal transmitted by the first control signal line.

[0011] The pixel driving circuit further includes an auxiliary anode, which is located between the anode and the substrate and is electrically connected to the anode; the first power signal line includes a first part and a second part that are electrically connected, the first part of the first power signal line is disposed on the same layer as the first control signal line, and the second part of the first power signal line is disposed on the same layer as the auxiliary anode.

[0012] In some embodiments of this application, the pixel driving circuit further includes a second control module;

[0013] The second control module is electrically connected to the first power signal line, the second control signal line and the drive module respectively, and is configured to transmit the first power signal transmitted in the first power signal line to the drive module under the control of the second control signal transmitted in the second control signal line, thereby assisting in generating a current in the path to make the light-emitting device emit light.

[0014] Wherein, the orthographic projection of the second control module on the substrate overlaps with the orthographic projection of the second part of the first power signal line on the substrate.

[0015] In some embodiments of this application, the pixel driving circuit further includes an input module;

[0016] The input module is electrically connected to the gate line, the data line and the first node respectively, and is configured to write the data signal transmitted by the data line into the first node under the control of the scan signal transmitted by the gate line.

[0017] The orthographic projection of the input module on the substrate overlaps with the orthographic projection of the gate line on the substrate, and the orthographic projection of the input module on the substrate overlaps with the orthographic projection of the second control signal line on the substrate.

[0018] In some embodiments of this application, the input module and the second control module are located on the same side of the drive module, and the first control module is located on the side of the drive module away from the second control module.

[0019] In some embodiments of this application, the input module includes a first transistor, the driving module includes a driving transistor, the second control module includes a second transistor, and the first control module includes a third transistor.

[0020] The gate of the first transistor is electrically connected to the gate line, the source of the first transistor is electrically connected to the data line, and the drain of the first transistor is electrically connected to the gate of the driving transistor.

[0021] The gate of the second transistor is electrically connected to the second control signal line, the source of the second transistor is electrically connected to the first power signal line, and the drain of the second transistor is electrically connected to the source of the driving transistor.

[0022] The gate of the third transistor is electrically connected to the first control signal line, the source of the third transistor is electrically connected to the drain of the driving transistor, and the drain of the third transistor is electrically connected to the second power supply signal line.

[0023] In some embodiments of this application, the pixel driving circuit further includes a first trace, the extension direction of the first trace intersects the extension direction of the first control signal line, the first trace is electrically connected to the gate of the third transistor and the first control signal line respectively, and the first trace and the data line are disposed on the same layer.

[0024] In some embodiments of this application, the orthographic projection of the gate of the third transistor on the substrate overlaps with the orthographic projection of the first control signal line on the substrate, the orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the gate of the third transistor on the substrate, the orthographic projection of the first trace on the substrate extends from the side of the gate of the third transistor near the first control signal line to the side of the gate of the third transistor away from the first control signal line, and the orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the active region of the third transistor on the substrate.

[0025] In some embodiments of this application, the pixel driving circuit further includes a second trace, the extension direction of the second trace being consistent with the extension direction of the data line, the second trace being electrically connected to the source of the second transistor and the first power signal line respectively, and the second trace and the data line being disposed on the same layer.

[0026] In some embodiments of this application, the extension direction of the second trace intersects the extension direction of the gate line, and the orthographic projection of the second trace on the substrate overlaps with the orthographic projection of the gate line on the substrate.

[0027] The orthographic projection of the second trace on the substrate extends from the location of the orthographic projection of the source of the second transistor on the substrate to the location of the orthographic projection of the first portion of the first power signal line on the substrate.

[0028] In some embodiments of this application, the orthographic projection of the second control signal line on the substrate overlaps with the orthographic projections of the gate of the first transistor and the gate of the second transistor on the substrate, respectively.

[0029] The orthographic projection of the gate line on the substrate overlaps with the orthographic projection of the gate of the first transistor on the substrate, and the orthographic projection of the gate line on the substrate overlaps with the orthographic projection of the active region of the first transistor on the substrate.

[0030] In some embodiments of this application, within the same region of the second control signal line, the distance between the gate of the first transistor and the gate of the driving transistor in a direction parallel to the data line is greater than the distance between the gate of the second transistor and the gate of the driving transistor in a direction parallel to the data line.

[0031] In some embodiments of this application, within the region where the sub-pixels are located in the same row, along a direction parallel to the data line, the minimum distance between the overlapping segment of the second control signal line and the gate of the first transistor and the gate line is less than the minimum distance between the overlapping segment of the second control signal line and the gate of the second transistor and the gate line.

[0032] In some embodiments of this application, the orthographic projection of the data line on the substrate overlaps with the orthographic projection of the first portion of the first power signal line on the substrate.

[0033] The orthographic projections of the first transistor, the second transistor, the second control signal line, and the gate line on the substrate are respectively located within the orthographic projection of the second portion of the first power signal line on the substrate.

[0034] In some embodiments of this application, the first power signal line further includes a third portion, the extension direction of the third portion of the first power signal line intersecting the extension direction of the first control signal line; the third portion of the first power signal line connects the first portions of the first power signal lines in two adjacent rows of sub-pixels together.

[0035] The orthographic projection of the third portion of the first power signal line on the substrate overlaps with the orthographic projection of the data line on the substrate and the orthographic projection of the first control signal line on the substrate.

[0036] In some embodiments of this application, the first portion of the first power signal line and the third portion of the first power signal line together form a grid shape on the substrate, and the sub-pixel is located in the closed area defined by the grid.

[0037] In some embodiments of this application, the array substrate includes a semiconductor layer located on the substrate, the semiconductor layer including a first portion, a second portion, a third portion, a fourth portion, a fifth portion, and a sixth portion; the area of ​​the orthographic projection of the fourth portion of the semiconductor layer on the substrate is larger than the area of ​​the orthographic projection of the other portions on the substrate.

[0038] The first part of the semiconductor layer includes the source, drain, and active region of the first transistor; the second part of the semiconductor layer includes the source, drain, and active region of the second transistor; the third part of the semiconductor layer includes the source, drain, and active region of the third transistor; the fourth part of the semiconductor layer includes the source, drain, and active region of the driving transistor; the fifth and sixth parts are both electrically connected to the substrate.

[0039] In one of the sub-pixel regions, the second part and the fourth part of the semiconductor layer are integrated; in the same row of sub-pixels perpendicular to the extension direction of the data line, two sub-pixels are grouped together, and in the same group of sub-pixels regions, the two third parts of the semiconductor layer are integrated.

[0040] In some embodiments of this application, two third transistors are symmetrically arranged in the same group of sub-pixels, and two sixth portions of the semiconductor layer are symmetrically arranged.

[0041] In some embodiments of this application, the array substrate further includes a gate layer located on the side of the semiconductor layer away from the substrate.

[0042] The gate layer includes the gate of each transistor. The orthographic projection of the gate layer on the substrate overlaps with the orthographic projection of the semiconductor layer on the substrate. The region in the semiconductor layer that overlaps with the orthographic projection of the gate layer on the substrate is the active region of each transistor. The region in the semiconductor layer that does not overlap with the orthographic projection of the gate layer on the substrate is the source or drain of each transistor. The area of ​​the orthographic projection of the gate of the driving transistor on the substrate is larger than the area of ​​the orthographic projection of the gates of the other transistors on the substrate.

[0043] In some embodiments of this application, the array substrate further includes a first conductive layer located on the side of the gate layer away from the substrate.

[0044] The first conductive layer includes a third power signal line, the gate line, the second control signal line, and the second power signal line;

[0045] The third power signal line is electrically connected to the fifth part of the semiconductor layer, and the second power signal line is electrically connected to the sixth part of the semiconductor layer.

[0046] In some embodiments of this application, in the region where the sub-pixels are located in the same row perpendicular to the extension direction of the data line, the third power signal line includes a first line segment and a plurality of second line segments. The first line segment is connected to each of the second line segments respectively, and the second line segments are electrically connected to the fifth portion of the semiconductor layer. The extension direction of the first line segment intersects with the extension direction of the data line, and the extension direction of each of the second line segments is consistent with the extension direction of the data line. The orthographic projection of the first line segment on the substrate overlaps with the orthographic projection of the driving transistor on the substrate, and the orthographic projection of the second line segment on the substrate overlaps with the orthographic projection of the fifth portion of the semiconductor layer on the substrate.

[0047] In the region where the sub-pixels are located in the same row perpendicular to the extension direction of the data line, the second power signal line includes a third segment, a plurality of fourth segments, and a plurality of fifth segments. The third segment is connected to each of the fourth segments and each of the fifth segments respectively. The fourth segments are electrically connected to the drain of the third transistor. The fifth segments are electrically connected to the sixth part of the semiconductor layer. The extension direction of each of the fourth segments and each of the fifth segments is consistent with the extension direction of the data line. The extension direction of the third segment intersects with the extension direction of the data line. The orthographic projection of the fifth segment on the substrate overlaps with the orthographic projection of the sixth part of the semiconductor layer on the substrate.

[0048] In some embodiments of this application, the first conductive layer further includes a first connection portion, a second connection portion, and a third connection portion. The first connection portion is electrically connected to the source of the third transistor and the drain of the driving transistor, respectively. The second connection portion is electrically connected to the gate of the driving transistor and the drain of the first transistor, respectively. The third connection portion is electrically connected to the source of the first transistor and the data line, respectively.

[0049] The orthographic projection of the third connection portion on the substrate overlaps with the orthographic projection of the first portion of the first power signal line on the substrate.

[0050] In some embodiments of this application, the pixel driving circuit further includes a compensation module, which is electrically connected to the first node, the second node and the first power signal line respectively, and is configured to compensate the threshold voltage of the driving module.

[0051] The compensation module includes a first capacitor and a second capacitor. The first plate of the first capacitor is electrically connected to the source of the driving transistor, and the second plate of the first capacitor is electrically connected to the gate of the driving transistor. The first plate of the second capacitor is electrically connected to the source of the driving transistor, and the second plate of the second capacitor is electrically connected to the first power signal line.

[0052] In some embodiments of this application, the array substrate further includes a second conductive layer located on the side of the first conductive layer away from the substrate, the second conductive layer including the data line and the first conductive pattern, the first conductive pattern being electrically connected to the source of the driving transistor;

[0053] The second conductive layer also includes the first trace and the second trace.

[0054] In some embodiments of this application, the array substrate further includes a third conductive layer located on the side of the second conductive layer away from the substrate, the third conductive layer including the first control signal line, the second electrode of the first capacitor, and a first portion of the first power signal line;

[0055] In the region where the sub-pixels are located in the same row perpendicular to the extension direction of the data line, the first part of the first power signal line includes a sixth segment and a plurality of seventh segments, each of the seventh segments being connected to the sixth segment. The seventh segment is located between the second plates of two adjacent first capacitors, and the sixth segment is located on the side of the second plate of each first capacitor away from the first control signal line. The sixth segment is in the same extension direction as the first control signal line.

[0056] The orthographic projection of the sixth line segment on the substrate overlaps with the orthographic projection of the first transistor on the substrate, and the orthographic projection of the seventh line segment on the substrate overlaps with the orthographic projection of the data line on the substrate.

[0057] In some embodiments of this application, the array substrate further includes a capacitive conductive layer located on the side of the third conductive layer away from the substrate. The capacitive conductive layer includes a second conductive pattern, the orthographic projection of the second conductive pattern on the substrate overlaps with the orthographic projection of the first conductive pattern on the substrate, and the second conductive pattern is indirectly electrically connected to the first conductive pattern.

[0058] In some embodiments of this application, the array substrate further includes a fourth conductive layer located on the side of the capacitive conductive layer away from the substrate, the fourth conductive layer including a third conductive pattern, the third conductive pattern being electrically connected to the first conductive pattern and the third conductive pattern being electrically connected to the second conductive pattern;

[0059] The first conductive pattern, the second conductive pattern, and the third conductive pattern together serve as the first electrode of the first capacitor and the first electrode of the second capacitor.

[0060] In some embodiments of this application, the fourth conductive layer further includes a third portion of the first power signal line and an adapter cable;

[0061] The third part of the first power signal line electrically connects the seventh line segment in two adjacent rows of the sub-pixels together. The adapter line is electrically connected to the sixth line segment and the second part of the first power signal line respectively. The orthographic projection of the adapter line on the substrate overlaps with the orthographic projection of the sixth line segment on the substrate.

[0062] In some embodiments of this application, the array substrate further includes a fifth conductive layer located on the side of the fourth conductive layer away from the substrate, and a sixth conductive layer located on the side of the fifth conductive layer away from the substrate.

[0063] The fifth conductive layer includes the second electrode of the second capacitor, and the sixth conductive layer includes the second part of the first power signal line and the auxiliary anode. The second electrode of the second capacitor is electrically connected to the second part of the first power signal line. The orthographic projection of the auxiliary anode on the substrate overlaps with the orthographic projections of the third transistor and the driving transistor on the substrate.

[0064] In some embodiments of this application, in the region where the sub-pixels are located in the same row perpendicular to the extension direction of the data line, the shape of the orthographic projection of the second portion of the first power signal line on the substrate is comb-shaped, and the area of ​​the orthographic projection of the second portion of the first power signal line on the substrate is larger than the area of ​​the orthographic projection of the first portion of the first power signal line on the substrate.

[0065] In some embodiments of this application, in the region where the sub-pixels are located in the same row perpendicular to the extension direction of the data line, the second portion of the first power signal line includes a main extension and a plurality of branch extensions.

[0066] The orthographic projection of the main extension on the substrate covers the orthographic projections of the first transistor, the second transistor, the gate line, the second control signal line, and the sixth line segment on the substrate. The branch extension is located in the region between two adjacent auxiliary anodes, and the branch extension overlaps with the orthographic projections of the seventh line segment and the data line on the substrate.

[0067] Secondly, embodiments of this application provide a display panel including an array substrate as described in any one of the first aspects.

[0068] Thirdly, embodiments of this application provide a display device including a display panel as described in the second aspect.

[0069] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0070] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0071] Figure 1 A schematic diagram of a pixel driving circuit provided for an embodiment of this application;

[0072] Figures 2-5 for Figure 1 The diagram illustrates the working principle of the four stages of the pixel driving circuit.

[0073] Figure 6 A top view of the semiconductor layer on the array substrate provided for an embodiment of this application;

[0074] Figure 7 A simplified design layout of the pixel driving circuit on the array substrate provided for embodiments of this application;

[0075] Figure 8 A top view of the gate layer structure provided in an embodiment of this application;

[0076] Figure 9 A top view of the stacked semiconductor layer and gate layer on the array substrate provided for an embodiment of this application;

[0077] Figure 10 A top view of the first conductive layer provided for an embodiment of this application;

[0078] Figure 11 A top view of the stacked semiconductor layer, gate layer, and first conductive layer on an array substrate provided for an embodiment of this application;

[0079] Figure 12 A top view of the second conductive layer provided in an embodiment of this application;

[0080] Figure 13 A top view of the stacked semiconductor layer, gate layer, first conductive layer, and second conductive layer on an array substrate provided for an embodiment of this application;

[0081] Figure 14 A top view of the third conductive layer provided in an embodiment of this application;

[0082] Figure 15 A top view of the stacked semiconductor layer, gate layer, first conductive layer, second conductive layer, and third conductive layer on an array substrate provided for embodiments of this application;

[0083] Figure 16 A top view of the capacitive conductive layer provided in an embodiment of this application;

[0084] Figure 17 A top view of the stacked semiconductor layer, gate layer, first conductive layer, second conductive layer, third conductive layer, and capacitor conductive layer on an array substrate provided for embodiments of this application;

[0085] Figure 18 A top view of the fourth conductive layer provided in an embodiment of this application;

[0086] Figure 19 A top view of the stacked semiconductor layer, gate layer, first conductive layer, second conductive layer, third conductive layer, capacitor conductive layer, and fourth conductive layer on an array substrate provided for embodiments of this application;

[0087] Figure 20 A top view of a first portion and a second portion of a first power signal line provided for an embodiment of this application;

[0088] Figure 21 A top view of a first portion, a second portion, and a third portion of a first power signal line provided for an embodiment of this application;

[0089] Figure 22 A top view of the fifth conductive layer provided in an embodiment of this application;

[0090] Figure 23 A top view of the stacked semiconductor layer, gate layer, first conductive layer, second conductive layer, third conductive layer, capacitor conductive layer, fourth conductive layer, and fifth conductive layer on an array substrate provided for embodiments of this application;

[0091] Figure 24 A top view of the fifth conductive layer provided in an embodiment of this application;

[0092] Figure 25 for Figure 1 The signal timing diagram of the pixel driving circuit shown is shown below;

[0093] Figure 26 A top view of the stacked semiconductor layer, gate layer, first conductive layer, second conductive layer, third conductive layer, capacitor conductive layer, fourth conductive layer, fifth conductive layer, and sixth conductive layer on an array substrate provided for embodiments of this application.

[0094] Figure 27 A top view of the second and third power signal lines in the same row of sub-pixels provided for embodiments of this application;

[0095] Figure 28 A top view of the first power signal line, second power signal line, third power signal line, first control signal, and gate line provided for embodiments of this application. Detailed Implementation

[0096] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0097] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0098] Additionally, it should be noted that when describing the elements and embodiments thereof in this application, the articles “a,” “an,” “the,” and “the” are intended to indicate the presence of one or more elements; unless otherwise stated, “multiple” means two or more; the terms “comprising,” “including,” “containing,” and “having” are intended to be inclusive and indicate that additional elements may exist besides those listed; the terms “first,” “second,” “third,” etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or order of formation.

[0099] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0100] In this specification, "electrical connection" and "coupling" include situations where components are connected together by elements that have some electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0101] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0102] The polygons used in this specification are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, etc. They may have minor deformations due to tolerances, and may include chamfers, fillets, curved edges, and other variations.

[0103] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes the state where the angle is greater than -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes the state where the angle is greater than 85° and less than 95°.

[0104] Exemplary embodiments will now be described more fully with reference to the accompanying drawings.

[0105] Silicon-based OLED microdisplays mainly consist of a driving module (also known as an array substrate) called a silicon-based BP (Backplate) and a device component called an OLED (Organic Light Emitting Diode). The silicon-based BP mainly comprises a pixel driving circuit array, a source driver, a gate driver, an emission control driver, an oscillator (OSC), a gamma register, an interface, and a display control module. The OLED device component mainly consists of the OLED, a thin-film encapsulation (TFE), a color filter (CF), and a microlens. Compared to traditional glass-based BPs, silicon-based BPs offer advantages in reducing system size and achieving lightweight design, and are more suitable for display products with high PPI (Pixels Per Inch) and narrow bezels.

[0106] This application provides an array substrate, comprising:

[0107] Substrate;

[0108] Multiple sub-pixels arranged in an array on a substrate;

[0109] Multiple gate lines (WS) and multiple data lines (DL) intersect. A sub-pixel (e.g., P1 or P2) is located at a position defined by two adjacent gate lines (WS) and two adjacent data lines (DL). The sub-pixel includes an electrically connected pixel driving circuit and a light-emitting device. Wherein, combined with... Figure 1 and Figure 7 As shown, the pixel driving circuit includes:

[0110] The driving module 2 is electrically connected to the first node G, the second node S and the anode of the light-emitting device 6 respectively. It is configured to conduct the path between the second node S and the anode under the control of the voltage of the first node G, and generate a current in the path to make the light-emitting device 6 emit light. The second node S is coupled to the first power signal line ELVDD.

[0111] The first control module 5 is electrically connected to the first control signal line AZ, the second power signal line VSS and the anode of the light-emitting device 6, respectively, and is configured to transmit the second power signal transmitted by the second power signal line VSS to the anode under the control of the first control signal transmitted by the first control signal line AZ.

[0112] The pixel driving circuit also includes an auxiliary anode ANF, which is located between the anode AN and the substrate and is electrically connected to the anode AN. The first power signal line ELVDD includes a first part ELVDD-1 and a second part ELVDD-2 that are electrically connected. The first part ELVDD-1 of the first power signal line is disposed on the same layer as the first control signal line AZ, and the second part ELVDD-2 of the first power signal line is disposed on the same layer as the auxiliary anode ANF. The first control signal line AZ and the auxiliary anode ANF are located on different layers.

[0113] To be clear, in Figure 7 In this document, some parts of the pixel driving circuit structure are simplified or omitted to show the arrangement of the main components and signal lines in the pixel driving circuit. This is hereby explained.

[0114] It should be noted that the first node G and the second node S in the above pixel driving circuit do not actually exist. They are just concepts proposed for the convenience of describing the connection relationship of the circuit.

[0115] For example, the driving module 2 includes a driving transistor DMOS, and the first control module 5 includes a third transistor T3.

[0116] In an exemplary embodiment, the substrate can be a rigid substrate, such as a silicon substrate or a glass substrate; or the substrate can be a flexible substrate, such as a flexible polyimide or other flexible polymer film.

[0117] The silicon substrate material mentioned above includes silicon, such as monocrystalline silicon or polycrystalline silicon. Before fabricating the pixel driving circuit, N-type ion implantation can be performed on the silicon substrate to form an N-well region (NW), followed by P-type ion implantation in the NW region to form an SP region, which is used to form the channel region of the transistor. The specific processing steps for the silicon substrate are not limited here; only the fabrication of a PMOS transistor (P-type Metal Oxide Semiconductor) is used as an example to illustrate the ion implantation types in different regions of the silicon substrate. When the transistor is an NMOS transistor, the specific processing steps for the silicon substrate are similar to those described above, but the polarity of the ion implantation is reversed in each step. The specific processing steps for the silicon substrate can be found in relevant technical descriptions and will not be repeated here.

[0118] The display color of each of the above sub-pixels is not limited here;

[0119] In some embodiments, the display color of each sub-pixel can be the same, for example, all sub-pixels can display blue, or for another example, all sub-pixels can display white;

[0120] In other embodiments, the array substrate may include multiple sub-pixels that display different colors. For example, the array substrate may simultaneously include three sub-pixels that display red, blue, and green; or, for another example, the array substrate may simultaneously include four sub-pixels that display red, blue, green, and white.

[0121] The type of the light-emitting device 6 mentioned above is not limited here.

[0122] For example, the light-emitting device 6 mentioned above can be a light-emitting diode, etc.; the light-emitting diode can be an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro light-emitting diode (Micro-LED), etc.

[0123] For example, the first power signal line ELVDD can continuously provide a high-level voltage signal, and the signal provided by the first power signal line ELVDD is called the ELVDD signal; the second power signal line VSS can continuously provide a low-level voltage signal, and the signal provided by the second power signal line VSS is called the VSS signal.

[0124] "Same-layer configuration" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials can be the same or different. For example, the precursors of multiple structures forming a same-layer configuration are made of the same material, while the final materials can be the same or different.

[0125] For example, the first portion of the first power signal line, ELVDD-1, is disposed in the same layer and made of the same material as the first control signal line, AZ; wherein, the first control signal line, AZ, can be a reset signal line.

[0126] For example, the second portion of the first power signal line, ELVDD-2, is disposed in the same layer as the auxiliary anode, ANF, and is made of the same material.

[0127] In the embodiments of this application, by setting the first power signal line ELVDD to include an electrically connected first part ELVDD-1 and a second part ELVDD-2, the first part ELVDD-1 of the first power signal line is disposed in the same layer as the first control signal line AZ, and the second part ELVDD-2 of the first power signal line is disposed in the same layer as the auxiliary anode ANF. The film layer where the auxiliary anode ANF is located is located in a different layer from the film layer where the first control signal line AZ is located. In this way, the conductivity of the first power signal line ELVDD can be significantly improved, the IR drop problem of the first power signal line ELVDD can be reduced, and the stability of the signal provided by the first power signal line ELVDD to the pixel driving circuit of each sub-pixel can be improved, thereby improving the stability and uniformity of the luminous brightness of each sub-pixel and improving the display effect.

[0128] In some embodiments of this application, such as Figure 1 As shown, the pixel driving circuit also includes a second control module 4;

[0129] The second control module 4 is electrically connected to the first power signal line ELVSS, the second control signal line DS, and the drive module 2, respectively. It is configured to transmit the first power signal transmitted in the first power signal line ELVDD to the drive module 2 under the control of the second control signal transmitted in the second control signal line DS, and generate a current in the auxiliary path to make the light-emitting device 6 emit light; the voltage of the first power signal is greater than the voltage of the second power signal.

[0130] The orthographic projection of the second control module 4 on the substrate overlaps with the orthographic projection of the second part of the first power signal line ELVDD-2 on the substrate.

[0131] For example, the second control module 4 includes a second transistor T2.

[0132] The term "overlapping" as used above refers to at least partial overlap. The relevant descriptions in this specification are similar in meaning to this, and will not be repeated here.

[0133] For example, the orthographic projection of the second control module 4 on the substrate is located within the orthographic projection of the second part ELVDD-2 of the first power signal line on the substrate.

[0134] In the embodiments of this application, by setting the orthographic projection of the second control module 4 on the substrate to overlap with the orthographic projection of the second part ELVDD-2 of the first power signal line on the substrate, the size of the second part ELVDD-2 of the first power signal line is greatly increased. In this way, the conductivity of the first power signal line ELVDD can be significantly improved, the IR drop problem of the first power signal line ELVDD can be reduced, and the stability of the signal provided by the first power signal line ELVDD to the pixel driving circuit of each sub-pixel can be improved, thereby improving the stability and uniformity of the luminous brightness of each sub-pixel and improving the display effect.

[0135] In some embodiments of this application, such as Figure 1 As shown, the pixel driving circuit also includes an input module 1; the input module 1 is electrically connected to the gate line WS, the data line DL and the first node G respectively, and is configured to write the data signal transmitted by the data line DL into the first node G under the control of the scan signal transmitted by the gate line WS.

[0136] Among them, such as Figure 7 As shown, the orthographic projection of the input module 1 on the substrate overlaps with the orthographic projection of the gate line WS on the substrate, and the orthographic projection of the input module 1 on the substrate overlaps with the orthographic projection of the second control signal line DS on the substrate.

[0137] For example, input module 1 includes a first transistor T1.

[0138] For example, such as Figure 7 As shown, the orthographic projection of the input module 1 on the substrate overlaps with the orthographic projection of the gate line WS on the substrate, and the orthographic projection of the input module 1 on the substrate overlaps with the orthographic projection of the second control signal line DS on the substrate.

[0139] In some embodiments of this application, such as Figure 7 As shown, the input module 1 and the second control module 4 are located on the same side of the drive module 2, and the first control module 5 is located on the side of the drive module 2 away from the second control module 4.

[0140] For example, input module 1 includes a first transistor T1, driving module 2 includes a driving transistor DMOS, second control module 4 includes a second transistor T2, and first control module 5 includes a third transistor T3.

[0141] The gate of the first transistor T1 is electrically connected to the gate line WS, the source of the first transistor T1 is electrically connected to the data line DL, and the drain of the first transistor T1 is electrically connected to the gate of the driving transistor DMOS.

[0142] The gate of the second transistor T2 is electrically connected to the second control signal line DS, the source of the second transistor T2 is electrically connected to the first power supply signal line ELVDD, and the drain of the second transistor T2 is electrically connected to the source of the driving transistor DMOS.

[0143] The gate of the third transistor T3 is electrically connected to the first control signal line AZ, the source of the third transistor T3 is electrically connected to the drain of the driving transistor DMOS, and the drain of the third transistor T3 is electrically connected to the second power supply signal line VSS.

[0144] In an exemplary embodiment, in order to save space for the arrangement of components and traces in the pixel driving circuit, the source (or drain) of one transistor can be shared with the source (or drain) of another transistor.

[0145] For example, the drain of the second transistor T2 and the source of the driving transistor DMOS can be configured as an integrated structure; for example, the drain of the second transistor T2 and the source of the driving transistor DMOS can share the same structure.

[0146] For example, the source of the third transistor T3 and the drain of the driving transistor DMOS can be configured as an integrated structure; for example, the source of the third transistor T3 and the drain of the driving transistor DMOS can share the same structure.

[0147] For example, the drains of two third transistors T3 in two adjacent sub-pixels can be set to an integrated structure; or the drains of two third transistors T3 in two adjacent sub-pixels can be set to share the same structure.

[0148] It should be noted that an integrated structure refers to a structure formed using the same precursor material in the same manufacturing process; the final materials of the two structures corresponding to an integrated structure can be the same or different; sharing a structure means that the two structures are formed using the same material in the same manufacturing process, and the final materials are the same.

[0149] There are no restrictions on the types of transistors mentioned above.

[0150] For example, each transistor can be a P-type MOS transistor; for example, each transistor can be an N-type MOS transistor; for example, some transistors are P-type MOS transistors and some transistors are N-type MOS transistors, for example, the driving transistor DMOS is a P-type MOS transistor and the other transistors are N-type MOS transistors, or for another example, the driving transistor DMOS is an N-type MOS transistor and the other transistors are P-type MOS transistors.

[0151] In the pixel driving circuit design layout provided in this specification, the third transistor T3 is an N-type MOS transistor, and the other transistors are P-type MOS transistors, as an example for illustration. Based on this, pixel driving circuit design layouts derived by changing the transistor types are all within the scope of protection of this application.

[0152] In some embodiments of this application, such as Figure 7 As shown, the pixel driving circuit also includes a first trace M2-1. The extension direction of the first trace M2-1 intersects the extension direction of the first control signal line AZ. The first trace M2-1 is electrically connected to the gate of the third transistor T3 and the first control signal line AZ, respectively. The first trace M2-1 and the data line DL are arranged on the same layer.

[0153] For example, such as Figure 7 As shown, the first trace M2-1 and the data line DL are both located in the first conductive layer M1.

[0154] For example, such as Figure 7 As shown, the orthographic projection of the first trace M2-1 on the substrate overlaps with the orthographic projection of the gate of the third transistor T3 on the substrate.

[0155] In some embodiments of this application, such as Figure 7 As shown, the orthographic projection of the gate of the third transistor T3 on the substrate overlaps with the orthographic projection of the first control signal line AZ on the substrate. The orthographic projection of the first trace M2-1 on the substrate overlaps with the orthographic projection of the gate of the third transistor T3 on the substrate. The orthographic projection of the first trace M2-1 on the substrate extends from the side of the gate of the third transistor T3 near the first control signal line AZ to the side of the gate of the third transistor T3 away from the first control signal line AZ. The orthographic projection of the first trace M2-1 on the substrate overlaps with the orthographic projection of the active region of the third transistor T3 on the substrate.

[0156] For example, such as Figure 7 As shown in the elliptical dashed circle, the first trace M2-1 is electrically connected to the gate of the third transistor T3 at a position on the side of the gate of the third transistor T3 away from the first control signal line AZ.

[0157] Additionally, in some embodiments, such as Figure 7 As shown in the rectangular dashed box, the connection point between the first trace M2-1 and the first control signal line AZ is located in the region where the first trace M2-1 and the first control signal line AZ overlap, and the gate of the first trace M2-1 and the third transistor T3 do not overlap.

[0158] In some embodiments of this application, such as Figure 7As shown, the pixel driving circuit also includes a second trace M2-2. The extension direction of the second trace M2-2 is consistent with the extension direction of the data line DL. The second trace M2-2 is electrically connected to the source of the second transistor T2 and the first power signal line ELVDD, respectively. The second trace M2-2 and the data line DL are arranged on the same layer.

[0159] For example, such as Figure 7 As shown, the second trace M2-2 and the data line DL are both located in the first conductive layer M1.

[0160] For example, such as Figure 7 As shown, the second trace M2-2 is electrically connected to the first part of the first power signal line ELVDD-1, and the source of the second transistor T2 is electrically connected to the first part of the first power signal line ELVDD-1 through the second trace M2-2.

[0161] For example, such as Figure 7 As shown, the extension direction of the second trace M2-2 intersects the extension direction of the gate line WS, and the orthographic projection of the second trace M2-2 on the substrate overlaps with the orthographic projection of the gate line WS on the substrate.

[0162] The orthographic projection of the second trace M2-2 on the substrate extends from the location of the orthographic projection of the source of the second transistor T2 on the substrate to the location of the orthographic projection of the first part of the first power signal line ELVDD-1 on the substrate.

[0163] In an exemplary embodiment, the second trace M2-2 may be aligned with the extension direction of the data line DL and cross the gate line WS and the first portion ELVDD-1 of the first power signal line (e.g. Figure 7 The first portion of the first power signal line (the horizontally extending segment) is electrically connected together; in other embodiments, the second trace M2-2 may intersect the extension direction of the data line DL and cross the gate line WS to the first portion ELVDD-1 of the first power signal line (e.g., Figure 7 The vertically extending segment of the first part of the first power signal line is electrically connected together. In this specification, the second trace M2-2 extends in the same direction as the data line DL and crosses the gate line WS to connect with the first part ELVDD-1 of the first power signal line (e.g., Figure 7 The following explanation uses the example of a horizontally extending segment in the first part of the first power signal line being electrically connected together.

[0164] In some embodiments of this application, such as Figure 7 As shown, the orthographic projection of the second control signal line DS on the substrate overlaps with the orthographic projections of the gate of the first transistor T1 and the gate of the second transistor T2 on the substrate.

[0165] The orthographic projection of the gate line WS on the substrate overlaps with the orthographic projection of the gate of the first transistor T1 on the substrate, and the orthographic projection of the gate line WS on the substrate overlaps with the orthographic projection of the active region of the first transistor T1 on the substrate.

[0166] In this specification, a transistor is a device that includes at least three terminals: a gate electrode (also called a gate), a drain electrode (also called a drain), and a source electrode (also called a source). A transistor has a channel region (active region) between the drain and source, and current can flow through the drain, the channel region, and the source. Note that in this specification, the channel region refers to the region through which current primarily flows. In cases where transistors of opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0167] In some embodiments of this application, such as Figure 7 As shown, within the same region of the second control signal line DS, the distance h1 between the gate of the first transistor T1 and the gate of the driving transistor DMOS along the direction parallel to the data line DL is greater than the distance h2 between the gate of the second transistor T2 and the gate of the driving transistor DMOS along the direction parallel to the data line DL.

[0168] In some embodiments of this application, such as Figure 7 As shown, within the same row of sub-pixels, along the direction parallel to the data line DL, the minimum distance h3 between the overlapping segment of the second control signal line DS and the gate of the first transistor T1 and the gate line WS is less than the minimum distance h4 between the overlapping segment of the second control signal line DS and the gate of the second transistor T2 and the gate line WS.

[0169] In some embodiments of this application, such as Figure 7 As shown, the orthographic projection of the data line DL on the substrate overlaps with the orthographic projection of the first part of the first power signal line ELVDD-1 on the substrate.

[0170] Combination Figure 7 and Figure 28 As shown, the orthographic projections of the first transistor T1, the second transistor T2, the second control signal line DS, and the gate line WS on the substrate are respectively located within the orthographic projection of the second part ELVDD-2 of the first power signal line on the substrate.

[0171] In the embodiments of this application, by setting the orthographic projection of the data line DL on the substrate to overlap with the orthographic projection of the first part ELVDD-1 of the first power signal line on the substrate, the orthographic projections of the first transistor T1, the second transistor T2, the second control signal line DS, and the gate line WS on the substrate are respectively located within the orthographic projection of the second part ELVDD-2 of the first power signal line on the substrate. On the one hand, the conductivity of the first power signal line ELVDD can be greatly improved, and the IR drop problem of the first power signal line ELVDD can be reduced. On the other hand, by setting the overlap, the design space of the pixel driving circuit can be greatly saved, and it is more conducive to the fabrication of display products with high PPI (Pixels Per Inch).

[0172] In some embodiments of this application, such as Figure 20 As shown, the first power signal line ELVDD also includes a third part ELVDD-3, the extension direction of the third part ELVDD-3 of the first power signal line intersects the extension direction of the first control signal line AZ; the third part ELVDD-3 of the first power signal line connects the first part ELVDD-1 of the first power signal line in two adjacent rows of sub-pixels together.

[0173] The orthographic projection of the third part of the first power signal line ELVDD-3 on the substrate overlaps with the orthographic projection of the data line DL on the substrate and the orthographic projection of the first control signal line AZ on the substrate.

[0174] In some embodiments of this application, the orthographic projection of the first portion ELVDD-1 and the third portion ELVDD-3 of the first power signal line on the substrate is a grid shape, and the sub-pixel is located in the closed area defined by the grid.

[0175] For example, the pattern formed by the first portion ELVDD-1 and the third portion ELVDD-3 of the first power signal line is a plurality of rings connected together;

[0176] For example, a ring can be a square ring;

[0177] Since the sub-pixels are located in the closed area defined by the grid, all components in the pixel driving circuit are located within the grid. In this way, the ring formed by the first part ELVDD-1 and the third part ELVDD-3 of the first power signal line separates the pixel driving circuits of two adjacent sub-pixels, shielding the signals of the pixel driving circuits of two adjacent sub-pixels and avoiding signal crosstalk between two adjacent sub-pixels. This improves the driving stability of the pixel driving circuit and enhances the display effect.

[0178] To save space in the arrangement of components and traces in the pixel driving circuit, the source (or drain) of one transistor can be shared with the source (or drain) of another transistor.

[0179] For example, within the same sub-pixel, such as Figure 9 As shown, the source of the driving transistor DMOS shares the drain of the second transistor T2 (marked at the DMOS-s / T2-d position); in the same row of sub-pixels perpendicular to the extension direction of the data line DL, two sub-pixels are divided into a group, and the drains of the two third transistors T3 in the same group of sub-pixels share the drain (marked at the T3-d position).

[0180] In some embodiments of this application, the array substrate includes a semiconductor layer AL located on the substrate, such as Figure 6 As shown, the semiconductor layer AL includes a first part aa-1, a second part aa-2, a third part aa-3, a fourth part aa-4, a fifth part aa-5, and a sixth part aa-6;

[0181] The area of ​​the fourth part aa-4 of the semiconductor layer AL projected onto the substrate is larger than the area of ​​the other parts projected onto the substrate.

[0182] The first part aa-1 of the semiconductor layer AL includes the source, drain and active region of the first transistor T1; the second part aa-2 of the semiconductor layer AL includes the source, drain and active region of the second transistor T2; the third part aa-3 of the semiconductor layer AL includes the source, drain and active region of the third transistor T3; the fourth part aa-4 of the semiconductor layer AL includes the source, drain and active region of the driving transistor DMOS; the fifth part aa-5 and the sixth part aa-6 are both electrically connected to the substrate.

[0183] For example, the orthographic projections of the first part aa-1, the second part aa-2, the third part aa-3, the fourth part aa-4, the fifth part aa-5, and the sixth part aa-6 of the semiconductor layer AL onto the substrate all include quadrilaterals.

[0184] For example, the first part aa-1, the second part aa-2, the fourth part aa-4, the fifth part aa-5, and the sixth part aa-6 of the semiconductor layer AL have the same extension direction, and the extension direction of the third part aa-3 of the semiconductor layer AL intersects with the extension directions of the other parts.

[0185] In a sub-pixel, for example, in the region where sub-pixel P1 is located, the second part aa-2 of semiconductor layer AL and the fourth part aa-4 of semiconductor layer AL are integrated structures; in the same row of sub-pixels perpendicular to the extension direction of data line DL, two sub-pixels are divided into a group (for example, including sub-pixel P1 and sub-pixel P2), and in the region where the same group of sub-pixels is located, the two third parts aa-3 of semiconductor layer AL are integrated structures.

[0186] The specific material of the semiconductor layer AL is not limited here. For example, the material of the semiconductor layer AL can be silicon, such as polycrystalline silicon.

[0187] For example, in the same group of sub-pixels (e.g., including sub-pixels P1 and P2), two third transistors T3 are symmetrically arranged, and two sixth portions aa-6 of the semiconductor layer AL are symmetrically arranged.

[0188] For example, when the third transistor T3 is an N-type transistor and the other transistors are P-type transistors, the substrate of the region where the third transistor T3 is located is a P-type silicon substrate, the substrate of the regions where the other transistors are located is an N-type silicon substrate, and the sixth part aa-6 of the semiconductor layer AL near the third transistor T3 is electrically connected to the region of the P-type silicon substrate, and the fifth part aa-5 of the semiconductor layer AL near the driving transistor DMOS is electrically connected to the region of the N-type silicon substrate.

[0189] In some embodiments of this application, such as Figure 8 As shown, the array substrate also includes a gate layer GT located on the side of the semiconductor layer AL away from the substrate.

[0190] The gate layer GT includes the gates of each transistor, for example, the gate gt-1 of the first transistor T1, the gate gt-2 of the second transistor T2, the gate gt-3 of the third transistor T3, and the gate gt-4 of the driving transistor DMOS; the area of ​​the gate of the driving transistor DMOS projected onto the substrate is larger than the area of ​​the gates of the other transistors projected onto the substrate.

[0191] The orthographic projection of the gate layer GT on the substrate partially overlaps with the orthographic projection of the semiconductor layer AL on the substrate; the area in the semiconductor layer AL that overlaps with the orthographic projection of the gate layer GT on the substrate is the active region (channel region) of each transistor, and the area in the semiconductor layer AL that does not overlap with the orthographic projection of the gate layer GT on the substrate is the source or drain of each transistor; the area of ​​the orthographic projection of the gate of the driving transistor DMOS on the substrate is larger than the area of ​​the orthographic projection of the gates of other transistors on the substrate.

[0192] For example, Figure 9The diagram provides a top view of the structure after the semiconductor layer AL and the gate layer GT are stacked; the upper and lower sides of the active regions of the first transistor T1, the second transistor T2, and the driving transistor DMOS are the source and drain, respectively; the left and right sides of the active region of the third transistor T3 are the source and drain, respectively.

[0193] For example, the driving transistor DMOS is located between the second transistor T2 and the third transistor T3, the first transistor T1 and the second transistor T2 are arranged adjacent to each other and their positions are staggered vertically, and the first transistor T1 is located on the side of the driving transistor DMOS away from the third transistor T3.

[0194] In an exemplary embodiment, the source and drain of each transistor can be doped to improve their conductivity; the doping element can be boron or the like.

[0195] For example, such as Figure 8 As shown, the black squares marked on the gates of each transistor represent the gate connection holes Via of each transistor. Each transistor is electrically connected to traces or other devices through its connection holes. For example, the first transistor T1 has a first connection hole Via-g1 with the gate layer GT facing upwards at the location of its gate gt-1, the second transistor T2 has a second connection hole Via-g2 with the gate layer GT facing upwards at the location of its gate gt-2, the third transistor T3 has a third connection hole Via-g3 with the gate layer GT facing upwards at the location of its gate gt-3, and the driving transistor DMOS has a fourth connection hole Via-g4 with the gate layer GT facing upwards at the location of its gate gt-14. The "connection hole with the gate layer facing upwards" mentioned above refers to the connection hole between the gate layer GT and other film layers on the side of the gate layer GT away from the substrate.

[0196] For example, the connection holes described above are filled with a conductive material, such as tungsten metal (e.g., W-Via).

[0197] In some embodiments of this application, the array substrate further includes a gate insulating layer (GI) that covers the gate layer GT and is located between the gate layer GT and the first conductive layer M1.

[0198] In some embodiments of this application, such as Figure 10 and Figure 11 As shown, the array substrate further includes a first conductive layer M1 located on the side of the gate layer GT away from the substrate; wherein, Figure 11 This is a top view of the semiconductor AL, with the gate layer GT and the first conductive layer M1 stacked together.

[0199] The first conductive layer M1 includes a third power signal line AVDD, a gate line WS, a second control signal line DS, and a second power signal line VSS. The voltage of the third power signal AVDD transmitted in the third power signal line AVDD is greater than the voltage of the second power signal VSS.

[0200] The third power signal line AVDD is electrically connected to the fifth part aa-5 of the semiconductor layer AL, and the second power signal line VSS is electrically connected to the sixth part aa-6 of the semiconductor layer AL.

[0201] The relationship between the voltage magnitudes of the third power signal AVDD transmitted in the third power signal line AVDD and the first power signal ELVDD transmitted in the first power signal line ELVDD is not limited here; it can be determined based on the circuit design in the array substrate.

[0202] For example, in combination Figure 11 and Figure 27 As shown, the orthographic projection of the third power signal line AVDD on the substrate overlaps with the orthographic projection of the driving transistor DMOS on the substrate.

[0203] For example, such as Figure 11 As shown, the second power signal line VSS is located on the side of the third transistor T3 away from the driving transistor DMOS. Since the second power signal line VSS is electrically connected to the drain of the third transistor T3, the second power signal line VSS and the third transistor T3 can be arranged adjacent to each other to save design space.

[0204] The size of the pattern area of ​​the fifth part aa-5 and the sixth part aa-6 of the semiconductor layer AL is not limited here; for example, the pattern area of ​​the fifth part aa-5 of the semiconductor layer AL is larger than that of the sixth part aa-6 of the semiconductor layer AL; or, for another example, the pattern area of ​​the fifth part aa-5 of the semiconductor layer AL is less than or equal to that of the sixth part aa-6 of the semiconductor layer AL; the specific size can be determined according to the electrical connection requirements of the design space.

[0205] The following example, using a silicon substrate, illustrates the substrate requirements for different types of transistors (MOS transistors): When the third transistor T3 is an N-type transistor and the other transistors are P-type transistors, the silicon substrate in the region where the third transistor T3 is located is a P-type silicon substrate, and the silicon substrate in the regions where the other transistors are located is an N-type silicon substrate. The fifth part aa-5 of semiconductor layer AL is electrically connected to the region of the N-type silicon substrate, and the sixth part aa-6 of semiconductor layer AL is electrically connected to the region of the P-type silicon substrate. Furthermore, by setting the fifth part aa-5 of semiconductor layer AL to be electrically connected to the third power signal line AVDD, and setting the sixth part aa-6 of semiconductor layer AL to be electrically connected to the second power signal line VSS, the third power signal line AVDD provides the AVDD potential to the region of the N-type silicon substrate, and the second power signal line VSS provides the VSS potential to the region of the P-type silicon substrate. The AVDD potential is greater than the VSS potential. For example, the AVDD potential can be a positive voltage potential, and the VSS potential can be a ground potential or a negative voltage potential. Alternatively, the AVDD potential can be a high-level potential, and the VSS potential can be a low-level potential.

[0206] In some embodiments of this application, combined with Figure 10 and Figure 27 As shown, in the region where the same row of sub-pixels is located perpendicular to the extension direction of the data line DL, the third power signal line packet AVDD includes a first segment XD1 and multiple second segments XD2. The first segment XD1 is connected to each of the second segments XD2 respectively. The second segments XD2 are electrically connected to the fifth part aa-5 of the semiconductor layer AL. The extension direction of the first segment XD1 intersects with the extension direction of the data line DL. The extension direction of each of the second segments XD2 is consistent with the extension direction of the data line DL. The orthographic projection of the first segment XD on the substrate overlaps with the orthographic projection of the driving transistor DMOS on the substrate. The orthographic projection of the second segment XD2 on the substrate overlaps with the orthographic projection of the fifth part aa-5 of the semiconductor layer AL on the substrate.

[0207] For example, consistent extension direction can include parallel extension direction; the description of consistent extension direction in the following text is similar to the meaning here, and will not be repeated here;

[0208] It should be noted that the term "parallel" as used in this specification refers to a broad definition, which means that the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, it also includes the state where the angle is greater than -5° and less than 5°.

[0209] For example, such as Figure 27 As shown, the shape of the orthographic projection of the third power signal line AVDD on the substrate can be similar to that of a fence or enclosure.

[0210] In some embodiments of this application, combined with Figure 10 and Figure 27 As shown, in the region of the same row of sub-pixels perpendicular to the extension direction of the data line DL, the second power signal line VSS includes a third segment XD3, multiple fourth segments XD4, and multiple fifth segments XD5. The third segment XD3 is connected to each of the fourth segments XD4 and each of the fifth segments XD5 respectively. The fourth segment XD4 is electrically connected to the drain of the third transistor T3. The fifth segment XD5 is electrically connected to the sixth part aa-6 of the semiconductor layer AL. The extension directions of each fourth segment XD4 and each fifth segment XD5 are consistent with the extension direction of the data line DL. The extension direction of the third segment XD3 intersects with the extension direction of the data line DL. The orthographic projection of the fifth segment XD5 on the substrate overlaps with the orthographic projection of the sixth part aa-6 of the semiconductor layer AL on the substrate.

[0211] In some embodiments of this application, such as Figure 10 As shown, the first conductive layer M1 further includes a first connecting portion M1-1, a second connecting portion M1-2, and a third connecting portion M1-3;

[0212] like Figure 11 As shown, the first connection part M1-1 is electrically connected to the source of the third transistor T3 and the drain of the driving transistor DMOS, respectively.

[0213] like Figure 11 As shown, the second connection part M1-2 is electrically connected to the gate of the driving transistor DMOS and the drain of the first transistor T1, respectively.

[0214] Combination Figure 7 , Figure 11 and Figure 13 As shown, the third connection part M1-3 is electrically connected to the source of the first transistor T1 and the data line DL respectively; the orthographic projection of the third connection part M1-3 on the substrate overlaps with the orthographic projection of the first part ELVDD-1 of the first power signal line on the substrate.

[0215] In some embodiments, such as Figure 7 As shown, the first connecting part M1-1 includes a first part and a second part, wherein, in Figure 7 In the diagram, the first part and the second part of the first connecting part M1-1 are divided by a dashed line segment. For example, the part above the dashed line segment is the first part of the first connecting part M1-1, and the part below the dashed line segment is the second part of the first connecting part M1-1.

[0216] The orthographic projection of the first part of the first connection portion M1-1 on the substrate overlaps with the orthographic projection of the gate of the third transistor T3 on the substrate, and the extension direction of the overlapping portion is the same as the extension direction of the first trace M2-1; the orthographic projection of the second part of the first connection portion M1-1 on the substrate overlaps with the orthographic projection of the drain of the driving transistor DMOS on the substrate, and the extension direction of the overlapping portion intersects with the extension direction of the first trace M2-1.

[0217] In some embodiments, such as Figure 7 As shown, both the first and second parts of the first connecting part M1-1 are L-shaped (with... Figure 7 The dashed line segment shown divides the two parts), and the connection between the first part and the second part of the first connecting part M1-1 (as shown in the figure) Figure 7 The minimum distance h5 between the location of the bid price (the dotted line segment) and the first trace M2-1 is less than the minimum distance h6 between the connection point and the drain of the driving transistor.

[0218] like Figure 7 As shown, the first trace M2-1 is located between the first connector M1-1 and the data line DL; along the extension direction of the first control signal line AZ, the distance h7 between the first trace M2-1 and the data line DL is less than the distance h5 between the first trace M2-1 and the first connector M1-1.

[0219] like Figure 7 As shown, the second connection part M1-2 includes a first part (e.g., a part extending vertically) extending along the extension direction of the data line DL and a second part (e.g., a part extending horizontally) extending along the extension direction of the first control signal line AZ.

[0220] The second part of the second connection part M1-2 overlaps with the orthographic projection of the source of the first transistor T1 onto the substrate. The extension line of the first part of the second connection part M1-2 is located on the side of the second part of the second connection part M1-2 closer to the driving transistor DMOS.

[0221] In some embodiments, such as Figure 7 As shown, the orthographic projection of one end of the third connection part M1-3 on the substrate overlaps with the orthographic projection of the source of the first transistor T1 on the substrate, and the orthographic projection of the other end of the third connection part M1-3 on the substrate overlaps with the orthographic projection of the data line DL on the substrate; and the area of ​​the region where the third connection part M1-3 overlaps with the source of the first transistor T1 is greater than the area of ​​the region where it overlaps with the data line DL.

[0222] In an exemplary embodiment, the location marked with a black box is a connection hole, wherein, combined with Figure 10 and Figure 11 As shown, each connection hole is a connection hole with the first conductive layer M1 facing downwards, for example, a connection hole between the first conductive layer M1 and the semiconductor layer AL or a connection hole between the first conductive layer M1 and the gate layer GT.

[0223] For example, the connection hole Via-M1 / AL provided on the second segment XD2 of the third power signal line AVDD is the connection hole between the second segment XD2 and the fifth part aa-5 of the semiconductor layer AL.

[0224] For example, the connection hole Via-T3-d provided on the fourth segment XD4 of the second power signal line VSS is the connection hole between the second power signal line VSS and the drain of the third transistor T3.

[0225] For example, the connection hole Via-M1 / AL provided on the fifth segment XD5 of the second power signal line VSS is the connection hole between the second power signal line VSS and the sixth part aa-6 of the semiconductor layer AL.

[0226] For example, each connection hole provided on the gate line WS is a connection hole between the gate line WS and the gate of each first transistor T1;

[0227] For example, each connection hole provided on the second control signal line DS is a connection hole between the second control signal line DS and the gate of each second transistor T2;

[0228] For example, the two connection holes on the first connection part M1-1 are electrically connected to the source of the third transistor T3 and the drain of the driving transistor DMOS, respectively.

[0229] For example, the two connection holes on the second connection part M1-2 are electrically connected to the gate of the driving transistor DMOS and the drain of the first transistor T1, respectively.

[0230] For example, the two connection holes on the third connection part M1-3 are electrically connected to the source of the first transistor T1 and the data line DL, respectively;

[0231] Each connection hole is filled with a conductive material, such as a metal material, which may include tungsten (W).

[0232] In some embodiments of this application, such as Figure 1 As shown, the pixel driving circuit also includes a compensation module 3, which is electrically connected to the first node G, the second node S and the first power signal line ELVDD, and is configured to compensate the threshold voltage of the driving module 2.

[0233] The compensation module 3 includes a first capacitor C1 and a second capacitor C2. The first plate of the first capacitor C1 is electrically connected to the source of the driving transistor DMOS, and the second plate of the first capacitor C1 is electrically connected to the gate of the driving transistor DMOS. The first plate of the second capacitor C2 is electrically connected to the source of the driving transistor DMOS, and the second plate of the second capacitor C2 is electrically connected to the first power signal line ELVDD.

[0234] In some embodiments of this application, such as Figure 14 As shown, the first part of the first power signal line ELVDD-1, the first control signal line AZ, and the second plate C1-DJ2 of the first capacitor are arranged on the same layer.

[0235] In some embodiments of this application, the orthographic projection of the first capacitor C1 on the substrate overlaps with the orthographic projection of the driving transistor DMOS on the substrate, and the orthographic projection of the second capacitor C2 on the substrate overlaps with the orthographic projection of the driving transistor DMOS on the substrate; the second capacitor C2 is located on the side of the first capacitor C1 away from the driving transistor DMOS.

[0236] In the embodiments of this application, by setting the driving transistor DMOS, the first capacitor C1 and the second capacitor C2 in a stacked configuration, the design space of the pixel driving circuit can be greatly saved, and it is more conducive to the fabrication of display products with high PPI (Pixels Per Inch).

[0237] In some embodiments of this application, the array substrate further includes a second conductive layer M2 located on the side of the first conductive layer M1 away from the substrate, combined with Figure 12 and Figure 13 As shown, the second conductive layer M2 includes a data line DL and a first conductive pattern M2-C, and the first conductive pattern M2-C is electrically connected to the source of the driving transistor DMOS.

[0238] The second conductive layer M2 also includes a first trace M2-1 and a second trace M2-2. The first trace M2-1 is electrically connected to the gate of the third transistor T3 and the first control signal line AZ, respectively. The second trace M2-2 is electrically connected to the source of the second transistor T2 and the first power signal line ELVDD, respectively.

[0239] The shape of the orthographic projection of the first conductive pattern M2-C onto the substrate is not limited here;

[0240] For example, the shape of the orthographic projection of the first conductive pattern M2-C on the substrate may include a polygon, an arc, or a combination of polygons and arcs; wherein, the combination of polygons and arcs includes a pattern formed by splicing polygons and arcs, or a pattern formed by removing a portion of a polygon or arc; polygons may include triangles, quadrilaterals, pentagons, etc., and arcs may include sectors, circles, ellipses, semicircles, etc.

[0241] For example, such as Figure 12 As shown, the shape of the orthographic projection of the first conductive pattern M2-C on the substrate can be a region that has been removed from a rectangle. The removed region can be a polygon or an arc.

[0242] Among them, such as Figure 12 As shown, a connection hole Via (DMOS-gt / C1-DJ2) is provided in the area removed from the first conductive pattern M2-C. This hole is used to electrically connect the gate of the driving transistor DMOS to the second plate of the first capacitor C1. In order to avoid a short circuit between the first conductive pattern M2-C and the second plate of the first capacitor C1, this area is removed so that the first conductive pattern M2-C avoids the connection hole Via (DMOS-gt / C1-DJ2).

[0243] For example, the first conductive pattern M2-C can be used as part of the first plate of the first capacitor C1; another part of the first plate of the first capacitor C1 can be electrically connected to the first conductive pattern M2-C through the connection hole Via (M2-M4) and the third trace M-3. The description of the other part of the first plate of the first capacitor C1 can be found in the following description.

[0244] For example, the first conductive pattern M2-C can be used as part of the first plate of the second capacitor C2; the other part of the first plate of the second capacitor C2 can be electrically connected to the first conductive pattern M2-C through the connection hole Via (M2-M4) and the third trace M-3. The description of the other part of the first plate of the second capacitor C2 can be found in the following description.

[0245] For example, the first conductive pattern M2-C can simultaneously serve as part of the first plate of the first capacitor C1 and part of the first plate of the second capacitor C2;

[0246] For example, such as Figure 12 As shown, the first conductive pattern M2-C can be electrically connected to the source of the driving transistor DMOS through the connection hole Via (DMOS-s) so that the first conductive pattern M2-C has the source potential of the driving transistor DMOS.

[0247] In some embodiments of this application, the array substrate further includes a third conductive layer M3 located on the side of the second conductive layer M2 away from the substrate. The third conductive layer M3 includes a first control signal line AZ, a second electrode C1-DJ2 of the first capacitor C1, and a first portion ELVDD-1 of the first power signal line.

[0248] For example, such as Figure 15 As shown, the extension directions of the first control signal line AZ and the data line DL intersect, and the orthographic projection of the first control signal line AZ on the substrate overlaps with the orthographic projection of the third transistor T3 on the substrate.

[0249] For example, the orthographic projection of the first control signal line AZ on the substrate partially overlaps with the orthographic projection of the second power signal line VSS on the substrate; or, there may be a gap between the orthographic projection of the first control signal line AZ on the substrate and the orthographic projection of the second power signal line VSS on the substrate.

[0250] For example, in combination Figure 15 , Figure 12 and Figure 13 As shown, the first control signal line AZ is electrically connected to the gate of the third transistor T3 through the first trace M2-1 in the second conductive layer M2;

[0251] For example, such as Figure 14 As shown, the second plate C1-DJ2 of the first capacitor C1 is electrically connected to the gate of the driving transistor DMOS through the connection hole Via(DMOS-gt / C1-DJ2);

[0252] For example, in combination Figure 14 and Figure 20 As shown, for example, in the region where the first portion of the first power signal line ELVDD-1 is located, the orthographic projection of the first portion of the first power signal line ELVDD-1 on the substrate is a series of connected "U" shapes. Specifically, the orthographic projection of the first portion of the first power signal line ELVDD-1 in a sub-pixel onto the substrate is a "U" shape. It should be noted that... Figure 14 In the drawing, only the first part of the first power signal line ELVDD-1 between two adjacent sub-pixels is drawn, and the complete structure of the first part of the first power signal line ELVDD-1 is not drawn.

[0253] For example, in combination Figure 14 and Figure 20As shown, in the region of the same row of sub-pixels perpendicular to the extension direction of the data line DL, the first part of the first power signal line ELVDD-1 includes a sixth segment XD6 and multiple seventh segments XD7. Each seventh segment XD7 is connected to the sixth segment XD6. The seventh segment XD7 is located between the second plates C1-DJ2 of two adjacent first capacitors C1. The sixth segment XD6 is located on the side of the second plates C1-DJ2 of each first capacitor C1 away from the first control signal line AZ. The extension direction of the sixth segment XD6 is consistent with that of the first control signal line ZA.

[0254] For example, in combination Figure 15 and Figure 20 As shown, the orthographic projection of the sixth line segment XD6 on the substrate overlaps with the orthographic projection of the first transistor T1 on the substrate, and the orthographic projection of the seventh line segment XD7 on the substrate overlaps with the orthographic projection of the data line DL on the substrate.

[0255] For example, the line width of the seventh segment XD7 included in the first part ELVDD-1 of the first power signal line is greater than or equal to the line width of the data line DL.

[0256] For example, the line width of the seventh segment XD7 included in the first part ELVDD-1 of the first power signal line is greater than or equal to the line width of the first control signal line AZ;

[0257] For example, the line width of the seventh segment XD7 included in the first part ELVDD-1 of the first power signal line is greater than or equal to the line width of the sixth segment XD6 included in the first part ELVDD-1 of the first power signal line.

[0258] For example, the source of the second transistor T2 can be directly connected to the seventh segment XD7;

[0259] For example, the source of the second transistor T2 can be directly connected to the sixth segment XD6;

[0260] In the accompanying drawings provided in the embodiments of this application, the source of the second transistor T2 is directly connected to the sixth line segment XD6 as an example for drawing and illustration;

[0261] In the embodiments of this application, by setting the first part of the first power signal line ELVDD-1 to include a sixth segment XD6 and a plurality of seventh segments XD7, and such that the seventh segment XD7 is located between the second plates C1-DJ2 of two adjacent first capacitors C1, wherein the second plates C1-DJ2 of the first capacitors C1 have the gate potential of the driving transistor DMOS, the electrical signal crosstalk between the second plates C1-DJ2 of two adjacent first capacitors C1 is avoided, thereby avoiding the electrical signal crosstalk between the gates of the driving transistors DMOS of two adjacent sub-pixels, improving the signal stability of the pixel driving circuit, and improving the display effect of the array substrate.

[0262] In some embodiments of this application, the array substrate further includes a capacitive conductive layer MIM located on the side of the third conductive layer M3 away from the substrate, such as... Figure 16 As shown, the capacitor conductive layer MIM includes a second conductive pattern MIM-C. The orthographic projection of the second conductive pattern MIM-C on the substrate overlaps with the orthographic projection of the first conductive pattern M2-C on the substrate, and the second conductive pattern MIM-C and the first conductive pattern M2-C are indirectly electrically connected.

[0263] For example, the second conductive pattern MIM-C is electrically connected to the fourth conductive layer M4 through an upward-facing connection hole;

[0264] The indirect electrical connection between the second conductive pattern MIM-C and the first conductive pattern M2-C refers to the fact that the second conductive pattern MIM-C and the first conductive pattern M2-C are electrically connected through other electrodes or components, and both have the same potential. For example, since the first conductive pattern M2-C is electrically connected to the source of the driving transistor DMOS, and the second conductive pattern MIM-C is indirectly connected to the first conductive pattern M2-C, both the second conductive pattern MIM-C and the first conductive pattern M2-C have the source potential of the driving transistor DMOS.

[0265] It should be noted that the orthographic projection of the second conductive pattern MIM-C on the substrate partially overlaps with the orthographic projection of the first conductive pattern M2-C on the substrate. Additionally, in conjunction with... Figure 12 , Figure 16 and Figure 17 As shown, the orthographic projection of the second conductive pattern MIM-C on the substrate and the orthographic projection of the connection via Via (DMOS-gt / C1-DJ2) on the substrate do not overlap; wherein, as Figure 17 As shown, the connection via Via (DMOS-gt / C1-DJ2) is located in the area where the first conductive pattern M2-C has been removed;

[0266] The shape of the orthographic projection of the second conductive pattern MIM-C onto the substrate is not limited here;

[0267] For example, the shape of the orthographic projection of the second conductive pattern MIM-C on the substrate may include a polygon, an arc, or a combination of polygons and arcs; wherein, the combination of polygons and arcs includes a pattern formed by splicing polygons and arcs, or a pattern formed by removing a portion of a polygon or arc; polygons may include triangles, quadrilaterals, pentagons, etc., and arcs may include sectors, circles, ellipses, semicircles, etc.

[0268] For example, such as Figure 17 As shown, the orthographic projection of the second conductive pattern MIM-C onto the substrate can be rectangular.

[0269] In some embodiments of this application, such as Figure 18 As shown, the array substrate also includes a fourth conductive layer M4 located on the side of the capacitive conductive layer MIM away from the substrate. The fourth conductive layer M4 includes a third conductive pattern M4-C, which is electrically connected to the first conductive pattern M2-C and to the second conductive pattern MIM-C.

[0270] For example, such as Figure 18 As shown, the third conductive pattern M4-C is electrically connected to the first conductive pattern M2-C through the connecting hole Via (M2-M4);

[0271] For example, the third conductive pattern M4-C is electrically connected to the second conductive pattern MIM-C through the connection hole Via (MIM-M4);

[0272] In this configuration, the first conductive pattern M2-C, the second conductive pattern MIM-C, and the third conductive pattern M4-C together serve as the first electrode of the first capacitor C1 and the first electrode of the second capacitor C2. At this time, the first capacitor C1 and the second capacitor C2 are connected in series, and the first electrode of the first capacitor C1 and the first electrode of the second capacitor C2 have the same potential. The first conductive pattern M2-C, the second conductive pattern MIM-C, and the third conductive pattern M4-C, connected in series, serve as both the first electrode of the first capacitor C1 and the first electrode of the second capacitor C2. Thus, while ensuring the normal operation of the pixel driving circuit, this increases the capacitance of the capacitors and saves design space on the array substrate, which is beneficial for manufacturing high PPI display products.

[0273] In some embodiments of this application, combined with Figure 18 and Figure 19 As shown, the fourth conductive layer M4 also includes the third part of the first power signal line, ELVDD-3, and the adapter cable M4-1;

[0274] like Figure 20 As shown, the third part of the first power signal line, ELVDD-3, electrically connects the seventh segment XD7 in the two adjacent rows of sub-pixels together. The adapter line M4-1 is electrically connected to the sixth segment XD6 (the first part of the first power signal line, ELVDD-1, includes the sixth segment XD6) and the second part of the first power signal line, ELVDD-2, respectively. The orthographic projection of the adapter line M4-1 on the substrate overlaps with the orthographic projection of the sixth segment XD6 on the substrate.

[0275] For example, in combination Figure 18 and Figure 14 As shown, the adapter cable M4-1 is electrically connected to the sixth segment XD6 in the first part of the first power signal line ELVDD-1 through the connection hole Via (M3-M4);

[0276] For example, in combination Figure 18 and Figure 20 As shown, adapter cable M4-1 is electrically connected to the second part of the first power signal line ELVDD-2 through connection hole Via (M4 / TM);

[0277] For example, the extension direction of adapter cable M4-1 is the same as the extension direction of the sixth segment XD6;

[0278] The relationship between the line widths of the aforementioned adapter M4-1 and the sixth line segment XD6 is not limited here. For example, the line width of the adapter M4-1 may be less than or equal to the line width of the sixth line segment XD6; or the line width of the adapter M4-1 may be greater than the line width of the sixth line segment XD6.

[0279] It should be noted that in this specification, for example, Via(M2-M3) refers to the connection hole between the second conductive layer M2 and the third conductive layer M3, and Via(T3-AN) is the connection hole between the third transistor T3 and the anode AN. The naming method for other connection holes is similar and will not be repeated.

[0280] In some embodiments of this application, such as Figure 22 and Figure 24 As shown, the array substrate also includes a fifth conductive layer M5 (or CTOP) located on the side of the fourth conductive layer M4 away from the substrate, and a sixth conductive layer M6 (or TM) located on the side of the fifth conductive layer M5 away from the substrate.

[0281] The fifth conductive layer CTOP includes the second electrode C2-DJ2 of the second capacitor C2, and the sixth conductive layer TM includes the second part ELVDD-2 of the first power signal line and the auxiliary anode ANF. The second electrode C2-DJ2 of the second capacitor C2 is electrically connected to the second part ELVDD-2 of the first power signal line. The orthographic projection of the auxiliary anode ANF on the substrate overlaps with the orthographic projections of the third transistor T3 and the driving transistor DMOS on the substrate.

[0282] Since the second electrode C2-DJ2 of the second capacitor C2 is the uppermost electrode on the array substrate (the electrode with the greatest distance from the substrate), the fifth conductive layer can be the CTOP layer.

[0283] For example, in combination Figure 22 and Figure 24 As shown, the second plate C2-DJ2 of the second capacitor C2 is electrically connected to the second part ELVDD-2 of the first power signal line through the connection hole Via (CTOP / TM);

[0284] For example, in combination Figure 19 and Figure 23 As shown, the orthographic projection of the second plate C2-DJ2 of the second capacitor C2 onto the substrate is located within the orthographic projection of the third conductive pattern M4-C onto the substrate; for example, the orthographic projection area of ​​the second plate C2-DJ2 of the second capacitor C2 onto the substrate is less than or equal to the orthographic projection area of ​​the third conductive pattern M4-C onto the substrate.

[0285] For example, such as Figure 20 and Figure 24 As shown, the orthographic projection of the second part of the first power signal line ELVDD-2 on the substrate can be a "U" shape. In the region corresponding to the sub-pixel in the same row, the orthographic projection of the second part of the first power signal line ELVDD-2 on the substrate can be multiple "U" shapes connected together.

[0286] For example, in the region corresponding to the sub-pixels in the same row, the orthographic projection pattern of the second part of the first power signal line ELVDD-2 on the substrate can be comb-shaped;

[0287] For example, such as Figure 26 As shown, the orthographic projection of the auxiliary anode ANF on the substrate overlaps with the driving transistor DMOS portion, the orthographic projection of the auxiliary anode ANF on the substrate overlaps with the third transistor T3 portion, the orthographic projection of the auxiliary anode ANF on the substrate overlaps with the first capacitor C1 portion, and the orthographic projection of the auxiliary anode ANF on the substrate overlaps with the second capacitor C2 portion.

[0288] For example, such as Figure 26 As shown, the orthographic projection of the auxiliary anode ANF on the substrate overlaps with the orthographic projection of the first control signal line AZ on the substrate.

[0289] For example, such as Figure 24 As shown, the auxiliary anode ANF is located in the area enclosed by the second part ELVDD-2 of the "U"-shaped first power signal line. In this way, the second part ELVDD-2 of the first power signal line can avoid signal interference or crosstalk between the auxiliary anode ANF in two adjacent sub-pixels, thereby improving the driving stability of the pixel driving circuit and improving the display effect.

[0290] In some embodiments of this application, such as Figure 21 and Figure 24 As shown, in the region where the same row of sub-pixels is located perpendicular to the extension direction of the data line DL, the orthographic projection of the second part ELVDD-2 of the first power signal line on the substrate is comb-shaped, and the area of ​​the orthographic projection of the second part ELVDD-2 of the first power signal line on the substrate is larger than the area of ​​the orthographic projection of the first part ELVDD-1 of the first power signal line on the substrate.

[0291] The comb-shaped part resembles the shape of a comb, including multiple teeth and a back that connects the teeth.

[0292] In some embodiments of this application, such as Figure 21 and Figure 24 As shown, in the region where the same row of sub-pixels is located perpendicular to the extension direction of the data line DL, the second part of the first power signal line ELVDD-2 includes a main extension Comb-Z and multiple branch extensions Comb-F; wherein, the main extension Comb-Z is equivalent to the back of a comb, and the multiple branch extensions Comb-F are equivalent to the teeth of a comb.

[0293] like Figure 26 and Figure 28 As shown, the orthographic projection of the main extension Comb-Z on the substrate covers the orthographic projections of the first transistor T1, the second transistor T2, the gate line WS, the second control signal line DS, and the sixth line segment XD6 on the substrate. The branch extension Comb-F is located in the area between two adjacent auxiliary anodes ANF. The branch extension Comb-F overlaps with the orthographic projections of the seventh line segment XD7 and the data line DL on the substrate.

[0294] For example, the main extension Comb-Z intersects the extension direction of the branch extension Comb-F, and the main extension Comb-Z connects multiple branch extensions Comb-F together.

[0295] For example, the area of ​​the main extension Comb-Z projected onto the substrate is greater than the sum of the areas of the first transistor T1 and the second transistor T2 projected onto the substrate.

[0296] For example, the orthogonal projection of the main extension Com-Z onto the silicon substrate covers the source of the driving transistor DMOS;

[0297] For example, two adjacent first control signal lines AZ divide the data line DL into multiple data line segments, wherein the orthographic projection of the data line segment on the substrate overlaps with the orthographic projection of the branch extension Comb-F on the substrate.

[0298] For example, the projected area of ​​the data line segment on the substrate is less than or equal to the projected area of ​​the branch extension Comb-F on the substrate.

[0299] For example, the line width of the data line segment is less than or equal to the line width of the branch extension Comb-F;

[0300] For example, such as Figure 28 As shown, each branch extension Comb-F overlaps with the orthographic projection of the third portion ELVDD-3 of a first power signal line on the substrate; in the same row of sub-pixels, the number of the third portion ELVDD-3 of the first power signal line is the same as the number of branch extensions Comb-F.

[0301] In the embodiments of this application, by setting the shape of the orthographic projection of the second part ELVDD-2 of the first power signal line on the substrate to be comb-shaped, and the second part ELVDD-2 of the first power signal line includes a main extension Comb-Z and multiple branch extensions Comb-F, with the auxiliary anode ANF located between two adjacent branch extensions Comb-F; in this way, signal interference or crosstalk between the auxiliary anodes ANF in two adjacent sub-pixels can be largely avoided, thereby improving the driving stability of the pixel driving circuit and improving the display effect; in addition, by setting the orthographic projection of the main extension Comb-Z on the substrate to cover the orthographic projection of the first transistor T1, the second transistor T2, the gate line WS, the second control signal line DS, and the sixth segment XD6 on the substrate, the size and area of ​​the first power signal line ELVDD are greatly increased, thereby improving the conductivity of the first power signal line ELVDD, reducing the occurrence of IR drop problems, improving the voltage stability of the signal transmitted by the first power signal line ELVDD, thereby improving the driving stability of the pixel driving circuit array, improving the light emission stability and uniformity of the sub-pixel array, and improving the display effect.

[0302] In an exemplary embodiment, the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the capacitor conductive layer MIM, the fourth conductive layer M4, the fifth conductive layer CTOP, and the sixth conductive layer TM can also be referred to as the first metal layer Metal1, the second metal layer Metal2, the third metal layer Metal3, the capacitor conductive layer MIM used to form the MIM (Metal-Insulator-Metal, abbreviated as MIM) capacitor structure, the fourth metal layer Metal4, the capacitor top plate layer CTOP, and the top metal layer TM, respectively.

[0303] For example, the gate layer GT, the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the capacitor conductive layer M1, the fourth conductive layer M4, the fifth conductive layer CTOP, and the sixth conductive layer TM can be made of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo); or, they can be made of alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb); the alloy material can be a single-layer structure; or it can be a multi-layer composite structure, such as a stacked structure composed of Mo layer, Cu layer, and Mo layer;

[0304] An insulating layer is provided between each two adjacent conductive layers. The material of the insulating layer can be silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), etc. The insulating layer can be a single-layer structure or a multi-layer composite structure.

[0305] In addition, the number of connection holes (also known as vias) on the insulating layer between each conductive layer in the embodiments of this application can be determined according to actual needs, and is not limited here;

[0306] In local areas, to improve the conductivity stability between connecting lines or components of different film layers, multiple vias filled with conductive material can be set between two conductive structures. The number of vias shown in the accompanying drawings does not represent a limitation on the number of vias, but is merely an illustrative example.

[0307] The shape and arrangement of multiple vias are not limited here;

[0308] For example, the planar shape of the via can be rectangular, circular, or elliptical, and the dimensions of multiple vias can be the same or different.

[0309] The array substrate provided in the embodiments of this application may further include a pixel definition layer, an organic light-emitting layer, a cathode, a common electrode layer, a first encapsulation layer, a color filter structure layer, and a second encapsulation layer, etc. For details, please refer to the description in the related technology, which will not be repeated here.

[0310] Figure 25 It shows Figure 1 The signal timing diagram of the pixel driving circuit operation process shown is as follows: Figure 25 As shown, the operation of the pixel driving circuit includes four stages.

[0311] The following is based on Figure 1 Taking the pixel driving circuit shown as an example where all transistors are P-type MOS transistors, combined with... Figure 25 The signal timing diagram shown illustrates the working principle of this pixel driving circuit.

[0312] 1. In the first stage H1 (Vofs write stage, also known as the initialization stage), such as... Figure 25 As shown, a low-level second control signal is input to the second control signal line DS, a low-level gate drive signal (also known as a scan signal) is input to the gate line WS, and a low-level first control signal is input to the first control signal line AZ.

[0313] like Figure 2 As shown, the transistor connected to the second control signal line DS receives a low-level second control signal, the transistor connected to the gate line WS receives a low-level gate drive signal, the transistor connected to the first control signal line AZ receives a low-level first control signal, the data line DL receives the Vofs voltage signal, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on, the first node G writes the voltage value of Vofs, and the second node S writes the voltage value of Vdd. At this time, Vini = Vdd - Vofs.

[0314] 2. In the second stage H2 (self-discharge threshold voltage reading stage), such as Figure 25 As shown, a high-level second control signal is input to the second control signal line DS, a high-level gate drive signal is input to the gate line WS, and a low-level first control signal is input to the first control signal line AZ.

[0315] like Figure 3 As shown, the transistor connected to the second control signal line DS receives a high-level second control signal, the transistor connected to the gate line WS receives a high-level gate drive signal, and the transistor connected to the first control signal line AZ receives a low-level first control signal; the first transistor T1 and the second transistor T2 are cut off, and the third transistor T3 is turned on; since the first node G is floating, under the action of the first capacitor C1, the voltage of the first node G changes with the voltage of the second node S. In this way, the voltage difference between the first node G and the second node S remains unchanged in the previous stage, that is, Vgs = Vini = Vdd - Vofs;

[0316] Under the influence of the back-gate effect, |V TH-EF |=a*(Vdd-Vs)+|V TH| where a is the coefficient of the back-gate effect, and Vs is the voltage at the second node S. As the voltage Vs at the second node S decreases, since Vgs remains constant at Vini, then |V TH-EF When the value increases to Vini, the discharge drive transistor DMOS is turned off. At this time:

[0317] a*(Vdd-Vs)+|V TH |=Vini=Vdd-Vofs;

[0318] Then Vs = Vdd + (|V TH -Vini) / a;

[0319] Vg = Vdd - Vini + (|V TH |-Vini) / a.

[0320] 3. In the third stage H3 (Vdata writing and threshold compensation stage), such as Figure 25 As shown, a high-level second control signal is input to the second control signal line DS, a low-level gate drive signal is input to the gate line WS, and a low-level first control signal is input to the first control signal line AZ.

[0321] like Figure 4 As shown, the transistor connected to the second control signal line DS receives a high-level second control signal, the transistor connected to the gate line WS receives a low-level gate drive signal, and the transistor connected to the first control signal line AZ receives a low-level first control signal. The first transistor T1 and the third transistor T3 are turned on, and the second transistor T2 is turned off. At this time, the first node G writes the Vdata signal, and the voltage of the first node G changes from Vofs to Vdata. Since the second node S is floating, the voltage change value of the second node S is ΔVs.

[0322] ΔVs=(1-b)*Vg, where b=C2 / (C1+C2);

[0323] ΔVg=Vdata-Vdd+Vini-(|V TH |-Vini) / a

[0324] =Vdata - Vdd + Vini + (Vini - |V TH |) / a;

[0325] Then, ΔVs=(1-b)*[Vdata-Vdd+Vini+(Vini-|V TH |) / a];

[0326] Then, at this time, the voltage at the second node S is:

[0327] Vdd-(Vini-|VTH |) / a+ΔVs

[0328] =Vdd-(Vini-|V TH |) / a+(1-b)*[Vdata-Vdd+Vini+(Vini-|V TH ) / a]

[0329] =Vdata+Vini-bVdata+bVdd*b(Vini-|V TH ) / a-bVini;

[0330] Then |Vgs|=(1-b / ab)*Vini+b|V TH | / a+b(Vdd-Vdata).

[0331] 4. In the fourth stage H4 (luminescent stage), such as Figure 25 As shown, a low-level second control signal is input to the second control signal line DS, a high-level gate drive signal is input to the gate line WS, and a high-level first control signal is input to the first control signal line AZ;

[0332] like Figure 5 As shown, the transistor connected to the second control signal line DS receives a low-level second control signal, the transistor connected to the gate line WS receives a high-level gate drive signal, the transistor connected to the first control signal line AZ receives a high-level first control signal, the first transistor T1 and the third transistor T3 are turned off, the second transistor T2 is turned on, and the driving transistor DMOS is turned on.

[0333] During the stage when the light-emitting device 6 emits light, the current in the light-emitting path from the second node S to the anode is:

[0334]

[0335] As can be seen from the above formula, the current in the light-emitting path between the second node S and the anode is independent of the threshold voltage VTH of the driving transistor DMOS.

[0336] It should be noted that, in Figures 2-5 In the diagram, "×" indicates that the transistor is in the off state, and "√" indicates that the transistor is in the on state. Additionally, at the nodes of the pixel driving circuit (e.g., the first node G, the second node S) and at the signal line input terminals of the pixel driving circuit, "H" indicates that the signal at that location is a high-level signal, and "L" indicates that the signal at that location is a low-level signal. Here, "high" and "low" only represent the relative magnitude of the input voltage signals.

[0337] It should also be noted that in practical applications, when all the transistors in the above pixel driving circuit are N-type transistors, the signal timing diagram of this circuit (including DS signal, WS signal, and AZ signal) is different from that of... Figure 25 The timing signals in the circuit are out of phase, and the working principle of this circuit is similar to the process described above.

[0338] When the third transistor T3 in the above pixel driving circuit is an N-type transistor and the other transistors are P-type transistors, the DS signal and WS signal in the timing signals of this circuit diagram are... Figure 25 The timing signals in the data are the same, and the AZ signal is the same as... Figure 25 The timing signals in the circuit are out of phase, and the circuit works in a similar way to the process described above.

[0339] Embodiments of this application provide a display panel including an array substrate as described above.

[0340] In the embodiments of this application, by setting the first power signal line ELVDD to include an electrically connected first part ELVDD-1 and a second part ELVDD-2, the first part ELVDD-1 of the first power signal line is disposed in the same layer as the first control signal line AZ, and the second part ELVDD-2 of the first power signal line is disposed in the same layer as the auxiliary anode ANF. The film layer where the auxiliary anode ANF is located is located in a different layer from the film layer where the first control signal line AZ is located. In this way, the conductivity of the first power signal line ELVDD can be significantly improved, the IR drop problem of the first power signal line ELVDD can be reduced, and the stability of the signal provided by the first power signal line ELVDD to the pixel driving circuit of each sub-pixel can be improved, thereby improving the stability and uniformity of the luminous brightness of each sub-pixel and improving the display effect.

[0341] Embodiments of this application provide a display device, including a display panel as described above.

[0342] In exemplary embodiments, the display device of this application may include, but is not limited to, an OLED display device or a QLED display device, and may be used in virtual reality devices or augmented display devices, etc. The display device may include, but is not limited to: mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators or any product or component with display function.

[0343] In an exemplary embodiment, the array substrate of the display device can integrate the pixel driving circuit array, source driver, gate driver, emission control driver (i.e., the EOA unit in this application), OSC (oscillator), gamma register, and display control module onto the same chip using integrated circuits. The pixel driving circuit, source driver, gate driver, and emission driver are analog circuit modules, while the gamma register, interface, and display control module are mainly digital modules. The array substrate of the substrate integrating digital and analog modules is a typical SOC (System on Chip). Because the analog and digital circuit modules are mixed on the same chip (One Chip technology), the manufacturing process node of the chip is determined by the more demanding digital circuit module.

[0344] For example, the array substrate of the One Chip technology substrate can be fabricated using integrated circuit manufacturing processes of 0.11µm or less than 55nm. In practical applications, due to the high cost of One Chip technology, it is typically used in small-sized display products, such as virtual reality (VR) or augmented reality (AR) near-eye displays.

[0345] In an exemplary embodiment, the array substrate of the substrate can further separate the analog circuit parts, such as the pixel driving circuit array, source driver, gate driver, and emission driver (i.e., the EOA unit of this application), from the OSC, gamma register, interface, and display control module, changing from One-Chip technology to Two-Chip technology. The size of the analog circuit parts is determined by the size of the display area (active area) of the silicon-based microdisplay, but its manufacturing process requirements are low, allowing for the use of low-process technology to reduce costs. Furthermore, because the digital circuit parts are separated, their size is smaller than in the One-Chip mode, further reducing costs. The digital circuit parts mainly include the OSC, gamma register, interface, and display control module. These parts are smaller and can be fabricated separately using high-process technology that matches the circuit manufacturing requirements; this is the so-called Two-Chip mode. The two-chip model separates the display panel from the DDIC (Display Driver Integrated Chip). OLED devices are fabricated on the panel. After processing and testing, the finished product that can be displayed normally is bonded to the DDIC through methods such as COF (Chip on FPC) or COC (Chip on Chip), ultimately forming a controllable silicon-based microdisplay device.

[0346] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An array substrate, wherein, include: A substrate and a plurality of sub-pixels arranged in an array on the substrate, each sub-pixel including an electrically connected pixel driving circuit and a light-emitting device, the pixel driving circuit including: The device includes a driving module and a first control module. The driving module is electrically connected to a first node, a second node, and the anode of the light-emitting device, and is configured to conduct the path between the second node and the anode under the control of the voltage of the first node, and generate a current in the path to make the light-emitting device emit light. The second node is coupled to a first power signal line. The first control module is electrically connected to a first control signal line, a second power signal line, and the anode of the light-emitting device, and is configured to transmit a second power signal transmitted by the second power signal line to the anode under the control of a first control signal transmitted by the first control signal line. The first control module includes a third transistor, the gate of which is electrically connected to the first control signal line via a first trace. The orthographic projection of the first trace on the substrate extends from the side of the gate of the third transistor closer to the first control signal line to the side of the gate of the third transistor away from the first control signal line.

2. The array substrate according to claim 1, wherein, The orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the gate of the third transistor on the substrate, and the first trace is electrically connected to the gate of the third transistor at a position on the side of the gate of the third transistor away from the first control signal line.

3. The array substrate according to claim 2, wherein, The connection point between the first trace and the first control signal line is located in the region where the first trace and the first control signal line overlap, but the first trace does not overlap with the gate of the third transistor.

4. The array substrate according to claim 1, wherein, The array substrate includes a first connection portion; the driving module includes a driving transistor; the first connection portion is electrically connected to the source of the third transistor and the drain of the driving transistor, respectively; The first connecting portion includes a first part and a second part that are connected and are both L-shaped, and the first part and the second part of the first connecting portion have different orientations.

5. The array substrate according to claim 4, wherein, The orthographic projection of the first portion of the first connection on the substrate overlaps with the orthographic projection of the gate of the third transistor on the substrate, and the extension direction of the overlapping portion is the same as the extension direction of the first trace.

6. The array substrate according to claim 5, wherein, The orthographic projection of the second portion of the first connection on the substrate overlaps with the orthographic projection of the drain of the driving transistor on the substrate, and the extension direction of the overlapping portion intersects with the extension direction of the first trace.

7. The array substrate according to claim 6, wherein, The minimum distance between the connection point of the first part and the second part of the first connection portion and the first trace is less than the minimum distance between the connection point and the drain of the driving transistor.

8. The array substrate according to claim 6, wherein, The array substrate includes multiple gate lines and multiple data lines, the gate lines and the data lines intersect, and the sub-pixel is located at a position defined by two adjacent gate lines and two adjacent data lines; In the area occupied by any of the sub-pixels, the first trace is located between the first connection portion and the data line.

9. The array substrate according to claim 8, wherein, Along the extension direction of the first control signal line, the distance between the first trace and the data line is less than the distance between the first trace and the first connection portion.

10. The array substrate according to claim 1, wherein, The pixel driving circuit further includes an input module; the input module is electrically connected to the gate line, the data line and the first node respectively, and is configured to write the data signal transmitted by the data line into the first node under the control of the scan signal transmitted by the gate line; the input module includes a first transistor, the gate of the first transistor is electrically connected to the gate line, the source of the first transistor is electrically connected to the data line, and the drain of the first transistor is electrically connected to the gate of the driving transistor. The array substrate includes a second connection portion, which is electrically connected to the gate of the driving transistor and the drain of the first transistor, respectively; wherein the second connection portion includes a first portion extending along the data line extension direction and a second portion extending along the first control signal line extension direction.

11. The array substrate according to claim 10, wherein, The extension line of the first part of the second connection portion is located on the side of the second part of the second connection portion close to the driving transistor, and the second part of the second connection portion overlaps with the orthographic projection of the source of the first transistor on the substrate.

12. The array substrate according to claim 10, wherein, The array substrate further includes a third connection portion, which is electrically connected to the source of the first transistor and the data line, respectively. The orthographic projection of the third connection portion on the substrate overlaps with the orthographic projection of the source of the first transistor on the substrate, and the orthographic projection of the third connection portion on the substrate overlaps with the orthographic projection of the data line on the substrate.

13. The array substrate according to claim 12, wherein, The area where the third connection portion overlaps with the source of the first transistor is greater than the area where the third connection portion overlaps with the data line.

14. The array substrate according to claim 12, wherein, The region where the third connection portion and the source of the first transistor overlap extends along the gate line direction.

15. The array substrate according to claim 14, wherein, The orthographic projection of the third connection portion and the source of the first transistor on the substrate extends from the side of the source of the first transistor closer to the data line to the side of the source of the first transistor farther from the data line.

16. The array substrate according to claim 15, wherein, The extension direction of the region where the third connection portion and the source of the first transistor overlap intersects the data line; The connection between the third connection portion and the source of the first transistor is located on the side away from the data line in the overlapping area of ​​the two.

17. The array substrate according to claim 4, wherein, The first connecting portions in the sub-pixels of the same row are not completely identical.

18. The array substrate according to claim 17, wherein, In the same row of sub-pixels, the lengths of the first connecting portions of multiple first connecting portions are approximately the same in the direction parallel to the data line, while the lengths of the first connecting portions of two adjacent sub-pixels are different in the direction parallel to the gate line.

19. The array substrate according to claim 10, wherein, The pixel driving circuit further includes a second control module; the second control module is electrically connected to the first power signal line, the second control signal line, and the driving module, and is configured to transmit the first power signal transmitted in the first power signal line to the driving module under the control of the second control signal transmitted in the second control signal line, thereby assisting in generating a current in the path to make the light-emitting device emit light; the second control module includes a second transistor, the gate of the second transistor is electrically connected to the second control signal line, the source of the second transistor is electrically connected to the first power signal line, and the drain of the second transistor is electrically connected to the source of the driving transistor; The array substrate further includes a second trace, the extension direction of which is consistent with the extension direction of the data line. The second trace is electrically connected to the source of the second transistor and the first power signal line, respectively. The second trace and the data line are disposed on the same layer.

20. The array substrate according to claim 19, wherein, In some of the sub-pixels, the extensions of the second trace and the first trace substantially overlap; in some of the sub-pixels, the extensions of the second trace and the first trace are substantially parallel.

21. The array substrate according to claim 1, wherein, The pixel driving circuit further includes an auxiliary anode, which is located between the anode and the substrate, and is electrically connected to the anode. The first power signal line includes a first part and a second part that are electrically connected. The first part of the first power signal line is disposed on the same layer as the first control signal line, and the second part of the first power signal line surrounds the auxiliary anode and the two are disposed on the same layer.

22. A display panel, wherein, Includes the array substrate as described in any one of claims 1 to 21.

23. A display device, wherein, Includes the display panel as described in claim 22.

Images