A chip interconnect device with dual vias

Abstract

The application relates to the field of chip interconnection packaging, and discloses a chip interconnection device with double through holes, wherein the chip interconnection device comprises a dielectric layer, a grounding layer, a first pad, a second pad, a first microstrip line and a second microstrip line; the dielectric layer is provided with a first through hole and a second through hole; the first pad and the second pad are arranged on the upper surface of the dielectric layer; the top end of the first through hole is connected with the first pad; the top end of the second through hole is connected with the second pad; the first through hole and the second through hole vertically penetrate the dielectric layer; the grounding layer is arranged below the dielectric layer; the bottom ends of the first through hole and the second through hole are electrically connected with the grounding layer; the first microstrip line and the second microstrip line are arranged on the upper surface of the dielectric layer; the first microstrip line is electrically connected with the first through hole through the first pad; and the first pad is electrically connected with the second pad through the second microstrip line. The technical scheme provided by the application can improve the signal transmission performance of chip interconnection packaging.

Description

Technical Field

[0001] This application relates to the field of chip interconnect packaging, and more particularly to a chip interconnect device with dual through-holes. Background Technology

[0002] With the rapid development of millimeter-wave technology, the high-frequency communication industry has increasingly higher performance requirements for chip interconnect packaging. Traditional bonded wire interconnects have large parasitic inductance, which easily leads to signal transmission loss and reflection, making it difficult to meet the needs of high-frequency scenarios.

[0003] Currently, the industry commonly uses flip-chip interconnect technology, which connects the electrical connection points of the chip to the printed circuit board or the front side of the package through thermal vias, mitigating the parasitic effects caused by electromagnetic coupling between bond wires to some extent. However, in the millimeter-wave band, due to the impedance mismatch between the load connected to the via and the via, signal reflection and loss still exist, thus affecting the integrity of signal transmission.

[0004] Therefore, improving the signal transmission performance of chip interconnect packaging has become a key research focus in the field of chip packaging. Summary of the Invention

[0005] This application provides a chip interconnect device with dual through-holes, which can improve the signal transmission performance of chip interconnect packages.

[0006] This application provides a chip interconnect device with dual vias. The chip interconnect device includes a dielectric layer, a ground layer, a first pad, a second pad, a first microstrip line, and a second microstrip line. The dielectric layer has the first via and the second via, wherein: the first pad and the second pad are disposed on the upper surface of the dielectric layer; the top end of the first via is connected to the first pad, and the top end of the second via is connected to the second pad; the first via and the second via perpendicularly penetrate the dielectric layer; the ground layer is disposed below the dielectric layer, and the bottom ends of the first via and the second via are electrically connected to the ground layer; the first microstrip line and the second microstrip line are disposed on the upper surface of the dielectric layer; the first microstrip line is electrically connected to the first via through the first pad, and the first pad and the second pad are electrically connected through the second microstrip line.

[0007] In one possible implementation, the dielectric layer includes a first dielectric region, a second dielectric region, and an annular isolation region; wherein: the first through-hole and the second through-hole are located in the first dielectric region, and the annular isolation region is hollow inside; the first dielectric region is surrounded by the annular isolation region, and the annular isolation region is surrounded by the second dielectric region.

[0008] In one possible implementation, the first through hole and the second through hole are annular through holes.

[0009] In one possible implementation, the first through hole and the second through hole are metal through holes.

[0010] In one possible implementation, a first radio frequency (RF) input port and a second RF input port are provided on the lower surface of the first microstrip line, and an RF output port is provided on the boundary line between the annular isolation region, the first dielectric region, and the ground layer. The first RF input port, the second RF input port, and the RF output port are used to transmit RF signals.

[0011] In one possible implementation, the length of the first microstrip line is 550 μm, and the length of the second microstrip line is 30 μm.

[0012] In one possible implementation, the width of both the first microstrip line and the second microstrip line is 35 μm.

[0013] In one possible implementation, the first microstrip line and the second microstrip line are made of metal.

[0014] In one possible implementation, the dielectric layer is made of gallium arsenide.

[0015] The second aspect of this application provides a radio frequency chip packaging device, which is used in a chip interconnect device with dual vias as described in the first aspect.

[0016] The technical solutions provided in one or more embodiments of this application improve the signal transmission performance of chip interconnect packages by controlling the impedance interaction of chip interconnect devices through a dual-via structure and microstrip line design. Specifically, by setting two annular vias in the dielectric layer, the current flow area is increased and the current path is dispersed, resulting in a more uniform electric field distribution and reducing parasitic effects caused by the vias, thereby ensuring impedance stability in the millimeter-wave band. Furthermore, the use of a first and second microstrip line of appropriate length balances parasitic effects with signal transmission requirements, and the setting of an annular isolation region reduces electromagnetic interference, further avoiding impedance mismatch caused by parasitic effects of the vias, thereby ensuring the stability and integrity of signal transmission. Therefore, the technical solutions provided in this application can improve the signal transmission performance of chip interconnect packages. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a chip interconnect device with dual vias provided for one embodiment of this application;

[0019] Figure 2 A schematic diagram of a chip interconnect device with dual vias provided for another embodiment of this application;

[0020] Figure 3 A cross-sectional schematic diagram of a waist-shaped through hole provided for one embodiment of this application;

[0021] Figure 4 A schematic diagram of a chip interconnect device with dual vias provided for another embodiment of this application;

[0022] Figure 5(a) is a diagram of the S11 result obtained after de-embedding simulation according to an embodiment of this application;

[0023] Figure 5(b) is a diagram of the S21 result obtained after de-embedding simulation according to an embodiment of this application.

[0024] Explanation of reference numerals in the attached figures

[0025] 100 - Dielectric layer, 101 - Ground layer, 102 - First pad, 103 - Second pad, 104 - First microstrip line, 105 - Second microstrip line, 106 - First via, 107 - Second via, 20 - First dielectric region, 21 - Ring isolation region, 22 - Second dielectric region, 200 - Dielectric layer, 201 - Ground layer, 202 - First pad, 203 - Second pad, 204 - First microstrip line, 205 - Second microstrip line 206-First via, 207-Second via, 311-First RF input port, 312-Second RF input port, 313-RF output port, 30-First dielectric region, 31-Annular isolation region, 32-Second dielectric region, 300-Dielectric layer, 301-Ground layer, 302-First pad, 303-Second pad, 304-First microstrip line, 305-Second microstrip line, 306-First via, 307-Second via. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] Furthermore, the use of terms such as "first," "second," etc., in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of embodiments in this application, unless otherwise stated, "multiple" means two or more. Additionally, the use of "based on" or "according to" implies openness and inclusiveness, because processes, steps, calculations, or other actions "based on" or "according to" one or more of the stated conditions or values ​​may in practice be based on additional conditions or beyond the stated values.

[0028] Traditionally, chips are interconnected primarily using bonding wires. However, solder ribbons or wires, as bonding wires, have significant parasitic inductance and conductor loss, limiting the transmission performance of RF chips. With the continuous development of chip packaging, current technologies typically employ flip-chip interconnect technology. This involves placing the chip with its active side facing down, and using pads to achieve electrical connection between the chip and the substrate or package carrier for flip-chip interconnection. Thermal vias electrically connect the RF and DC nodes on the front side of the chip to the ground plane, forming the internal interconnection. Signals are transmitted from the active side of the chip to the bottom ground plane. Using vias as the transmission path for chip input and output RF signals mitigates the parasitic effects caused by electromagnetic coupling from bonding wires.

[0029] However, with the widespread use of millimeter waves in RF chips, signal reflection and loss still exist when using thermal vias instead of bonding wires. In the millimeter wave band, any tiny impedance change can cause signal reflection. Since thermal vias, as vertical channels, have altered characteristic impedance due to their geometry, discontinuities between the via's impedance and the impedance of the connected load can cause impedance abrupt changes at the connection point, leading to signal loss and degraded signal transmission performance. Therefore, this application provides one or more embodiments of a chip interconnect device with dual vias, which can solve the above problems and improve the signal transmission performance of chip interconnect packages.

[0030] Please see Figure 1One embodiment of this application provides a chip interconnect device with dual vias. The chip interconnect device includes a dielectric layer 100, a ground layer 101, a first pad 102, a second pad 103, a first microstrip line 104, and a second microstrip line 105. The dielectric layer 100 is provided with a first via 106 and a second via 107, wherein:

[0031] The first pad 102 and the second pad 103 are disposed on the upper surface of the dielectric layer 100. The top end of the first via 106 is connected to the first pad 102, and the top end of the second via 107 is connected to the second pad 103. The first via 106 and the second via 107 penetrate the dielectric layer 100 perpendicularly. The ground layer 101 is disposed below the dielectric layer 100, and the bottom ends of the first via 106 and the second via 107 are electrically connected to the ground layer 101. The first microstrip line 104 and the second microstrip line 105 are disposed on the upper surface of the dielectric layer 100. The first microstrip line 104 is electrically connected to the first via 106 through the first pad 102, and the first pad 102 is electrically connected to the second pad 103 through the second microstrip line 105.

[0032] Specifically, the first via 106 and the second via 107 penetrate the dielectric layer 100 perpendicularly. They are electrically connected on the upper surface of the dielectric layer 100 via the first pad 102, the second pad 103, and the second microstrip line 105, and electrically connected on the lower surface of the dielectric layer 100 via the ground layer 101. Preferably, the central axis of the first via 106 is aligned with the geometric center of the first pad 102, and the central axis of the second via 107 is preferably aligned with the geometric center of the second pad 103, allowing for a deviation in via cross-section not exceeding the size of the pad. The first microstrip line 104 is connected to the first pad 102, and both ends of the second microstrip line 105 are connected to the first pad 102 and the second pad 103, respectively, to achieve electrical connections between the microstrip line and the via, and between vias themselves.

[0033] In this embodiment, the first pad 102 and the second pad 103 are used for electrical connections during chip flip-chip interconnection, and the first via 106 and the second via 107 are used for electrical connections during chip internal interconnection. Chip flip-chip interconnection can be understood as inverting the chip and aligning the pads or bumps on the bottom of the chip with the first pad 102 or the second pad 103 on the dielectric layer to achieve electrical connection between the chip and the dielectric layer. Chip internal interconnection can be understood as electrical connection between different functional units inside the chip. Transistors, resistors, capacitors, and other components inside the chip are connected through multilayer metal wiring, the first via 106, and the second via 107 to form a complete electrical circuit, transmitting signals from the active surface of the chip to the ground plane of the bottom layer. Because the interconnection path formed by the pads and vias is short, the parasitic capacitance and parasitic inductance are small, and impedance changes are less likely to occur, thus ensuring the integrity of signal transmission and providing fast signal transmission, thereby improving signal transmission performance, especially suitable for high-frequency applications.

[0034] In this embodiment, the dual-via structure effectively improves the signal transmission performance of the chip interconnect device. Compared to a single-via structure, the dual-via structure, consisting of a first via 106 and a second via 107, disperses the high-frequency current path, reduces parasitic inductance per unit length of path, and thus reduces energy loss during signal transmission. Furthermore, by reducing parasitic effects in the millimeter-wave band, impedance matching between the load and the vias can be effectively controlled, reducing signal reflection and transmission loss caused by impedance mismatch. This ensures complete signal transmission in the millimeter-wave band or higher frequencies, reduces high-frequency signal transmission loss, and improves the signal transmission performance of the chip interconnect device. Setting the signal transmission path as a via structure with a hollow area reduces the contact area with the dielectric, significantly reducing dielectric loss. In addition, the dual-via structure provides a larger current path, improving the chip's current carrying capacity, preventing overheating and performance degradation, and thus improving the stability of the chip's power and ground networks.

[0035] In this embodiment, using two microstrip lines balances parasitic effects and transmission requirements, thereby ensuring impedance matching of the vias. The first microstrip line 104 and the second microstrip line 105 serve as signal transmission lines for signal transmission and distribution. The first microstrip line 104 serves as the main signal transmission path during chip input / output, specifically for signal reception and transmission. The second microstrip line 105 serves as the connection path between the first pad 102 and the second pad 103, specifically assisting in the electrical connection and signal transmission of the first via 106 and the second via 107. Furthermore, the use of the first microstrip line 104 and the second microstrip line 105 can also help optimize the parasitic effects and impedance matching of the vias. In high-frequency signal transmission in the millimeter-wave band, the design and layout of microstrip lines directly affect signal integrity and impedance matching. Compared to a single microstrip line, using two microstrip lines can disperse the signal transmission path, thereby reducing the impact of parasitic effects and minimizing signal loss and reflection.

[0036] Furthermore, impedance matching can be ensured by adjusting the lengths of the two microstrip lines. Longer microstrip lines may accumulate larger parasitic inductance, while shorter microstrip lines may accumulate larger parasitic capacitance. These parasitic effects lead to signal transmission loss and impedance mismatch, potentially causing signal phase jumps and poor signal integrity, failing to meet transmission requirements. Therefore, by adjusting the lengths of the first microstrip line 104 and the second microstrip line 105, a balance between parasitic effects and transmission requirements can be achieved, ensuring impedance matching of the vias and improving the signal transmission performance of the chip interconnect device.

[0037] In one embodiment, the dielectric layer is divided into a first dielectric region 20, a second dielectric region 22, and an annular isolation region 21, wherein the first through-hole 206 and the second through-hole 207 are located in the first dielectric region 20, and the annular isolation region 21 is hollow inside; the first dielectric region 20 is surrounded by the annular isolation region 21, and the annular isolation region 21 is surrounded by the second dielectric region 22.

[0038] Specifically, please refer to Figure 2The first via 206, the second via 207, the first pad 202, the second pad 203, and the second microstrip line 205 are all located within the first dielectric region 20. A hollow region is created around the first dielectric region 20 as an annular isolation region 21. The dielectric inside the annular isolation region 21 is removed to separate the first dielectric region 20 from the other dielectric regions of the dielectric layer 200. The other dielectric regions surrounding the annular isolation region 21 are designated as the second dielectric region 22. This forms a dielectric layer structure where the first dielectric region 20 is surrounded by the annular isolation region 21, and the annular isolation region 21 is surrounded by the second dielectric region 22. It should be noted that the lower surface of the annular isolation region 21 still retains a ground layer; only the dielectric portion inside the annular isolation region 21 has been removed, effectively making the interior of the annular isolation region 21 hollow.

[0039] In this embodiment, by setting an annular isolation region 21 as an isolation band, the impact of electromagnetic interference on the signal transmission of vias can be reduced. At high frequencies, the diffusion of electromagnetic fields can lead to signal loss and interference. The annular isolation region 21 forms a closed annular structure, effectively isolating the electromagnetic fields inside and outside the first dielectric region 20, preventing electromagnetic signals from the vias from leaking to the outside, and improving the efficiency and quality of signal transmission. Simultaneously, in a dual-via structure, setting the annular isolation region 21 can also reduce parasitic effects and electromagnetic coupling between vias, reduce crosstalk between signals, and ensure impedance matching of the vias, improving the accuracy and reliability of signal transmission. By limiting the diffusion of electromagnetic fields through the annular isolation region 21, the signal transmission performance of the chip interconnect structure is further improved.

[0040] In one embodiment, the first and second through-holes are configured as annular through-holes. This allows for the absorption of thermal expansion differences through deformation, reducing solder joint fatigue and improving the thermal stability and reliability of the chip interconnect device. Preferably, the annular through-hole can be selected as a waist-shaped through-hole. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 The diagram shows a cross-sectional view of the waist-shaped through-hole. The outer rings of both the first and second through-holes consist of two semicircles with a diameter of 15 μm and a square measuring 15 μm x 15 μm. The inner rings of both through-holes consist of two semicircles with a diameter of 9 μm and a rectangle measuring 15 μm x 9 μm. This equates to an outer semicircle diameter of 15 μm, an inner semicircle diameter of 9 μm, a through-hole length of 30 μm, and a through-hole width of 15 μm.

[0041] In one embodiment, the first via, the second via, the first microstrip line, and the second microstrip line are all made of metal, and the first and second vias are metal vias. Exemplarily, the metal can be copper, aluminum, tungsten, copper-aluminum alloy, or other metal materials with good conductivity. The first via, the second via, the first microstrip line, and the second microstrip line serve as the main pathways for signal transmission, and their materials are preferably metal materials that require low resistivity and good processing performance. Furthermore, the dielectric layer is made of gallium arsenide (GaAs). Gallium arsenide can be made into a semi-insulating material with extremely high resistivity, which helps reduce parasitic effects and improve the isolation of the device, making it suitable for fabricating the dielectric layer as a substrate. Exemplarily, the dielectric layer is made of a 2 mil gallium arsenide substrate, the size of the dielectric layer is 1 mm * 1 mm, and the thickness of the ground layer is 3.5 μm.

[0042] In one embodiment, a first radio frequency (RF) input port 311 and a second RF input port 312 are disposed on the lower surface of the first microstrip line 304, and an RF output port 313 is disposed on the interface between the annular isolation region 31 and the first dielectric region 30. The first RF input port 311, the second RF input port 312, and the RF output port 313 are used to transmit RF signals. The first RF input port 311 and the second RF input port 312 are used to input RF signals, and the RF output port 313 is used to output signals. The first RF input port 311, the second RF input port 312, and the RF output port 313 reflect the actual signal transmission status of the chip interconnect device.

[0043] Specifically, please refer to Figure 4 The first RF input port 311 and the second RF input port 312 are preferably located at a position far from the boundary of the dielectric layer 300 and the annular isolation region 31, with the first RF input port 311 and the second RF input port 312 spaced apart. The RF output port 313 is located on the boundary line between the first dielectric region 20, the annular isolation region 21, and the ground layer 301, at the position farthest from the first RF input port 311 and the second RF input port 312. Since the annular isolation region 31 is formed by hollowing out the middle of the dielectric layer 300, it changes the electromagnetic wave transmission mode of the through-hole in the first dielectric region 30. If the first RF input port 311 and the second RF input port 312 are placed close to the annular isolation region 31, it may cause direct coupling between the port and the first dielectric region 30, thereby introducing parasitic capacitance and parasitic inductance, affecting the accuracy of signal transmission. Therefore, to avoid unnecessary parasitic effects, the ports need to be placed far away from the annular isolation region 31.

[0044] In this embodiment, different RF input ports are provided on the first microstrip line 304 to acquire simulation data in order to evaluate signal transmission characteristics. To clearly understand the impact of parasitic responses of the chip interconnect device on signals at high frequencies, and to consider parasitic parameters in the matching circuit design to ensure appropriate impedance matching, a first RF input port 311, a second RF input port 312, and an RF output port 313 are provided to evaluate signal transmission characteristics. The different RF input ports on the first microstrip line 304 reflect the actual signal transmission situation of the chip interconnect device. For example, the RF signal is input from the first RF input port 311 and the second RF input port 312, transmitted through the first microstrip line 304 to the bottom of the first via 306 and the second via 307, and output as an electromagnetic wave from the bottom RF output port 313, thereby being transmitted to subsequent circuit elements.

[0045] In one embodiment, radio frequency (RF) signals are input from a first RF input port and a second RF input port, respectively, and the transmitted RF signal is acquired from the RF output port. The signal transmission simulations from both RF input ports are used as two simulation results. These two simulation results undergo de-embedding processing to remove the influence of the first microstrip line between the first and second RF input ports. This further separates the electrical characteristics of the via from the overall simulation results, thereby obtaining an accurate via impedance. In the millimeter-wave band, the parameter characteristics of the microstrip line significantly affect signal transmission; therefore, de-embedding processing can eliminate these effects, making the simulation results more accurately reflect the via impedance characteristics. Furthermore, the via impedance data obtained through de-embedding processing can be precisely compensated in the matching circuit design, thereby further optimizing the overall chip circuit performance.

[0046] It should be noted that de-embedding is a commonly used technique in signal processing and circuit design. It is used to eliminate the influence of peripheral components such as the test system or test fixture from measured data, thereby obtaining the true performance parameters of the circuit or system. Specifically, by establishing a mathematical model of the peripheral adapter circuit and then using calculation methods to eliminate its influence on the test results, de-embedding is performed on the simulation results of the first and second RF input ports. This eliminates the influence of the portion of the first microstrip line between the first and second RF input ports on the measurement results, thus obtaining a more realistic via impedance.

[0047] Please refer to Figures 5(a) and 5(b). Figure 5(a) shows the S11 result obtained after de-embedding simulation, and Figure 5(b) shows the S21 result obtained after de-embedding simulation. Specifically, S-parameters can be understood as scattering parameters describing the electrical performance of the RF network, including S11 and S21. S11 represents the reflection coefficient of the input port, used to describe how much of the input signal is reflected. If there is impedance mismatch, the S11 value will increase. S21 represents the transmission coefficient from the input port to the output port, used to describe the loss in the input signal. Figure 5(a) reflects the change of the reflection coefficient with frequency, thus allowing observation of the reflection loss at different frequencies to evaluate the quality of impedance matching. Figure 5(b) reflects the change of the transmission coefficient with frequency, thus allowing observation of the signal transmission loss at different frequencies to evaluate the transmission performance of the chip interconnect device. A lower S11 value indicates good impedance matching, and a higher S21 indicates good transmission performance. By analyzing the attached diagrams for S11 and S21, we can understand the performance of the chip interconnect device at different frequencies. This allows for further optimization of the chip interconnect device design to improve signal integrity and transmission efficiency. For example, if the signal loss is greater than 10dB, it is determined to be an impedance mismatch. In this case, the length of the microstrip line can be adjusted, or equivalent capacitance and equivalent inductance compensation can be performed at the chip level.

[0048] In one embodiment, both the first and second microstrip lines are set to a width of 35µm. Setting the microstrip line width to 35µm achieves a 50-ohm impedance, which facilitates a single transmission mode within a specific frequency range and ensures good matching with transmission lines such as coaxial cables, reducing signal reflection and loss, thereby guaranteeing signal integrity and the transmission performance of the chip interconnect device. It should be noted that 50 ohms is a standard impedance widely used in radio frequency systems.

[0049] In one embodiment, the length of the first microstrip line is set to 550 μm, and the length of the second microstrip line is set to 30 μm. In the millimeter-wave band from 71 GHz to 86 GHz, setting the length of the first microstrip line to 550 μm and the length of the second microstrip line to 30 μm can make the S11 signal loss greater than or equal to 10 dB, thereby achieving a match between parasitic effects and transmission requirements and improving the signal transmission performance of the chip interconnect area.

[0050] Specifically, when the microstrip line is shorter than 550µm or 30µm, additional parasitic capacitance is generated in the transition region between the microstrip line and the via in the 71-86GHz band. This results in a more pronounced impedance change, causing the impedance of the transition region to deviate from 50 ohms, thus causing signal loss. Particularly in the 82-86GHz band, it also increases the coupling capacitance between the via and the island, exacerbating the parasitic effect of the via. Conversely, when the microstrip line is longer than 550µm or 30µm, additional parasitic inductance is generated in the transition region between the microstrip line and the via in the 71-86GHz band. This leads to a more pronounced impedance change and increases the electromagnetic coupling between the chip interconnect and the surrounding metal structure, introducing additional cross-parasitic capacitance and further exacerbating impedance mismatch. Furthermore, when the microstrip line is shorter than 550µm or 30µm, the signal is prone to phase abrupt changes in the transition region between the microstrip line and the via, affecting the integrity of the link signal. When the microstrip line is shorter than 550µm or 30µm, the signal attenuation increases and the output power decreases, which cannot meet the signal strength requirements. It may also cause signal reflection and superposition to form standing waves, affecting the stability of signal transmission.

[0051] Exemplarily, this application provides a specific embodiment of the above-described chip interconnect device with dual vias. In the millimeter-wave band from 71 GHz to 86 GHz, the dimensions of each part of the chip interconnect device in this embodiment can be set as follows: the first microstrip line has a length of 550 μm and a width of 35 μm; the second microstrip line has a length of 550 μm and a width of 30 μm; both the first and second microstrip lines are microstrip lines with an impedance of 50 ohms; the first and second pads are both 30 μm * 50 μm in size; the first and second vias are oblong vias; the outer rings of both the first and second vias are composed of two semicircles with a diameter of 15 μm and a square of 15 μm * 15 μm; the inner rings of both the first and second vias are composed of two semicircles with a diameter of 9 μm and a rectangle of 15 μm * 9 μm; and the hollow first and second vias are modeled using Boolean operations. The dielectric layer and ground layer are 1mm*1mm in size. The dielectric layer substrate is a 2mil gallium arsenide substrate. The dielectric layer is 50um thick and the ground layer is 3.5um thick.

[0052] Based on the above ideas, the technical solution provided in one or more embodiments of this application improves the signal transmission performance of chip interconnect packages by employing a dual-via structure and microstrip line design to control the impedance interaction of the chip interconnect device. Specifically, by setting two annular vias in the dielectric layer, the current flow area is increased and the current path is dispersed, resulting in a more uniform electric field distribution and reducing the parasitic effects caused by the vias, thereby ensuring impedance stability in the millimeter-wave band. Furthermore, by using a first and second microstrip line of appropriate length to balance parasitic effects and signal transmission requirements, and by setting an annular isolation region to reduce electromagnetic interference, impedance mismatch caused by parasitic effects of the vias is further avoided, thereby ensuring the stability and integrity of signal transmission. Therefore, the technical solution provided in this application can improve the signal transmission performance of chip interconnect packages.

[0053] The second aspect of this application provides a radio frequency chip packaging device that utilizes a chip interconnect device with dual vias as described in the first aspect above.

[0054] In one embodiment, the radio frequency chip packaging device includes a radio frequency chip, a chip interconnect device, and a printed circuit board.

[0055] In another embodiment, the radio frequency chip packaging device includes a radio frequency chip, a chip interconnect device, and a packaging carrier.

[0056] In one embodiment, the radio frequency chip packaging device includes a radio frequency chip, a chip interconnect device, and a motherboard.

[0057] The chip described above can be implemented by a product with a certain function. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0058] It should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0059] It should be noted that, in this application, unless otherwise expressly specified and limited, the first feature in the second feature “” or “” can mean that the first feature and the second feature are in direct contact, or that the first feature and the second feature are in indirect contact through an intermediate medium. Furthermore, “above,” “over,” and “on top” can mean that the first feature is directly above or diagonally below the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. Similarly, “below,” “under,” and “beneath” can mean that the first feature is directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0060] It should be noted that an element is referred to as being "fixed to" or "set on" another element, which may be directly on the other element or may also include an intervening element. An element is considered to be "connected" to another element, which may be directly connected to the other element or may also include an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0061] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments; relevant parts can be referred to in the descriptions of other embodiments. The multiple embodiments provided in this application are used to illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them.

[0062] It should be noted that the illustrations provided in the above embodiments are only schematic representations of the basic concept of this application. The illustrations only show the elements related to this application and are not drawn according to the actual number, shape and size of the elements in the actual implementation. In the actual implementation, the form, quantity and proportion of each element can be arbitrarily changed, and the layout of the elements may also be more complex.

[0063] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0064] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A chip interconnect device with dual through-holes, characterized in that, The chip interconnect device includes a dielectric layer, a ground layer, a first pad, a second pad, a first microstrip line, and a second microstrip line. The dielectric layer has a first via and a second via, wherein: The first pad and the second pad are disposed on the upper surface of the dielectric layer, the top end of the first through hole is connected to the first pad, and the top end of the second through hole is connected to the second pad; The first through hole and the second through hole penetrate the dielectric layer perpendicularly, and the ground layer is disposed below the dielectric layer. The bottom ends of the first through hole and the second through hole are electrically connected to the ground layer. The first microstrip line and the second microstrip line are disposed on the upper surface of the dielectric layer. The first microstrip line is electrically connected to the first via through the first pad, and the first pad is electrically connected to the second pad through the second microstrip line. The dielectric layer includes a first dielectric region, a second dielectric region, and an annular isolation region. The first through-hole and the second through-hole are located in the first dielectric region. The annular isolation region is hollow inside. The first dielectric region is surrounded by the annular isolation region, and the annular isolation region is surrounded by the second dielectric region.

2. The chip interconnect device according to claim 1, characterized in that, The first through hole and the second through hole are annular through holes.

3. The chip interconnect device according to claim 1, characterized in that, The first through hole and the second through hole are metal through holes.

4. The chip interconnect device according to claim 1, characterized in that, The lower surface of the first microstrip line is provided with a first radio frequency input port and a second radio frequency input port, and a radio frequency output port is provided on the boundary line between the annular isolation region, the first dielectric region and the ground layer. The first radio frequency input port, the second radio frequency input port and the radio frequency output port are used to transmit radio frequency signals.

5. The chip interconnect device according to claim 1, characterized in that, The length of the first microstrip line is 550 μm, and the length of the second microstrip line is 30 μm.

6. The chip interconnect device according to claim 1, characterized in that, The width of both the first microstrip line and the second microstrip line is 35µm.

7. The chip interconnect device according to any one of claims 1, 5, or 6, characterized in that, The first microstrip line and the second microstrip line are made of metal.

8. The chip interconnect device according to claim 1, characterized in that, The dielectric layer is made of gallium arsenide.

9. A radio frequency chip packaging device, characterized in that, The application is a chip interconnect device with dual vias as described in any one of claims 1 to 8.

Images