A turn-off device for a pre-driver chip, a pre-driver chip and a motor driving system

Abstract

The application discloses a shutdown device for a pre-driver chip, a pre-driver chip and a motor driving system, and relates to the technical field of power device driving. The device comprises a logic circuit and a detection circuit. The logic circuit is adapted to be connected with a power control module, an enable control module, a driving end of a driver and an enable end of the driver respectively. The detection circuit is connected with the logic circuit and adapted to be connected with the enable control module. The logic circuit is used for enabling the driver to normally drive a connected transistor and closing the detection circuit when the enable control module outputs a first level, and enabling the driver to pull down a gate voltage of the transistor and enabling the detection circuit to work when the enable control module outputs a second level. The detection circuit is used for outputting the second level when the transistor is shut down, so as to trigger the logic circuit to close the driver and the detection circuit. Thus, the safe shutdown of the pre-driver chip can be realized without occupying software resources.

Description

Technical Field

[0001] This invention relates to the field of power device drive technology, and in particular to a shutdown device for a pre-drive chip, a pre-drive chip, and a motor drive system. Background Technology

[0002] In the pre-driver chip, such as Figure 1 As shown, the driver receives PWM (Pulse Width Modulation) signals from drive control modules, such as the PWM signal generated by the PWM module, and the enable signal generated by the enable control module. These signals are used to generate drive signals to drive external transistors, such as MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors), controlling the operating state of the load (e.g., a motor). When the diagnostic module detects an abnormal error state in the system, or when the system mode control module receives a low-power mode request or power-down request, the enable control module shuts down the driver to achieve the system-defined safe state or low-power mode. When the driver is shut down, the driver's output state is determined by the PWM signal previously received at the driver's drive terminal. If one of the driver's output terminals is high at this time, such as... Figure 2 As shown, due to the large gate capacitance of the off-chip transistor, the gate voltage drops slowly, and the high level of the transistor gate will be maintained for a long time (i.e., it remains in the conducting state for a long time), resulting in a long turn-off response time. During this period, due to incomplete turn-off and commutation cessation, the load will operate in a phase-loss manner, leading to load damage and endangering system safety.

[0003] To avoid the adverse effects of the above problems, the following two methods are commonly used in related technologies:

[0004] 1) Integrate pull-down resistors in the power module, such as Figure 1 As shown, this method allows the driver output to be pulled low to the off state by a pull-down resistor when the power module is off. However, in order not to affect normal function, the pull-down resistor has a relatively large value, which makes the gate voltage of the transistor drop very slowly. The transistor will remain in the conducting state for a long time, and the system safety hazard has not been completely eliminated.

[0005] 2) A software approach is used to pull the output of the power control module low before the system needs to enter low-power mode, ensuring that all transistors are de-conducting before shutting down the driver. However, this method is only effective for software-controllable low-power modes and consumes software resources. It is ineffective in cases where diagnostic errors, which are not software-controllable, cause the system to automatically shut down the driver. Summary of the Invention

[0006] The purpose of this invention is to provide a shutdown device for a pre-drive chip, a pre-drive chip, and a motor drive system, so as to achieve safe shutdown of the pre-drive chip without consuming software resources.

[0007] In a first aspect, embodiments of the present invention provide a shutdown device for a pre-driven chip, the pre-driven chip including a power control module, an enable control module, and a driver, the device including: a logic circuit and a detection circuit; the logic circuit is adapted to be connected to the power control module, the enable control module, the drive terminal of the driver, and the enable terminal of the driver respectively, the detection circuit being connected to the logic circuit and adapted to be connected to the enable control module; wherein, the logic circuit is used to enable the driver to normally drive the connected transistor and shut down the detection circuit when the enable control module outputs a first level, and to enable the driver to pull down the gate voltage of the transistor and enable the detection circuit to operate when the enable control module outputs a second level; the detection circuit is used to output a second level when the transistor is turned off, to trigger the logic circuit to shut down the driver and the detection circuit.

[0008] In some embodiments, the logic circuit includes: a first logic sub-circuit, connected to the detection circuit and adapted to be respectively connected to the power control module, the enable control module, the drive terminal of the driver, and the enable terminal of the driver, for enabling the driver to normally drive the connected transistor when the enable control module outputs a first level, enabling the driver to pull down the gate voltage of the transistor when the enable control module outputs a second level, and turning off the driver when the detection circuit outputs a second level; and a second logic sub-circuit, connected to the detection circuit and adapted to be connected to the enable control module, for turning off the detection circuit when the enable control module outputs a first level, enabling the detection circuit to operate when the enable control module outputs a second level, and turning off the detection circuit when the detection circuit outputs a second level.

[0009] In some embodiments, the first logic sub-circuit includes a first AND gate and an OR gate. The first input of the first AND gate is adapted to be connected to the power control module. The second input of the first AND gate is connected to the first input of the OR gate and is adapted to be connected to the enable control module. The output of the first AND gate is connected to the driving terminal of the driver. The second input of the OR gate is connected to the output of the detection circuit and the second input of the second logic sub-circuit, respectively.

[0010] In some embodiments, the second logic sub-circuit includes a first NOT gate and a second AND gate. The input of the first NOT gate is adapted to be connected to the enable control module. The output of the first NOT gate is connected to the first input of the second AND gate. The second input of the second AND gate is connected to the second input of the OR gate and the output of the detection circuit, respectively.

[0011] In some embodiments, the detection circuit includes a detection enable register and a voltage detection unit. The reset terminal of the detection enable register is adapted to be connected to the enable control module. The clock terminal of the detection enable register is connected to the output terminal of the voltage detection unit. The output terminal of the detection enable register is connected to the second input terminal of the OR gate and the second input terminal of the second AND gate, respectively. The enable terminal of the voltage detection unit is connected to the output terminal of the second AND gate. The detection terminal of the voltage detection unit is adapted to be connected to the gate and source of the transistor. The voltage detection unit is configured to detect the gate-source voltage of the transistor when the second AND gate outputs a first level, and output a first level when the gate-source voltage is greater than or equal to a threshold voltage, or when the second AND gate outputs a second level, so that the detection enable register outputs a first level; and output a second level when the gate-source voltage is less than the threshold voltage, so that the detection enable register outputs a second level.

[0012] In some embodiments, the detection circuit includes a second NOT gate, a counter, an overflow judgment unit, and an overflow status register. The output terminal of the second NOT gate is connected to the second input terminal of the OR gate and the second input terminal of the second AND gate, respectively. The enable terminal of the counter is connected to the output terminal of the second AND gate, and the reset terminal of the counter is connected to the input terminal of the second NOT gate and the output terminal of the overflow status register, respectively. The first input terminal of the overflow judgment unit is connected to the output terminal of the counter, and the input terminal of the overflow status register is connected to the output terminal of the overflow judgment unit. The reset terminal of the overflow status register is adapted to be connected to the enable control module. The counter is used to count the gate pull-down time of the transistor when the second AND gate outputs a first level. The overflow judgment unit is used to enable the overflow status register to output a first level when the counter's count value reaches a target value, thereby clearing the counter's count value and causing the second NOT gate to output a second level. The target value is the time required for the transistor's gate voltage to be pulled down to the turn-off voltage.

[0013] In some embodiments, the detection circuit further includes a clock source for providing a timing clock to the counter, wherein the target value is determined based on the parameters of the transistor, the drive strength of the driver, and the parameters of the clock source.

[0014] In some embodiments, the detection circuit further includes a shutdown pull-down time control word register and a memory, wherein the input of the shutdown pull-down time control word register is connected to the memory, and the output of the shutdown pull-down time control word register is connected to the second input of the overflow judgment unit; wherein the memory is used to store the target value, and the shutdown pull-down time control word register is used to load the target value when the pre-driver chip starts.

[0015] In a second aspect, embodiments of the present invention provide a pre-driving chip, comprising: a power control module, an enable control module, and a driver, as well as a shutdown device for the pre-driving chip as described in the first aspect embodiment.

[0016] Thirdly, embodiments of the present invention provide a motor drive system, comprising: a motor, a power module, and a pre-drive chip as described in the second aspect embodiment, wherein the power module comprises transistors.

[0017] The present invention provides a shutdown device for a pre-driven chip, a pre-driven chip, and a motor drive system. When the enable control module outputs a first level, the logic circuit enables the driver to normally drive the connected transistor and shuts down the detection circuit. When the enable control module outputs a second level, the enable driver pulls down the gate voltage of the transistor and enables the detection circuit to operate. The detection circuit outputs a second level when the transistor is turned off, triggering the logic circuit to shut down the driver and the detection circuit. Therefore, the safe shutdown of the pre-driven chip can be achieved without consuming software resources. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a pre-driver chip in related technologies;

[0019] Figure 2 This is a timing diagram of the pre-driver chip shutdown in related technologies;

[0020] Figure 3 This is a schematic diagram of the structure of a shutdown device for a pre-driven chip according to an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of a shutdown device for a pre-driven chip according to an embodiment of the present invention;

[0022] Figure 5 This is a topology diagram of a shutdown device for a pre-driven chip according to an embodiment of the present invention;

[0023] Figure 6 yes Figure 5 The shutdown timing diagram of the embodiment shown;

[0024] Figure 7This is a topology diagram of a shutdown device for a pre-driven chip according to another embodiment of the present invention;

[0025] Figure 8 yes Figure 7 The shutdown timing diagram of the embodiment shown;

[0026] Figure 9 This is a schematic diagram of the structure of the pre-driver chip according to an embodiment of the present invention;

[0027] Figure 10 This is a schematic diagram of the electrode driving system according to an embodiment of the present invention.

[0028] Figure label:

[0029] The pre-drive chip 1000, the shutdown device 100 for the pre-drive chip, the power control module 200, the enable control module 300, and the driver 400 are included.

[0030] Logic circuit 10, first logic sub-circuit 11, second logic sub-circuit 12, first AND gate 111, OR gate 112, first NOT gate 121, second AND gate 122, detection circuit 20, detection enable register 21, voltage detection unit 22, second NOT gate 23, counter 24, overflow judgment unit 25, overflow status register 26, clock source 27, shutdown pull-down time control word register 28, memory 29, transistor T. Detailed Implementation

[0031] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0032] The following is a reference appendix. Figure 3 - Appendix Figure 10 This invention describes a shutdown device for a pre-driven chip, a pre-driven chip, and a motor drive system according to embodiments of the present invention.

[0033] Figure 3 This is a schematic diagram of the structure of a shutdown device for a pre-driven chip according to an embodiment of the present invention.

[0034] In an embodiment of the present invention, the pre-driver chip 1000 includes a power control module 200, an enable control module 300, and a driver 400. For example... Figure 3As shown, the shutdown device 100 for the pre-driven chip includes: a logic circuit 10 and a detection circuit 20; the logic circuit 10 is adapted to be connected to the power control module 200, the enable control module 300, the drive terminal of the driver 400, and the enable terminal of the driver 400, respectively; the detection circuit 20 is connected to the logic circuit 10 and is adapted to be connected to the enable control module 300.

[0035] In this embodiment, the logic circuit 10 is used to enable the driver 400 to normally drive the connected transistor T (such as a MOSFET, IGBT, etc.) and turn off the detection circuit 20 when the enable control module 300 outputs a first level, and to enable the driver 400 to pull down the gate voltage of the transistor T and enable the detection circuit 20 to work when the enable control module 300 outputs a second level; the detection circuit 20 is used to output a second level when the transistor T is turned off, so as to trigger the logic circuit 10 to turn off the driver 400 and the detection circuit 20.

[0036] Specifically, see Figure 3 When the enable control module 300 outputs a first level, such as a high level 1, the logic circuit 10 synchronously outputs the first level from the enable control module 300 to the enable terminal of the driver 400, and synchronously outputs the output of the power control module 200 to the drive terminal of the driver 400, so that the driver 400 can normally drive the connected transistor T; at the same time, the logic circuit 10 outputs a second level, such as a low level 0, to the detection circuit 20, so that the detection circuit 20 is turned off (i.e., not working). When the enable control module 300 outputs a second level, such as a low level 0, the logic circuit 10 first maintains the first level output to the enable terminal of the driver 400 and outputs the second level to the drive terminal of the driver 400, so that the driver 400 pulls down the gate voltage of the connected transistor T, and outputs the first level to the detection circuit 20 to enable the detection circuit 20 to work; when the gate voltage of the transistor T reaches the turn-off voltage (at which time the transistor T is turned off), the detection circuit 20 outputs the second level to trigger the logic circuit 10 to output the second level to the enable terminal of the driver 400, so that the driver 400 is turned off, thus turning off the pre-driven chip 1000. At the same time, the logic circuit 10 also outputs the second level to the detection circuit 20 to turn off the detection circuit 20 (i.e., it does not work).

[0037] The output of the enable control module 300 can be based on Figure 1The outputs of the diagnostic module and the system mode control module are determined. For example, when the diagnostic module detects an abnormal error state in the system or the system mode control module receives a low-power mode request or a power-down request, the output of the enable control module 300 changes from the first level to the second level. The function of the logic circuit 10 can be implemented by digital logic devices, and the type and connection method of the digital logic devices can be selected and designed as needed. The detection circuit 20 detects whether the transistor T is turned off or not by detecting the gate-source voltage of the transistor T and recording the duration after the gate voltage of the transistor T is pulled low.

[0038] The shutdown device 100 for the pre-driven chip can safely shut down the pre-driven chip 1000 by being triggered by hardware signals from the logic circuit 10 and the detection circuit 20, without requiring software intervention and consuming no software resources. Furthermore, the detection circuit 20 only operates within the time window during which the driver performs the safe shutdown, and automatically shuts down after completion, preventing power waste.

[0039] It should be noted that the shutdown device 100 for the pre-drive chip corresponds one-to-one with the transistor T. When there are multiple transistors T (such as 6 in a three-phase bridge inverter, 4 in an H-bridge, and 2 in a half-bridge), multiple shutdown devices 100 for the pre-drive chip need to be set up simultaneously. Each shutdown device 100 for the pre-drive chip works according to the shutdown status of the corresponding transistor T.

[0040] In some embodiments of the present invention, such as Figure 4 As shown, the logic circuit 10 includes: a first logic sub-circuit 11 and a second logic sub-circuit 12.

[0041] See Figure 4 The first logic sub-circuit 11 is connected to the detection circuit 20 and is adapted to be connected to the power control module 200, the enable control module 300, the driver terminal of the driver 400, and the enable terminal of the driver 400, respectively. It is used to enable the driver 400 to drive the connected transistor T normally when the enable control module 300 outputs a first level, and to enable the driver 400 to pull down the gate voltage of the transistor T when the enable control module 300 outputs a second level, and to turn off the driver 400 when the detection circuit 20 outputs a second level. The second logic sub-circuit 12 is connected to the detection circuit 20 and is adapted to be connected to the enable control module 300. It is used to turn off the detection circuit 20 when the enable control module 300 outputs a first level, and to enable the detection circuit 20 to work when the enable control module 300 outputs a second level, and to turn off the detection circuit 20 when the detection circuit 20 outputs a second level.

[0042] In this embodiment, the functions of the first logic sub-circuit 11 and the second logic sub-circuit 12 can both be implemented by digital logic devices, and the type and connection method of the digital logic devices can be selected and designed as needed.

[0043] In some examples, such as Figure 5 , Figure 7 As shown, the first logic sub-circuit 11 includes a first AND gate 111 and an OR gate 112. The first input terminal of the first AND gate 111 is adapted to be connected to the power control module 200. The second input terminal of the first AND gate 111 is connected to the first input terminal of the OR gate 112 and is adapted to be connected to the enable control 300 module. The output terminal of the first AND gate 111 is connected to the driving terminal of the driver 400. The second input terminal of the OR gate 112 is connected to the output terminal of the detection circuit 20 and the second input terminal of the second logic sub-circuit 12, respectively.

[0044] In some examples, such as Figure 5 , Figure 7 As shown, the second logic sub-circuit 12 includes a first NOT gate 121 and a second AND gate 122. The input terminal of the first NOT gate 121 is adapted to be connected to the enable control module 300. The output terminal of the first NOT gate 121 is connected to the first input terminal of the second AND gate 122. The second input terminal of the second AND gate 122 is connected to the second input terminal of the OR gate 2 and the output terminal of the detection circuit 20, respectively.

[0045] As one implementation method, see Figure 5 The detection circuit 20 includes a detection enable register 21 and a voltage detection unit 22. The reset terminal RST of the detection enable register 21 is adapted to be connected to the enable control module 300. The clock terminal CP of the detection enable register 21 is connected to the output terminal of the voltage detection unit 22. The output terminal Q of the detection enable register 21 is connected to the second input terminal of the OR gate 112 and the second input terminal of the second AND gate 122, respectively. The enable terminal of the voltage detection unit 22 is connected to the output terminal of the second AND gate 122. The detection terminal of the voltage detection unit 22 is adapted to be connected to the gate and source of the transistor T.

[0046] In this embodiment, the voltage detection unit 22 is used to detect the gate-source voltage of transistor T when the second AND gate 122 outputs a first level, and outputs a first level when the gate-source voltage is greater than or equal to a threshold voltage, or when the second AND gate 122 outputs a second level, so that the detection enable register 21 outputs a first level; and outputs a second level when the gate-source voltage is less than a threshold voltage, so that the detection enable register 21 outputs a second level.

[0047] Taking transistor T as an example, where T is a MOSFET. See [link / reference]. Figure 5The voltage detection unit 22 can be arranged independently, while the first logic sub-circuit 11, the second logic sub-circuit 12, and the detection enable register 21 can be integrated into a shutdown timing control module. For example... Figure 6 As shown, the voltage detection unit 22 outputs 1 to indicate that the MOSFET VGS (i.e., the gate-source voltage of transistor T) is greater than or equal to Vth (i.e., the threshold voltage), and the MOSFET is in the on state; the output 0 indicates that the MOSFET VGS is less than Vth, and the MOSFET is in the off state. When the voltage detection unit 22 is not enabled, its default output value is 1. The RST terminal of the detection enable register 21 is connected to the output of the enable control module 300, and resetting it makes the Q terminal output 1; the D terminal of the detection enable register 21 is grounded, and the CP terminal is connected to the output of the voltage detection unit 22. When the enable control module 300 outputs 1 to enable the driver 400, the shutdown timing control module remains functionally transparent, and the voltage detection unit 22 remains in the disabled state. When the enable control module 300 outputs 0 to indicate that the driver 400 is about to be turned off, the shutdown timing control module will temporarily maintain the enabled state of the driver 400 and send 0 to the driver terminal of the driver 400, causing the driver 400 to quickly pull down the gate voltage of the MOSFET. Simultaneously, the enable voltage detection unit 22 will operate. Before the MOSFET is turned off, the voltage detection unit 22 will output a detection result of 1. This will cause the shutdown timing control module to maintain the aforementioned state of pulling down the MOSFET gate voltage until the voltage detection unit outputs a detection result of 0, indicating that the MOSFET has been successfully turned off. At this point, the MOSFET VGS detection enable register CP terminal is driven by a falling edge, and the Q terminal outputs 0, turning off the driver 400 and the voltage detection unit 22. Throughout the process, the voltage detection unit 22 only operates within the safe shutdown time window of the driver and automatically shuts down after completion, without wasting power. The next time the enable control module 300 outputs 1 to enable the driver 400, the detection enable register 21 is reset to its default value of 1.

[0048] thus, Figure 5 The implementation shown can safely shut down the pre-driver chip 1000 without consuming software resources and without wasting power.

[0049] In another implementation, the detection circuit 20 includes a second NOT gate 23, a counter 24, an overflow judgment unit 25, and an overflow status register 26. The output of the second NOT gate 23 is connected to the second input of the OR gate 112 and the second input of the second AND gate 122, respectively. The enable terminal of the counter 24 is connected to the output of the second AND gate 122, and the clear terminal of the counter 24 is connected to the input of the second NOT gate 122 and the output of the overflow status register 25, respectively. The first input of the overflow judgment unit 25 is connected to the output of the counter 24, and the input of the overflow status register 26 is connected to the output of the overflow judgment unit 25. The reset terminal of the overflow status register 26 is adapted to be connected to the enable control module 300.

[0050] In this embodiment, the counter 24 is used to count the gate pull-down time of transistor T when the second AND gate 122 outputs the first level. The overflow judgment unit 25 is used to enable the overflow status register 26 to output the first level when the count value of the counter 24 reaches the target value, so as to clear the count value of the counter 24 and enable the second NOT gate 122 to output the second level. The target value is the time required for the gate voltage of transistor T to be pulled down to the turn-off voltage.

[0051] For example, such as Figure 7 As shown, the detection circuit 20 also includes a clock source 27, which provides a timing clock to the counter 24. The target value is determined based on the parameters of the transistor T, the driving strength of the driver 400, and the parameters of the clock source 27.

[0052] For example, see Figure 7 The detection circuit 20 also includes a shutdown pull-down time control word register 28 and a memory 29. The input terminal of the shutdown pull-down time control word register 28 is connected to the memory 29, and the output terminal of the shutdown pull-down time control word register 28 is connected to the second input terminal of the overflow judgment unit 26.

[0053] Among them, memory 29 is used to store the target value, and the shutdown pull-down time control word register 28 is used to load the target value when the pre-driver chip 1000 starts.

[0054] Taking transistor T as an example, where T is a MOSFET. See [link / reference]. Figure 7The clock source 27 and memory 29 can be arranged separately, while the first logic sub-circuit 11, the second logic sub-circuit 12, the second NOT gate 23, the counter 24, the overflow judgment unit 25, the overflow status register 26, and the shutdown pull-down time control word register 28 can be integrated into a shutdown timing control module. This shutdown timing control module uses the counter 24 to control the MOSFET gate pull-down time. The user can determine the time required for the MOSFET gate voltage to pull down to MOSFET turn-off based on the external MOSFET parameters and the driver 400's drive strength. Combined with the on-chip clock source 27 parameters, the target value of the counter 24 is determined and burned into the memory 29 (such as on-chip non-volatile memory). After the pre-driver chip 1000 starts, this target value will be loaded into the shutdown pull-down time control word register 28 inside the shutdown timing control module. Figure 8 As shown, when the enable control module 300 outputs 1 to enable the driver 400, the shutdown timing control module remains functionally transparent, and the overflow status register 26 is reset to 0. When the enable control module 300 outputs 0 to intend to shut down the driver 400, the shutdown timing control module will temporarily maintain the driver's enabled state and send a low level to the driver terminal of the driver 400, causing the driver 400 to quickly pull down the gate voltage of the MOSFET; at the same time, the enable counter 24 starts counting, and the overflow judgment unit 25 judges in real time whether the counter 24 has reached the target value recorded in the shutdown pull-down time control word register 28 and overflows. When no overflow is detected, the overflow status register 26 outputs 0, which will cause the shutdown timing control module to maintain the above-mentioned state of pulling down the MOSFET gate voltage until an overflow is detected, at which point the overflow status register 26 outputs 1 and maintains that value, shutting down the driver 400 and the counter. Therefore, the counter 24 only works within the time window of the driver's safe shutdown and automatically shuts down after work, without causing power waste. When the next time the control module 300 outputs 1 to enable the driver 400, the overflow status register 26 is reset back to its default value of 0.

[0055] thus, Figure 7 The implementation shown can safely shut down the pre-driver chip 1000 without consuming software resources and without wasting power.

[0056] Based on the shutdown device for the pre-driving chip in the above embodiments, the present invention proposes a pre-driving chip.

[0057] Figure 9 This is a structural block diagram of the pre-driver chip according to an embodiment of the present invention.

[0058] like Figure 9As shown, the pre-drive chip 1000 includes: a power control module 200, an enable control module 300, and a driver 400, as well as a shutdown device 100 for the pre-drive chip in the above embodiment.

[0059] Among them, the pre-drive chip 1000 can be a motor pre-drive chip.

[0060] Based on the pre-driving chip in the above embodiments, the present invention proposes a motor drive system.

[0061] Figure 10 This is a structural block diagram of the motor drive system according to an embodiment of the present invention.

[0062] like Figure 10 As shown, the motor drive system 10000 includes: a motor M, a power module 2000 (such as a three-phase inverter bridge, H-bridge, half-bridge, etc.), and a pre-drive chip 1000 in the above embodiment, wherein the power module 2000 includes a transistor T.

[0063] In summary, the shutdown device, pre-drive chip, and motor drive system for the pre-drive chip in this embodiment of the invention can achieve safe shutdown of the pre-drive chip, eliminating safety hazards. The entire process is automatically executed by hardware without software intervention and does not consume software resources. Furthermore, the voltage detection and counting functions involved in the detection circuit only operate within the time window of the safe shutdown process and automatically shut down after completion, without causing power consumption waste.

[0064] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0066] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0067] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0068] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A shutdown device for a pre-driven chip, characterized in that, The pre-driver chip includes a power control module, an enable control module, and a driver. The device includes a logic circuit and a detection circuit. The logic circuit is adapted to be connected to the power control module, the enable control module, the driver's drive terminal, and the driver's enable terminal, respectively. The detection circuit is connected to the logic circuit and is adapted to be connected to the enable control module. The logic circuit is configured to enable the driver to normally drive the connected transistor and turn off the detection circuit when the enable control module outputs a first level, and to enable the driver to pull down the gate voltage of the transistor and enable the detection circuit to work when the enable control module outputs a second level. The detection circuit is configured to output a second level when the transistor is turned off, thereby triggering the logic circuit to shut down the driver and the detection circuit.

2. The shutdown device for a pre-driven chip according to claim 1, characterized in that, The logic circuit includes: A first logic sub-circuit, connected to the detection circuit and adapted to connect to the power control module, the enable control module, the drive terminal of the driver, and the enable terminal of the driver respectively, is used to enable the driver to normally drive the connected transistor when the enable control module outputs a first level, enable the driver to pull down the gate voltage of the transistor when the enable control module outputs a second level, and turn off the driver when the detection circuit outputs a second level. A second logic sub-circuit, connected to the detection circuit and adapted to connect to the enable control module, is used to turn off the detection circuit when the enable control module outputs a first level, enable the detection circuit to operate when the enable control module outputs a second level, and turn off the detection circuit when the detection circuit outputs a second level.

3. The shutdown device for a pre-driven chip according to claim 2, characterized in that, The first logic sub-circuit includes a first AND gate and an OR gate. The first input terminal of the first AND gate is adapted to be connected to the power control module. The second input terminal of the first AND gate is connected to the first input terminal of the OR gate and is adapted to be connected to the enable control module. The output terminal of the first AND gate is connected to the driving terminal of the driver. The second input terminal of the OR gate is connected to the output terminal of the detection circuit and the second input terminal of the second logic sub-circuit, respectively.

4. The shutdown device for a pre-driven chip according to claim 3, characterized in that, The second logic sub-circuit includes a first NOT gate and a second AND gate. The input terminal of the first NOT gate is adapted to be connected to the enable control module. The output terminal of the first NOT gate is connected to the first input terminal of the second AND gate. The second input terminal of the second AND gate is connected to the second input terminal of the OR gate and the output terminal of the detection circuit, respectively.

5. The shutdown device for a pre-driven chip according to claim 4, characterized in that, The detection circuit includes a detection enable register and a voltage detection unit. The reset terminal of the detection enable register is adapted to be connected to the enable control module. The clock terminal of the detection enable register is connected to the output terminal of the voltage detection unit. The output terminal of the detection enable register is connected to the second input terminal of the OR gate and the second input terminal of the second AND gate, respectively. The enable terminal of the voltage detection unit is connected to the output terminal of the second AND gate. The detection terminal of the voltage detection unit is adapted to be connected to the gate and source of the transistor. The voltage detection unit is configured to detect the gate-source voltage of the transistor when the second AND gate outputs a first level, and output a first level when the gate-source voltage is greater than or equal to a threshold voltage, or when the second AND gate outputs a second level, so that the detection enable register outputs a first level; and output a second level when the gate-source voltage is less than the threshold voltage, so that the detection enable register outputs a second level.

6. The shutdown device for a pre-driven chip according to claim 4, characterized in that, The detection circuit includes a second NOT gate, a counter, an overflow judgment unit, and an overflow status register. The output of the second NOT gate is connected to the second input of the OR gate and the second input of the second AND gate, respectively. The enable terminal of the counter is connected to the output of the second AND gate. The clear terminal of the counter is connected to the input of the second NOT gate and the output of the overflow status register, respectively. The first input of the overflow judgment unit is connected to the output of the counter. The input of the overflow status register is connected to the output of the overflow judgment unit. The reset terminal of the overflow status register is adapted to be connected to the enable control module. Wherein, the counter is used to count the gate pull-down time of the transistor when the second AND gate outputs a first level, and the overflow judgment unit is used to enable the overflow status register to output a first level when the count value of the counter reaches a target value, so as to clear the count value of the counter and enable the second NOT gate to output a second level, wherein the target value is the time required for the gate voltage of the transistor to be pulled down to the turn-off voltage.

7. The shutdown device for a pre-driven chip according to claim 6, characterized in that, The detection circuit further includes a clock source for providing a timing clock to the counter, wherein the target value is determined based on the parameters of the transistor, the driving strength of the driver, and the parameters of the clock source.

8. The shutdown device for a pre-driven chip according to claim 7, characterized in that, The detection circuit further includes a shutdown pull-down time control word register and a memory. The input terminal of the shutdown pull-down time control word register is connected to the memory, and the output terminal of the shutdown pull-down time control word register is connected to the second input terminal of the overflow judgment unit. The memory is used to store the target value, and the shutdown pull-down time control word register is used to load the target value when the pre-driver chip starts up.

9. A pre-driver chip, characterized in that, include: A power control module, an enable control module, and a driver, and a shutdown device for a pre-driven chip as claimed in any one of claims 1-8.

10. A motor drive system, characterized in that, include: The motor, the power module, and the pre-drive chip as described in claim 9, wherein the power module includes transistors.

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