Dual comparison loop control system for switched capacitor dc-dc converter

Abstract

The application discloses a double comparison loop control system for a switched capacitor DC-DC converter, comprising a main comparator, a secondary comparator, a multi-clock triggered D flip-flop, a charge pump and a voltage-controlled oscillator. The application uses the characteristics of the converter output ripple to quickly adjust the reference voltage between the maximum and minimum values of the output voltage ripple by adjusting the number of pulses of the converter driving clock through the comparison of the two loops of the main comparator and the secondary comparator. Since the secondary comparator loop can be triggered multiple times during operation without being affected by the main comparator driving clock signal, the control system of the application enables the converter to quickly recover to a steady state in the case of load transients. The main comparator driving clock signal is generated by the voltage-controlled oscillator, and the frequency thereof is proportional to the size of the load current, thereby reducing the energy loss of the control system under light load, so that the fast response of load transients is realized without losing efficiency.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a dual comparator loop control system for a switched capacitor DC-DC converter. Background Technology

[0002] A switched-capacitor DC-DC converter is a type of switching power supply that converts a fixed DC voltage or a range of DC voltages into another DC voltage. It typically consists of a power switch, a flyback capacitor, and an output capacitor. As a key module of a power management system, the switched-capacitor DC-DC converter can adapt to load changes, ensure stable output voltage, and continuously power the load. In recent years, the rapid development of IoT systems has placed demands on miniaturization and high efficiency in power management units. Compared to switched-inductor DC-DC converters, switched-capacitor DC-DC converters do not require large external inductors, making them a research hotspot in power management units. To adapt to different operating conditions and application scenarios, while ensuring high efficiency, switched-capacitor DC-DC converters should respond to load changes through strategies such as closed-loop feedback control to adjust the frequency. When the load changes from light to heavy, the system should quickly enter a stable operating state, which places stringent requirements on the load transient response time of the switched-capacitor DC-DC converter.

[0003] Traditional control strategies for switched-capacitor DC-DC converters typically employ PFM (Pulse Frequency Modulation) or a single-loop low-side hysteresis comparator scheme to handle load changes. For example, the literature [Y. Lu and J. Jiang. A loop for a multiphase switched-capacitor DC-DC converter with fast transient response and low ripple characteristics. IEEE Solid State Circuits Journal, February 2017, Vol. 52, Article 2, pp. 579-591] proposes a pulse frequency modulation control strategy. However, the limitation of its excessively long pulse frequency modulation loop results in a slow converter response speed during load changes, requiring additional transient response enhancement circuitry. Traditional low-side hysteresis control schemes use a higher frequency fixed-frequency clock to compare the output voltage with the reference voltage, thereby improving the system response time, as illustrated in the literature [N. Butzen and MSJ Steyaert. Scalable charge redistribution: design of a high-efficiency fully integrated switched-capacitor DC-DC converter. IEEE Solid State Circuits Journal, December 2016, Vol. 51, Article 12, pp. 2843-2853]. However, excessively high frequencies can lead to higher power consumption in the controller, impairing the overall system efficiency. Summary of the Invention

[0004] In view of the above, the present invention provides a dual comparator loop control system for a switched capacitor DC-DC converter, which can improve the conversion efficiency of the DC-DC converter under light load and greatly reduce the power consumption generated by the control circuit.

[0005] A dual comparator loop control system for a switched-capacitor DC-DC converter includes:

[0006] The main comparator compares the minimum output voltage ripple of the switched capacitor DC-DC converter with the reference voltage at the rising edge of the clock, generating a pulse increase signal PUMP and a pulse decrease signal SKIP.

[0007] The secondary comparator is turned on after a delay after the converter clock flips. It is used to compare the maximum value of the output voltage ripple of the switched capacitor DC-DC converter with the reference voltage when the rising edge of the clock arrives, and generate two pulse increment signals PUMP2 and PUMP3.

[0008] The multi-clock triggered D flip-flop increments or decrements the converter clock pulses based on the pulse increment signals PUMP, PUMP2, and PUMP3, thereby generating the clock signal to drive the switched capacitor DC-DC converter and the clock signal to drive the secondary comparator.

[0009] The charge pump generates the input voltage of the voltage-controlled oscillator based on the pulse increase signals PUMP2 and PUMP3 and the pulse decrease signal SKIP through switched capacitor technology, which is used to control the increase or decrease of the clock frequency of the main comparator.

[0010] A voltage-controlled oscillator is used to generate a clock signal whose frequency is proportional to the input voltage to drive the main comparator.

[0011] Furthermore, the main comparator includes five NMOS transistors M0, M1, M2, M4, M5 and six PMOS transistors M3, M6, M7, M8, M9, M1, M2, M4, M5. 10 And two CMOS inverters I0 and I1, wherein the source of M0 is grounded, the gate of M0 is connected to the clock signal VCLK, the drain of M0 is connected to the source of M1 and the source of M2, and the gate of M1 is connected to the reference voltage V. REF The drain of M1 is connected to the drain of M3 and the source of M4. The gate of M2 is connected to the output voltage V of the switched capacitor DC-DC converter. OUT The drain of M2 is connected to the source of M5 and the drain of M6. The gate of M3 is connected to the gate of M6, the gate of M7, and the gate of M6. 10 The gates of all M3, M6, M7, M8, and M9 are connected to the clock signal VCLK. 10 The sources of M4 and M8 are all connected to the power supply voltage VDD. The gates of M4 and M8, the drains of M9 and M5, and M...10 The drain of M4 is connected to the input of I0. The drain of M4 is connected to the drain of M7, the drain of M8, the gate of M9, the gate of M5 and the input of I1. The output of I0 generates a pulse decrease signal SKIP, and the output of I1 generates a pulse increase signal PUMP.

[0012] Furthermore, the secondary comparator includes two rising-edge triggered comparators, CMP2 and CMP3, wherein the clock terminal of CMP2 is connected to the clock signal CLK. D The clock terminal of CMP3 is connected to the clock signal CLK. DB The non-inverting input of CMP2 is connected to the non-inverting input of CMP3 and then connected to the reference voltage V. REF The inverting input of CMP2 is connected to the inverting input of CMP3 and then connected to the output voltage V of the switched capacitor DC-DC converter. OUT The output of CMP2 generates a pulse increase signal PUMP2, and the output of CMP3 generates a pulse increase signal PUMP3.

[0013] Furthermore, the D flip-flop includes nine CMOS inverters I2~I 10 The system consists of three delay buffers B0-B2, three 2-input AND gates A0-A2, one 3-input OR gate O1, and four CMOS transmission gates T1-T4. The input of gate I2 is connected to the first input of A0 and to a pulse increment signal PUMP. The output of I2 is connected to the input of B0, the output of B0 is connected to the second input of A0, and the output of A0 is connected to the first input of O1. The input of gate I3 is connected to the first input of A1 and to a pulse increment signal PUMP2. The output of I3 is connected to the input of B1, the output of B1 is connected to the second input of A1, and the output of A1 is connected to the second input of O1. The input of gate I4 is connected to the first input of A2 and to a pulse increment signal PUMP3. The output of I4 is connected to the input of B2, the output of B2 is connected to the second input of A2, the output of A2 is connected to the third input of O1, and the output of O1 is connected to the third input of I2. 10 The input terminal of T1, the first clock terminal of T2, the first clock terminal of T3, and the first clock terminal of T4 are connected together. 10The output terminal is connected to the second clock terminals of T1, T2, T3, and T4. The input terminal of T1 serves as the input terminal of the D flip-flop. The output terminal of T1 is connected to the input terminal of I5 and the output terminal of T2. The output terminal of I5 is connected to the input terminal of T3 and the input terminal of I6. The output terminal of I6 is connected to the input terminal of T2. The output terminal of T3 is connected to the input terminal of I7 and the output terminal of T4. The output terminal of I7 is connected to the input terminal of I9 and the input terminal of I8 and serves as the positive output terminal of the D flip-flop. The output terminal of I9 serves as the inverted output terminal of the D flip-flop. The output terminal of I8 is connected to the input terminal of T4.

[0014] Furthermore, the non-inverting output of the D flip-flop generates a clock signal CLK for driving the switched-capacitor DC-DC converter. SW CLK SW After a delay of T by a delay buffer B3 D A clock signal CLK is generated after a certain duration. D Used to drive comparator CMP2, CLK D After passing through an inverter I 11 Generate clock signal CLK DB The input of the D flip-flop used to drive comparator CMP3 is connected to the inverting output.

[0015] Furthermore, the delay duration T of the delay buffer B3 D Its initial value is the time difference between the minimum and maximum values ​​of the output voltage ripple of the switched capacitor DC-DC converter. Then, its set value is obtained by simulation under the maximum load condition of the system so that it can be applied to the full load range of the system.

[0016] Furthermore, the charge pump includes a 2-input OR gate O2 and a CMOS inverter I. 12 One capacitor C0, two NMOS transistors M 11 and M 12 And two PMOS transistors M 13 and M 14 The two inputs of O2 are connected to pulse increment signals PUMP2 and PUMP3 respectively, and the output of O2 is connected to I. 12 Connected to the input terminal, I 12 The output terminal and M 14 The gate is connected to M. 14 The source is connected to the power supply voltage VDD, M 14 The drain and M 13 The source is connected, M 13 The gate external bias voltage VBP, M 13 The drain and one end of C0 and M 12The drains are connected to generate the input voltage V of the voltage-controlled oscillator. CTRL M 12 The gate external bias voltage VBN, M 12 The source and M 11 The drains are connected, M 11 The gate is connected to the pulse decrease signal SKIP, M 11 The source of C0 and the other end of C0 are both grounded.

[0017] Furthermore, the voltage-controlled oscillator includes three CMOS inverters I. 13 ~I 15 Five NMOS transistors M 21 ~M 24 and M 15 A resistor R1 and five PMOS transistors M 16 ~M 20 M 16 The source and M 17 The source, M 18 The source, M 19 The source and M 20 The sources of M are all connected to the power supply voltage VDD. 15 The input voltage V of the gate-connected voltage-controlled oscillator CTRL M 21 The source and M 22 The source, M 23 The source, M 24 The source of M and one end of R1 are both grounded. 15 The source of M is connected to the other end of R1. 15 The drain and M 16 gate, M 16 Drain, M 17 gate, M 18 gate, M 19 The gate and M 20 The gate is connected to M. 17 The drain and M 21 gate, M 21 Drain, M 22 gate, M 23 The gate and M 24 The gate is connected to M. 22 Drain and I 13 Connect to the grounding terminal, M 18 Drain and I 13 Connected to the power supply terminal, M 19 Drain and I 14 Connected to the power supply terminal, M 23 Drain and I 14 Connect to the grounding terminal, M 20 Drain and I15 Connected to the power supply terminal, M 24 Drain and I 15 Connected to the grounding terminal, I 13 The input terminal and I 15 The output terminal is connected to generate the clock signal VCLK used to drive the main comparator. 13 The output terminal and I 14 Connected to the input terminal, I 14 The output terminal and I 15 The input terminal is connected.

[0018] This invention utilizes the ripple characteristics of the output voltage of a switched-capacitor DC-DC converter. Two comparison loops, a primary comparator and a secondary comparator, ensure the reference voltage is positioned between the maximum and minimum values ​​of the output voltage ripple. The primary comparator guarantees normal operation under steady-state conditions, while the secondary comparator generates clock pulse increment or decrement signals during load changes, adjusting the number of pulses in the converter's drive clock to quickly restore the converter to steady state. Because the secondary comparator can trigger and drive the converter rapidly multiple times, compared to traditional pulse frequency modulation schemes that require waiting for the converter's response after a frequency change before comparison and adjustment, the system's transient response is significantly improved. Furthermore, the primary comparator's drive clock frequency can be adjusted according to load changes, comparing and responding faster under heavy loads and slower under light loads, achieving controller power consumption proportional to load and improving conversion efficiency under light loads. Under steady-state conditions, this invention only requires two comparisons per cycle, significantly reducing the power consumption of the control circuit.

[0019] Compared with existing technologies, this invention utilizes the ripple characteristics of the converter's output voltage. The main comparator compares the minimum output voltage ripple with a reference voltage, and the secondary comparator compares the maximum output voltage ripple with a reference voltage. The number of converter drive clock pulses is increased or decreased based on the comparison results of the main and secondary comparators. Furthermore, this invention adjusts the input voltage of the voltage-controlled oscillator (VCO) based on the comparison results of the main and secondary comparators, thereby adjusting the clock frequency to make the drive clock frequency of the main comparator proportional to the load. In the steady-state cycle, this control strategy performs only two comparisons, reducing the power consumption of the control circuit. This invention achieves steady-state operation by adjusting the converter drive clock so that the reference voltage value falls between the maximum and minimum values ​​of the converter's output voltage ripple. Simulation results show that when the control system of this invention is applied to a recursive switched-capacitor DC-DC converter system, the response time to load current transients (10μA↔1mA) is less than 3μs, and the system closed-loop efficiency reaches 86.2%. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the switched capacitor DC-DC converter and its control system in this invention.

[0021] Figure 2 This is a timing diagram of the dual comparator loop control system for the switched capacitor DC-DC converter in this invention.

[0022] Figure 3 This is a schematic diagram of the main comparator in the control system of the present invention.

[0023] Figure 4 This is a schematic diagram of the structure of a multi-clock triggered D flip-flop in the control system of the present invention.

[0024] Figure 5 This is a schematic diagram of the charge pump and voltage-controlled oscillator in the control system of the present invention.

[0025] Figure 6 This is a schematic diagram of the load transient response of the control system of the present invention. Detailed Implementation

[0026] To describe the present invention in more detail, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] Figure 1 It includes a switched-capacitor DC-DC converter and a load capacitor C. L Load resistance R L The invention also describes the circuit structure of the dual-comparison loop control system, which consists of a main comparator, a secondary comparator, a multi-clock triggered D flip-flop, a charge pump, and a voltage-controlled oscillator.

[0028] like Figure 1 As shown, due to the output voltage V of the switched capacitor DC-DC converter OUT There is ripple, and the output voltage V in each cycle is... OUT Does there exist a minimum value V? OUT(MIN) and maximum value V OUT(MAX) Reference voltage V REF It is a relatively stable DC value. When the system is in steady state, the reference voltage V REF It should be within the range of the output voltage ripple, that is, satisfy V OUT(MIN) <V REF <V OUT(MAX) At this time, the main comparator CMP1 is driven by the clock signal VCLK generated by the voltage-controlled oscillator, and compares V once every VCLK clock cycle. REF With V OUT(MIN) The PUMP signal increments by one pulse (generating a rising edge), while the SKIP signal decrements by remaining low. A multi-clock triggered D flip-flop receives the rising edge of the PUMP signal and triggers it once, causing the converter to drive the clock signal CLK. SWA flip produces a rising edge (or falling edge), CLK SW The flip is delayed by time T after passing through delay buffer B3. D , making CLK D The toggle generates a rising edge (or a falling edge) for the clock signal CLK. D After passing through CMOS inverter I 11 Then make the clock signal CLK DB The toggle generates a falling edge (or a rising edge), driving the secondary comparators CMP2 and CMP3 for comparison. Since the clock signals of secondary comparators CMP2 and CMP3 are inverted (180° out of phase), only one of comparators CMP2 and CMP3 is in normal operation when the secondary comparison loop is working, while the other waits for the clock to drive it. A suitable clock signal T is selected. D Delay, the comparator can be used for V REF and V OUT(MAX) A comparison is made, generating pulse-increment signals PUMP2 and PUMP3. In steady state, both PUMP2 and PUMP3 are low, i.e., V... REF <V OUT(MAX) This indicates that the converter drives the clock signal CLK. SW It has reached near its optimal value. In steady state, the multi-clock triggered D flip-flop toggles only once per VCLK clock cycle, generating a uniformly pulsed converter clock CLK. SW The switched capacitor DC-DC converter is stably driven by a two-phase non-overlapping clock generation circuit.

[0029] like Figure 2 As shown, when the system load changes from heavy load to light load, the minimum ripple value of the output voltage of the switched capacitor DC-DC converter will be higher than the reference voltage, i.e., V. OUT(MIN) >V REF When the rising edge of the clock signal VCLK arrives, the main comparator compares and obtains V. OUT(MIN) >V REF When the pulse decrease signal SKIP changes from low to high, and the pulse increase signal PUMP remains low, the multi-clock triggered D flip-flop is not triggered, thus driving the converter's clock CLK. SW Without flipping, the secondary comparator is not triggered due to the load R. L The function of switched capacitor DC-DC converter output voltage V OUT It gradually decreases until the next rising edge of VCLK arrives. When the main comparator detects V... OUT(MIN) <V REF When the pulse increment signal PUMP generates a high level, it triggers the multi-clock triggered D flip-flop to flip, the secondary comparator is re-triggered, and the output voltage V of the switched capacitor DC-DC converter is adjusted. OUTUntil the reference voltage V REF Falling back to V OUT The ripple is between its maximum and minimum values. During this process, the pulse reduction signal SKIP, through a charge pump, reduces the input voltage V of the voltage-controlled oscillator. CTRL The comparison frequency of the main comparator gradually decreases as the load decreases, thus reducing the power consumption of the controller under light load conditions.

[0030] When the load changes from light load to heavy load, such as Figure 2 As shown, the output voltage drops due to a surge in load, causing V to... OUT The maximum value of the ripple is less than the reference voltage V. REF V OUT(MAX) <V REF When the rising edge of the VCLK clock arrives, the main comparator compares and obtains V. OUT(MIN) <V REF When the pulse increase signal PUMP changes from low to high, and the pulse decrease signal SKIP remains low, the multi-clock triggered D flip-flop produces a toggle, driving the switched-capacitor DC-DC converter's clock CLK. SW A rising edge (or a falling edge) is generated, and the switched-capacitor DC-DC converter performs one charge transfer, V OUT Slow rise. Clock signal CLK SW The change is delayed by time T after passing through delay buffer B3. D The comparator is then triggered to perform the comparison and obtain V. OUT(MAX) <V REF The pulse increment signal PUMP2 or PUMP3 generates a pulse (changing from low to high), triggering the clock CLK of the driver converter. SW The flip-flop generates a falling edge (or a rising edge), driving the switched-capacitor DC-DC converter to output capacitor C. L Charging, output voltage V OUT Continue to rise. Delay T D The selection of T is determined by the time difference between the minimum and maximum output voltage ripple under maximum load conditions of the switched capacitor DC-DC converter. Under maximum load conditions, T is selected... D This delay value is then applicable across the entire system load range. Clock signal CLK SW The flip is delayed by time T after passing through delay buffer B3. D The comparator is then triggered again. The comparator's ability to be triggered multiple times significantly reduces the response time to load surges. Pulse increment signals PUMP2 and PUMP3, via a charge pump, increase the input voltage V of the voltage-controlled oscillator. CTRL As the load increases, the comparison frequency of the main comparator also increases until the reference voltage V... REFReset to output voltage V OUT The ripple enters a stable state between its maximum and minimum values.

[0031] like Figure 3 As shown, the main comparator includes NMOS transistors M0~M2 and M4~M5, and PMOS transistors M3 and M6~M7. 10 And CMOS inverters I0 and I1, where NMOS transistor M0 acts as the tail current source of the comparator when VCLK is high, and NMOS transistors M1 and M2 are the two input transistors, respectively inputting the gate voltage to V. REF and V OUT This is proportionally converted to current. When the clock VCLK is high, the voltages of OUT+ and OUT- gradually decrease from VDD. REF >V OUT Because the input transistor is an NMOS transistor, the current flowing through NMOS transistor M1 is larger, and the signal OUT- decreases faster. NMOS transistors M4, M8, M5, and M9 form a latching circuit consisting of two CMOS inverters connected end-to-end. When the signal OUT- decreases below the flip-point of the CMOS inverter formed by NMOS transistors M5 and M9, the signal OUT+ will become high, and the latching circuit will store both signals OUT- and OUT+ until VCLK becomes high again. PMOS transistors M3, M6, M7, and M8... 10 To reset the switching transistor, when the clock VCLK is low, the signals OUT+ and OUT- are reset to VDD, that is, the output signals PUMP and SKIP are reset to low.

[0032] like Figure 4 As shown, the multi-clock triggered D flip-flop includes CMOS inverters I2~I 10 The system consists of delay buffers B0-B2, 2-input AND gates A0-A2, 3-input OR gate O1, and CMOS transmission gates T1-T4. The pulse increment signal PUMP, after passing through CMOS inverter I2 and delay buffer B0, is ANDed with PUMP to extract its rising edge. Similarly, the rising edges of pulse increment signals PUMP2 and PUMP3 are also extracted. The 2-input AND gates A0-A2 generate signals CKP, CKP2, and CKP3, which serve as the output of the 3-input OR gate O1. The clock signal CLKUP generated by the 3-input OR gate O1 contains the rising edge information of the three pulse increment signals. CLKUP is then passed through inverter I1... 10The inverted clock signal CLKUPB is obtained. CMOS transmission gates T1~T4 and CMOS inverters I5~I9 form a D flip-flop. CMOS transmission gate T2, CMOS inverters I5 and I6 form a latch. CMOS transmission gate T4, CMOS inverters I7 and I8 form a latch. When the clock signal CLKUP is low, the input signal D is stored in the first latch, and the second latch is disconnected from the first latch, keeping the output signal Q unchanged. When the clock signal CLKUP is high, the output signal Q of the second latch is refreshed to the value of the input signal D, and the first latch is disconnected from the input signal, keeping the latched value. Therefore, this flip-flop can make the output signal equal to the input signal (Q=D) when the clock signal CLKUP is rising, while keeping the output signal Q unchanged at other times. The output signal QB is the inverted version of the output signal Q. When the input signal D and the output signal QB are connected together, the rising edge of the clock signal CLKUP causes the output signal Q to flip once, while remaining unchanged at other times.

[0033] like Figure 5 As shown, the charge pump includes a PMOS transistor M 13 ~M 14 NMOS transistor M 11 ~M 12 2-input OR gate O2, CMOS inverter I 12 And capacitor C0, where PMOS transistor M 14 The gate of the CMOS inverter I 12 The output terminal is connected in parallel to the UP signal and the NMOS transistor M. 11 The gate of the circuit is connected to the SKIP signal generated by the main comparator, which controls the upper and lower current sources to turn on or off, thereby generating the input voltage V of the voltage-controlled oscillator. CTRL The voltage-controlled oscillator includes resistor R1 and NMOS transistor M. 15 and M 21 ~M 24 PMOS transistor M 16 ~M 20 and CMOS inverter I 13 ~I 15 Among them, NMOS transistor M 15 The source of the NMOS transistor is connected to one end of resistor R1, forming source negative feedback, which causes the NMOS transistor M... 15 The current flowing through the NMOS transistor M 15 Gate voltage V CTRL The relationship is relatively linear, with PMOS transistor M... 16 ~M 20 and NMOS transistor M 21 ~M 24 As a current mirror, replicate NMOS transistor M 15The current flowing through it controls the CMOS inverter I. 13 ~I 15 The charging and discharging current is used to control the delay time. CMOS inverter I 13 ~I 15 An odd-order loop is formed, which can oscillate and generate a clock signal VCLK under the influence of slight disturbances, with an input voltage V. CTRL The larger the value, the higher the frequency of the clock signal VCLK generated by the voltage-controlled oscillator.

[0034] like Figure 6 As shown, when the load current I LOAD When the voltage suddenly changes from 1mA to 10μA, the pulse increase signals PUMP2 and PUMP3 remain at a low level, while the pulse decrease signal SKIP changes from a low level to a high level. The input voltage V of the voltage-controlled oscillator is then obtained via a charge pump. CTRL Continuously decrease until the reference voltage V REF Reaching the output voltage V OUT Between the maximum and minimum values ​​of ripple. When the load current I... LOAD When the voltage suddenly changes from 10μA to 1mA, the pulse increment signal PUMP goes high, triggering the converter clock CLK. SW The flip, after T D After a delay, comparators CMP2 and CMP3 are triggered for comparison. The pulse increment signals PUMP2 and PUMP3 change from low to high, which again triggers the converter clock CLK. SW The flip, V OUT The voltage then gradually increases until it reaches the reference voltage V. REF Returning to the output voltage V OUT The ripple value is between its maximum and minimum values. The delay T of delay buffer B3. D This is a constant value obtained from simulation under the system's maximum load condition, and it is applicable to the entire load range of the system. In this system, T... D Take 10.8 ns. For example... Figure 6 As shown, the load current I LOAD When the voltage drops from 1 mA to 10 μA, the transient response time of the system is 1 μs, and when the voltage drops from 10 μA to 1 mA, the transient response time of the system is 2.8 μs, which shows that the system of the present invention has the ability to respond quickly to load transients.

[0035] The control system of this invention compares two loops, a primary comparator and a secondary comparator, and utilizes the output ripple characteristics of a switched-capacitor DC-DC converter. By adjusting the number of pulses in the converter's drive clock, the reference voltage V is rapidly adjusted. REF Adjust to output voltage V OUTThe ripple ranges between its maximum and minimum values. Since the secondary comparator loop can be triggered multiple times during operation without being affected by the main comparator drive clock signal VCLK, this control system enables the switched-capacitor DC-DC converter to quickly recover to steady state under load transients. The main comparator drive clock signal VCLK is generated by a voltage-controlled oscillator, and its frequency is proportional to the load current, reducing the energy loss of the control system under light loads, thus achieving a fast response to load transients without sacrificing efficiency. Simulation results show that the response time of the control system of this invention does not exceed 3μs under a load current transient from 10μA to 1mA.

[0036] The above description of the embodiments is provided to enable those skilled in the art to understand and apply the present invention. Those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made to the present invention by those skilled in the art based on the disclosure thereof should be within the scope of protection of the present invention.

Claims

1. A dual comparator loop control system for a switched-capacitor DC-DC converter, characterized in that, include: The main comparator compares the minimum output voltage ripple of the switched capacitor DC-DC converter with the reference voltage at the rising edge of the clock, generating a pulse increase signal PUMP and a pulse decrease signal SKIP. The secondary comparator is turned on after a delay after the converter clock flips. It is used to compare the maximum value of the output voltage ripple of the switched capacitor DC-DC converter with the reference voltage when the rising edge of the clock arrives, and generate two pulse increment signals PUMP2 and PUMP3. The multi-clock triggered D flip-flop increments or decrements the converter clock pulses based on the pulse increment signals PUMP, PUMP2, and PUMP3, thereby generating the clock signal to drive the switched capacitor DC-DC converter and the clock signal to drive the secondary comparator. The charge pump generates the input voltage of the voltage-controlled oscillator based on the pulse increase signals PUMP2 and PUMP3 and the pulse decrease signal SKIP through switched capacitor technology, which is used to control the increase or decrease of the clock frequency of the main comparator. A voltage-controlled oscillator is used to generate a clock signal whose frequency is proportional to the input voltage to drive the main comparator; The secondary comparator includes two rising-edge triggered comparators, CMP2 and CMP3, wherein the clock input of CMP2 is connected to the clock signal CLK. D The clock terminal of CMP3 is connected to the clock signal CLK. DB The non-inverting input of CMP2 is connected to the non-inverting input of CMP3 and then connected to the reference voltage V. REF The inverting input of CMP2 is connected to the inverting input of CMP3 and then connected to the output voltage V of the switched capacitor DC-DC converter. OUT The output of CMP2 generates a pulse increase signal PUMP2, and the output of CMP3 generates a pulse increase signal PUMP3. The non-inverting output of the D flip-flop generates a clock signal CLK for driving the switched-capacitor DC-DC converter. SW CLK SW After a delay of T by a delay buffer B3 D A clock signal CLK is generated after a certain duration. D Used to drive comparator CMP2, CLK D After passing through an inverter I 11 Generate clock signal CLK DB The input of the D flip-flop used to drive comparator CMP3 is connected to the inverting output.

2. The dual comparator loop control system for a switched-capacitor DC-DC converter according to claim 1, characterized in that: The main comparator includes five NMOS transistors M0, M1, M2, M4, and M5, and six PMOS transistors M3, M6, M7, M8, M9, and M1. 10 And two CMOS inverters I0 and I1, wherein the source of M0 is grounded, the gate of M0 is connected to the clock signal VCLK, the drain of M0 is connected to the source of M1 and the source of M2, and the gate of M1 is connected to the reference voltage V. REF The drain of M1 is connected to the drain of M3 and the source of M4. The gate of M2 is connected to the output voltage V of the switched capacitor DC-DC converter. OUT The drain of M2 is connected to the source of M5 and the drain of M6. The gate of M3 is connected to the gate of M6, the gate of M7, and the gate of M6. 10 The gates of all M3, M6, M7, M8, and M9 are connected to the clock signal VCLK. 10 The sources of M4 and M8 are all connected to the power supply voltage VDD. The gates of M4 and M8, the drains of M9 and M5, and M... 10 The drain of M4 is connected to the input of I0. The drain of M4 is connected to the drain of M7, the drain of M8, the gate of M9, the gate of M5 and the input of I1. The output of I0 generates a pulse decrease signal SKIP, and the output of I1 generates a pulse increase signal PUMP.

3. The dual comparator loop control system for a switched-capacitor DC-DC converter according to claim 1, characterized in that: The D flip-flop includes nine CMOS inverters I2~I 10 The system consists of three delay buffers B0-B2, three 2-input AND gates A0-A2, one 3-input OR gate O1, and four CMOS transmission gates T1-T4. The input of gate I2 is connected to the first input of A0 and to a pulse increment signal PUMP. The output of I2 is connected to the input of B0, the output of B0 is connected to the second input of A0, and the output of A0 is connected to the first input of O1. The input of gate I3 is connected to the first input of A1 and to a pulse increment signal PUMP2. The output of I3 is connected to the input of B1, the output of B1 is connected to the second input of A1, and the output of A1 is connected to the second input of O1. The input of gate I4 is connected to the first input of A2 and to a pulse increment signal PUMP3. The output of I4 is connected to the input of B2, the output of B2 is connected to the second input of A2, the output of A2 is connected to the third input of O1, and the output of O1 is connected to the third input of I2. 10 The input terminal of T1, the first clock terminal of T2, the first clock terminal of T3, and the first clock terminal of T4 are connected together. 10 The output terminal is connected to the second clock terminals of T1, T2, T3, and T4. The input terminal of T1 serves as the input terminal of the D flip-flop. The output terminal of T1 is connected to the input terminal of I5 and the output terminal of T2. The output terminal of I5 is connected to the input terminal of T3 and the input terminal of I6. The output terminal of I6 is connected to the input terminal of T2. The output terminal of T3 is connected to the input terminal of I7 and the output terminal of T4. The output terminal of I7 is connected to the input terminal of I9 and the input terminal of I8 and serves as the positive output terminal of the D flip-flop. The output terminal of I9 serves as the inverted output terminal of the D flip-flop. The output terminal of I8 is connected to the input terminal of T4.

4. The dual comparator loop control system for a switched-capacitor DC-DC converter according to claim 1, characterized in that: The delay duration T of the delay buffer B3 D Its initial value is the time difference between the minimum and maximum values ​​of the output voltage ripple of the switched capacitor DC-DC converter. Then, its set value is obtained by simulation under the maximum load condition of the system so that it can be applied to the full load range of the system.

5. The dual comparator loop control system for a switched-capacitor DC-DC converter according to claim 1, characterized in that: The charge pump includes a 2-input OR gate O2 and a CMOS inverter I. 12 One capacitor C0, two NMOS transistors M 11 and M 12 And two PMOS transistors M 13 and M 14 The two inputs of O2 are connected to pulse increment signals PUMP2 and PUMP3 respectively, and the output of O2 is connected to I. 12 Connected to the input terminal, I 12 The output terminal and M 14 The gate is connected to M. 14 The source is connected to the power supply voltage VDD, M 14 The drain and M 13 The source is connected, M 13 The gate external bias voltage VBP, M 13 The drain and one end of C0 and M 12 The drains are connected to generate the input voltage V of the voltage-controlled oscillator. CTRL M 12 The gate external bias voltage VBN, M 12 The source and M 11 The drains are connected, M 11 The gate is connected to the pulse decrease signal SKIP, M 11 The source of C0 and the other end of C0 are both grounded.

6. The dual comparator loop control system for a switched-capacitor DC-DC converter according to claim 1, characterized in that: The voltage-controlled oscillator includes three CMOS inverters I 13 ~I 15 Five NMOS transistors M 21 ~M 24 and M 15 A resistor R1 and five PMOS transistors M 16 ~M 20 M 16 The source and M 17 The source, M 18 The source, M 19 The source and M 20 The sources of M are all connected to the power supply voltage VDD. 15 The input voltage V of the gate-connected voltage-controlled oscillator CTRL M 21 The source and M 22 The source, M 23 The source, M 24 The source of M and one end of R1 are both grounded. 15 The source of M is connected to the other end of R1. 15 The drain and M 16 gate, M 16 Drain, M 17 gate, M 18 gate, M 19 The gate and M 20 The gate is connected to M. 17 The drain and M 21 gate, M 21 Drain, M 22 gate, M 23 The gate and M 24 The gate is connected to M. 22 Drain and I 13 Connect to the grounding terminal, M 18 Drain and I 13 Connected to the power supply terminal, M 19 Drain and I 14 Connected to the power supply terminal, M 23 Drain and I 14 Connect to the grounding terminal, M 20 Drain and I 15 Connected to the power supply terminal, M 24 Drain and I 15 Connected to the grounding terminal, I 13 The input terminal and I 15 The output terminal is connected to generate the clock signal VCLK used to drive the main comparator. 13 The output terminal and I 14 Connected to the input terminal, I 14 The output terminal and I 15 The input terminal is connected.

Images