Nonlinear PWM signal generation method and circuit based on adjustable duty ratio

Abstract

The invention relates to the technical field of PWM, and provides a non-linear PWM signal generation method and circuit based on an adjustable duty ratio, and the method comprises the steps: carrying out the counting of PWM cycles based on a clock cycle; the PWM cycle counting result is compared with a high level counting threshold value, a PWM signal is output according to a comparison result, and a nonlinear duty ratio result can be output through clock fine tuning. According to the invention, PWM signal generation is realized through PWM period counting and comparison with a high level counting threshold, the whole process does not need to pre-store a lookup table of a frequency division number and does not adopt multiplication and division, compared with a traditional method, multiplication and division operation can be reduced, the circuit area can be reduced, the circuit area of a single PWM channel can be reduced to 1 / 2 of that of a traditional scheme, and the circuit area can be reduced to 1 / 2 of that of the traditional scheme. The method is especially suitable for a multi-channel PWM integration scene.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of PWM technology, in particular to a nonlinear PWM signal generation method and circuit based on adjustable duty cycle. BACKGROUND

[0002] The pulse width modulation (PWM) signal generation technology is particularly suitable for scenarios that require nonlinear period variation and support high-precision duty cycle adjustment, such as motor control, power management, light adjustment, etc.

[0003] Currently, the PWM period control is usually implemented by precomputing the division number and storing it in a lookup table. According to the target period and the reference clock frequency, the division number (i.e. the number of clock pulses in the period) corresponding to each nonlinear period is precomputed and stored in the lookup table for real-time calling by the circuit. The bit width of the PWM counter is determined by the maximum division number (for example, if the reference clock is 32MHz and the maximum PWM output period is 200Hz, the corresponding division number is 160000, then the counter bit width needs to be 18 bits, resulting in an increase in circuit resource occupation). For duty cycle adjustment, the formula "target value of high-level count threshold Ton = (duty cycle control value / total number of duty cycles) x division number" is used. This formula involves multiplication and division operations, which not only increases the circuit delay, but also requires additional operation units (such as multipliers and dividers), further increasing the circuit area. SUMMARY

[0004] The present application aims to provide a nonlinear PWM signal generation method and circuit based on adjustable duty cycle to reduce multiplication and division operations and reduce circuit area.

[0005] In a first aspect, the present application provides a nonlinear PWM signal generation method based on adjustable duty cycle, comprising: counting the PWM period based on the clock period; comparing the PWM period count result with the high-level count threshold, and outputting the PWM signal according to the comparison result.

[0006] Further, the clock period and the PWM period have an integer multiple relationship.

[0007] Further, when the clock period and the PWM period are not in an integer multiple relationship, the reference clock frequency is fine-tuned to make the clock period and the PWM period have an integer multiple relationship.

[0008] Further, the reference clock frequency is dynamically fine-tuned using a phase-locked loop.

[0009] Further, the PWM signal output according to the comparison result comprises: output a high level if the PWM period count result is greater than the high level count threshold value; output a low level if the PWM period count result is less than or equal to the high level count threshold value.

[0010] Further, the high level count threshold value is a duty cycle target value.

[0011] In a second aspect, the present application provides a non-linear PWM signal generation circuit based on adjustable duty cycle, comprising: a counter for counting a PWM period based on a clock period; a comparator for comparing a PWM period count result with a high level count threshold value, and outputting a PWM signal according to the comparison result.

[0012] Further, the non-linear PWM signal generation circuit based on adjustable duty cycle further comprises a phase-locked loop; the phase-locked loop is used to make the clock period and the PWM period have an integer multiple relationship by fine-tuning the reference clock frequency when the clock period and the PWM period are not in an integer multiple relationship.

[0013] Further, the comparator is specifically used for: outputting a high level if the PWM period count result is greater than the high level count threshold value; outputting a low level if the PWM period count result is less than or equal to the high level count threshold value.

[0014] Further, the high level count threshold value is a duty cycle target value.

[0015] In summary, the main design of the present application includes "fixed period count fraction + clock fine-tuning + simplified duty cycle mapping", and the beneficial effects of the present application are: 1. The present application realizes PWM signal generation by PWM period counting and comparison with a high level count threshold value, the entire process does not need to pre-store a lookup table of frequency division numbers and does not use multiplication and division, compared with the traditional method, multiplication and division operations can be reduced and the circuit area can be reduced, the circuit area of a single PWM channel can be reduced to 1 / 2 of the traditional scheme, and it is especially suitable for multi-channel PWM integrated scenarios.

[0016] 2. The present application realizes that the clock period and the PWM period have an integer multiple relationship by fine-tuning the clock frequency, and the clock signal only needs to be based on a small range of standard clock jitter to meet the demand.

[0017] 3. The present application simplifies the duty cycle mapping, and still realizes the adjustment of the duty cycle precision under the fixed period and the generation of the non-linear period, and meets the actual application demand. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1This is a flowchart of a nonlinear PWM signal generation method based on adjustable duty cycle proposed in an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of counting PWM cycles and fine-tuning the clock based on the clock cycle in an embodiment of the present invention.

[0020] Figure 3 This is a structural diagram of a nonlinear PWM signal generation circuit based on an adjustable duty cycle proposed in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0023] Example like Figure 1 As shown, this embodiment of the invention proposes a method for generating nonlinear PWM signals based on adjustable duty cycle, including: S100 counts PWM cycles based on clock cycles; S200 compares the PWM cycle count result with the high-level count threshold and outputs the PWM signal based on the comparison result.

[0024] This invention generates PWM signals by counting PWM cycles and comparing them with a high-level counting threshold. The entire process does not require a lookup table for pre-stored frequency division numbers and does not use multiplication and division. Compared with traditional methods, it can reduce multiplication and division operations and reduce circuit area. The circuit area of ​​a single PWM channel can be reduced to 1 / 2 of the traditional solution, which is especially suitable for multi-channel PWM integration scenarios.

[0025] The following details the specific implementation of the nonlinear PWM signal generation method based on adjustable duty cycle.

[0026] S100 counts PWM cycles based on clock cycles.

[0027] In this embodiment of the invention, the PWM period is divided into a base counting unit according to the clock period by a fixed period counting, without relying on the maximum frequency division to expand the bit width. For example... Figure 2 As shown, when counting the PWM period T_pwm based on the clock period, as the PWM period increases, the clock period of the clock signal typ_clk can increase the number of divisible parts of the PWM period pwm_cut. For example, a 10MHz clock can divide a 500KHz PWM into 20 parts and a 50KHz PWM into 200 parts.

[0028] Specifically, the clock period and the PWM period are integer multiples of each other to accurately divide the PWM period according to the clock period. When the clock period and the PWM period are not integer multiples of each other, the clock period and the PWM period can be fine-tuned to make them integer multiples of each other, ensuring that the PWM period is exactly equal to the clock period × n, where n is an integer, and ensuring that the counting units within the PWM period perfectly match the number of counts in the fixed period. Preferably, a phase-locked loop (PLL) can be used to dynamically fine-tune the reference clock frequency. Figure 2 As shown, the clock fine-tuning ratio clk_adj is not directly related to the PWM period. It is mainly related to the fractional part of the PWM period divided by the clock period in the reference unit. Therefore, the clock signal only needs to be jittered within a very small range based on the standard clock to meet the requirements.

[0029] S200 compares the PWM cycle count result with the high-level count threshold and outputs the PWM signal based on the comparison result.

[0030] In this embodiment of the invention, the duty cycle target value is directly used as the high-level counting threshold Ton, and the specific comparison includes: If the PWM cycle count result is greater than the high-level count threshold, output a high level; If the PWM cycle count result is less than or equal to the high-level count threshold, output a low level.

[0031] Therefore, based on the aforementioned reduction of multiplication and division operations and reduction of circuit area, this invention can still achieve duty cycle precision adjustment and nonlinear period generation under a fixed period by simplifying duty cycle mapping, thus meeting the needs of practical applications.

[0032] Based on the same technological concept, such as Figure 3 As shown, this embodiment of the invention also provides a nonlinear PWM signal generation circuit based on an adjustable duty cycle, comprising: A counter used to count PWM cycles based on the clock cycle; The comparator is used to compare the PWM cycle count result with the high-level count threshold and output the PWM signal based on the comparison result.

[0033] Likewise, it is required that the clock period and the PWM period have an integer multiple relationship. The adjustable duty cycle based nonlinear PWM signal generation circuit further comprises a phase-locked loop; the phase-locked loop is used to make the clock period and the PWM period have an integer multiple relationship by fine-tuning the reference clock frequency when the clock period and the PWM period are not an integer multiple.

[0034] Other designs and working principles in the circuit can refer to the descriptions in the foregoing method embodiments, which will not be described herein.

[0035] The above only describes preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for generating nonlinear PWM signals based on adjustable duty cycle, characterized in that, include: PWM cycle counting is based on clock cycle; The PWM cycle count result is compared with the high-level count threshold, and the PWM signal is output based on the comparison result.

2. The nonlinear PWM signal generation method based on adjustable duty cycle according to claim 1, characterized in that, The clock period and the PWM period are integer multiples of each other.

3. The nonlinear PWM signal generation method based on adjustable duty cycle according to claim 2, characterized in that, When the clock period and the PWM period are not integer multiples, the clock period and the PWM period are made to be integer multiples by fine-tuning the reference clock frequency.

4. The nonlinear PWM signal generation method based on adjustable duty cycle according to claim 3, characterized in that, A phase-locked loop is used to dynamically fine-tune the reference clock frequency.

5. The nonlinear PWM signal generation method based on adjustable duty cycle according to claim 1, characterized in that, The step of outputting a PWM signal based on the comparison result includes: If the PWM cycle count result is greater than the high-level count threshold, output a high level; If the PWM cycle count result is less than or equal to the high-level count threshold, output a low level.

6. The nonlinear PWM signal generation method based on adjustable duty cycle according to claim 1 or 5, characterized in that, The high-level counting threshold is the duty cycle target value.

7. A nonlinear PWM signal generation circuit based on adjustable duty cycle, characterized in that, include: A counter used to count PWM cycles based on the clock cycle; The comparator is used to compare the PWM cycle count result with the high-level count threshold and output the PWM signal based on the comparison result.

8. The nonlinear PWM signal generation circuit based on adjustable duty cycle according to claim 7, characterized in that, It also includes a phase-locked loop; the phase-locked loop is used to make the clock period and PWM period an integer multiple by fine-tuning the reference clock frequency when the clock period and PWM period are not integer multiples.

9. The nonlinear PWM signal generation circuit based on adjustable duty cycle according to claim 7, characterized in that, The comparator is specifically used for: If the PWM cycle count result is greater than the high-level count threshold, output a high level; If the PWM cycle count result is less than or equal to the high-level count threshold, output a low level.

10. The nonlinear PWM signal generation circuit based on adjustable duty cycle according to claim 7, characterized in that, The high-level counting threshold is the duty cycle target value.

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