Synchronous unweighted code counter

Abstract

The invention discloses a synchronous unweighted code counter, and relates to the technical field of array image sensors. The whole N-bit synchronous unweighted code counter is formed by 2N D triggers of the same type, and the triggers are controlled by the same clock signal and can generate code words with Gray code characteristics. Due to the fact that the synchronous unweighted code counter is driven by the same clock signal, the problem of delayed matching between bits of code words does not exist. Therefore, by replacing an asynchronous Gray code counter in a multi-ADC sharing counter scene with the counter, the situation that a local latch latches wrong data due to the fact that the actual delay of a delay matching link does not accord with a design value can be effectively avoided, the stability of a system and the accuracy of data are further improved, and the reliability of the system is improved. And the method adapts to the development trend that the reading speed of a large-area-array image sensor is higher.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of array image sensors, and in particular to a synchronous non-weighted code counter. BACKGROUND

[0002] When multiple Analog-to-Digital Converters (ADCs) share a counter, the design of the counter circuit is crucial. In the design of a multi-ADC shared counter, if there is a delay between the bits of the counter code, it will cause the latch of the ADC channel to latch to the wrong data, and thus cause the conversion result to deviate. The ordinary binary code is a weighted code, and there are multiple bits different between any two adjacent code words. Each time the counter counts, multiple signals change. Gray code is a reliable code. Compared with ordinary binary code, it is a non-weighted code, and there is only one bit different between any two adjacent code words, that is, only one bit of the code word changes in level each time the counter counts. Therefore, when using a Gray code counter instead of a binary counter in the scenario of a multi-ADC shared counter, even if the latch error occurs due to the delay between the bits of the digital code, the impact is limited, which means that the Gray code counter can work at a lower error rate in a large array image sensor with higher speed requirements.

[0003] Chinese patent CN116488640A discloses a double-edge triggered asynchronous Gray code counter circuit, as shown in Figure 1 The D flip-flop in the circuit has two types, where Rise1 is a D flip-flop triggered by a rising edge, and Fall1, Fall2 and Fall3 are D flip-flops triggered by falling edges. The D flip-flop of the first stage of flip-flop circuit is Rise1, the QB end data of Rise1 returns to the D end, the clock signal Clock is connected to the input end CLK, the XB signal of Rise1 is input to the CLK end of Fall1, and the non-inverted output ends Q(0), Q(1), Q(2) and Q(3) of Rise1, Fall1, Fall2 and Fall3 are used as the bit numbers of the Gray code. However, Figure 1The asynchronous Gray code counter shown is driven asynchronously by a clock signal, resulting in a delay mismatch during codeword generation. If this counter is used in an array image sensor with a shared ADC counter, an additional delay matching circuit is required; otherwise, the local latch will latch incorrect data due to the delay mismatch. Theoretically, a delay matching link can effectively solve the delay mismatch problem between the bits of the asynchronous Gray code counter's output codeword. However, in circuit manufacturing and practical applications, many factors can influence the actual delay, causing a deviation between the actual delay and the intended delay. This makes it impossible to completely solve the data latching error caused by the delay of each bit of the codeword in the latch. Summary of the Invention

[0004] The purpose of this invention is to provide a synchronous unweighted code counter, which solves the problem that existing asynchronous Gray code counters in multi-ADC shared scenarios suffer from deviations between the actual delay of the delay matching link and the design value due to various adverse factors, resulting in the local latch latching incorrect data.

[0005] The technical solution proposed in this invention is: a synchronous unweighted code counter, characterized in that: it possesses the feature that only one bit differs between two adjacent Gray code values, and the bit correspondence between its Gray code and binary code is 2... (N-1) The unweighted code corresponds to N bits of binary code. The entire N-bit synchronous unweighted code counter requires 2... N The synchronous unweighted code counter circuit consists of two identical D flip-flops with set and reset functions, all controlled by the same clock signal. The positive output Q of each stage of the D flip-flop between the first and last two stages is connected to the input D of the next stage, and the positive output Q of the last stage is connected to the input D of the first stage. (N-1) The set input (SET) and the last 2 D flip-flops (N-1) The reset terminals (RST) of each D flip-flop are all connected to a low level. The first two stages of the synchronous unweighted code counter circuit... (N-1) The reset terminal (RST) and the last two D flip-flops (N-1) The set (SET) terminals of each D flip-flop are uniformly connected to the Reset signal line. The first two terminals of the synchronous unweighted code counter circuit... (N-1) The positive outputs Q(0)~Q(2) of each D flip-flop (N-1)-1) is the required unweighted code. The 3-bit synchronous unweighted code counter with N=3 is composed of 8 D flip-flops (DFF(1)~DFF(8)), and the positive input of the first 4 D flip-flops (DFF(1)~DFF(4)) will output a set of 4-bit code words Q(0)~Q(3) with Gray code characteristics. The specific implementation of the 3-bit synchronous unweighted code counter circuit is as follows: the RST input of the D flip-flops DFF(1)~DFF(4) is connected to the Reset signal, and the SET input is connected to 0 (low level); the SET input of the D flip-flops DFF(5)~DFF(8) is connected to the Reset signal, and the RST input is connected to 0 (low level). The D flip-flops DFF(1)~DFF(8) are connected to the signal in the manner described above. The 3-bit synchronous unweighted code counter circuit is connected end-to-end. The output Q of D flip-flop DFF(8) is connected to the input D of D flip-flop DFF(1). The D flip-flops inside the circuit are connected so that the output Q of the previous stage D flip-flop is connected to the input D of the next stage D flip-flop, forming a ring shift counter. The outputs Q(0) to Q(3) of the positive inputs of DFF(1) to DFF(4) constitute the number of bits of each term of the unweighted code. When the 3-bit synchronous unweighted code counter circuit is reset, it completes the operation of clearing the outputs of the first 4 D flip-flops to zero and setting the outputs of the last 4 D flip-flops to 1, realizing the initialization of the synchronous unweighted code counter circuit. The 3-bit synchronous unweighted code counter circuit includes a decoder circuit that maps 4-bit unweighted code to 3-bit ordinary binary code. The decoder contains multiple logic gate circuits. The logic expression of the output of the decoder circuit is: When the LATCH signal changes from low to high, Q(0)~Q(3) of the decoder circuit is 1111, and the data latched by the latch is also 1111. After decoding by the decoder, the D(0)~D(2) signals are 011. This 3-bit synchronous unweighted code counter realizes the function of a 3-bit binary number counter.

[0006] The present invention provides a synchronous unweighted code counter design and its implementation method, which improves the reliability and stability of the circuit compared with the binary counter, and avoids the problem of latching errors in the local latch caused by the deviation between the actual value and the design value of the delay matching link of the asynchronous Gray code counter in the case of multiple ADCs sharing the counter. It further adapts to the development trend of faster readout speed requirements of large-area image sensors. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of an asynchronous Gray code counter circuit with double-edge triggering in the prior art; Figure 2 This is a schematic diagram of an N-bit synchronous unweighted code counter with reset function provided by the present invention; Figure 3 This is an example diagram of a 3-bit synchronous unweighted code counter with reset function provided by the present invention; Figure 4 This is the decoder circuit used in the examples of this invention; Figure 5 This is a timing diagram of the 3-bit synchronous unweighted code counter in an example of the present invention; The technical solutions and advantages of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0008] Figure 1 The example shown is an existing double-edge triggered asynchronous Gray code counter that is asynchronously driven by a clock signal. As mentioned earlier, there is a delay mismatch problem when the codeword is generated.

[0009] Figure 2 The image shows an N-bit synchronous unweighted code counter with reset function provided by this invention. The entire N-bit synchronous unweighted code counter requires 2... N D flip-flops of the same type (DFF(1)~DFF(2)) N ))constitute.

[0010] Figure 3 It is a circuit with a reset function designed according to the circuit and method disclosed in this invention. This counter can realize the function of a corresponding 3-bit binary counter and complete the counting of eight code words.

[0011] like Figure 3 As shown, the 3-bit synchronous unweighted code counter is composed of 8 D flip-flops (DFF(1)~DFF(8)), and the positive input of the first 4 D flip-flops (DFF(1)~DFF(4)) will output a set of 4-bit codewords Q(0)~Q(3) with Gray code characteristics.

[0012] like Figure 3The diagram shows the specific implementation of a 3-bit synchronous unweighted code counter circuit. The RST input of D flip-flops DFF(1)~DFF(4) is connected to the Reset signal, and the SET input is connected to 0 (low level); the SET input of D flip-flops DFF(5)~DFF(8) is connected to the Reset signal, and the RST input is connected to 0 (low level). With the D flip-flops DFF(1)~DFF(8) connected to the signals as described above, during reset, the first four D flip-flops' outputs can be cleared and the last four D flip-flops' outputs can be set to 1, thus initializing the synchronous unweighted code counter circuit. The counter circuit is connected end-to-end, meaning the output Q of D flip-flop DFF(8) is connected to the input D of D flip-flop DFF(1). The internal D flip-flops are connected so that the output Q of the preceding D flip-flop is connected to the input D of the following D flip-flop, forming a ring shift counter. The Q(0)~Q(3) outputs from the positive inverting inputs of DFF(1)~DFF(4) constitute the number of bits for each unweighted code term.

[0013] In the application scenario of the counter proposed in this patent, in order for the back-end processing unit to directly receive and process data without configuring additional decoding circuits or decoding programs, it is necessary to complete the conversion from unweighted code to binary code in advance before data transmission. Figure 4 This is the decoder circuit structure used in the decoding operation of this invention example. Its function is to map 4-bit unweighted code to 3-bit ordinary binary code. The correspondence is shown in the table below.

[0014] Table 1. Correspondence between 4-bit unweighted code and 3-bit ordinary binary code. Based on the correspondence between unweighted codes and binary codes in the table above, the logic expression for the decoder circuit can be obtained as follows: Based on the logical expression of the decoder circuit above, the decoder circuit can be obtained as follows: Figure 4 As shown, G(0)~G(3) are the signal input terminals of the decoder circuit, and D(0)~D(2) are the output terminals of the decoder circuit.

[0015] like Figure 5The diagram shows the timing sequence of a 3-bit synchronous unweighted code counter with reset function that can perform cyclic counting of eight numbers. CLK is the counter's clock signal, RST is the counter's reset signal, LATCH is the output signal of the ADC comparator, controlling the operation of the latch and decoder, 0 (low level) is the low level required for counter initialization, Q(0)~Q(3) are the positive outputs of the first four D flip-flops, which are the unweighted codes mentioned in this paper, G(0)~G(3) are the output signals of the latch, and D(0)~D(2) are the output signals after passing through the latch. Figure 4 The decoder shown decodes G(0) to G(3) to obtain 3-bit ordinary binary code.

[0016] exist Figure 5 In the example timing diagram, the counter performs eight increment operations within eight clock cycles. When the clock signal is input, the reset signal changes from high to low, and signal 0 remains low, the synchronous unweighted code counter continues to count. When the LATCH signal is low, the latch output signals G(0)~G(3) remain 0, and the decoder output signals D(0)~D(2) also remain 0; when the LATCH signal changes from low to high, the latch output signals G(0)~G(3) change, and the decoder decodes the unweighted code at this moment, obtaining signals D(0)~D(2). Figure 5 When the LATCH signal changes from low to high, Q(0)~Q(3) are 1111, and the data latched by the latch is also 1111. After decoding, the D(0)~D(2) signals are 011, which is consistent with the correspondence between the 4-bit unweighted code and the 3-bit ordinary binary code in Table 1. Therefore, this 3-bit synchronous unweighted code counter can realize the function of a 3-bit binary number counter.

Claims

1. A synchronous unweighted code counter, characterized in that: Gray code possesses the characteristic that only one bit differs between two adjacent values. Its bit correspondence with binary code is 2. (N-1) The unweighted code corresponds to N bits of binary code. The entire N-bit synchronous unweighted code counter requires 2... N It consists of D flip-flops of the same type with set and reset functions, and all D flip-flops are controlled by the same clock signal.

2. The synchronous unweighted code counter according to claim 1, characterized in that: The positive output Q of each D flip-flop between the first and last D flip-flops of the synchronous unweighted code counter circuit is connected to the input D of the next stage D flip-flop, and the positive output Q of the last stage D flip-flop is connected to the input D of the first D flip-flop circuit.

3. The synchronous unweighted code counter according to claim 1, characterized in that: The first two of the synchronous unweighted code counter circuit (N-1) The set input (SET) and the last 2 of the D flip-flops (N-1) The reset terminal (RST) of each D flip-flop is connected to a low level.

4. The synchronous unweighted code counter according to claim 1, characterized in that: The first two of the synchronous unweighted code counter circuit (N-1) The reset terminal (RST) and the last two D flip-flops (N-1) The set (SET) terminals of each D flip-flop are all connected to the Reset signal line.

5. The synchronous unweighted code counter according to claim 1, characterized in that: The first two of the synchronous unweighted code counter circuit (N-1) The positive outputs Q(0)~Q(2) of each D flip-flop (N-1) -1) is the required unweighted key.

6. The synchronous unweighted code counter according to claim 1, characterized in that: The 3-bit synchronous unweighted code counter with N=3 is composed of 8 D flip-flops (DFF(1)~DFF(8)), and the positive input of the first 4 D flip-flops (DFF(1)~DFF(4)) will output a set of 4-bit code words Q(0)~Q(3) with Gray code characteristics. The specific implementation of the 3-bit synchronous unweighted code counter circuit is as follows: the RST input of the D flip-flops DFF(1)~DFF(4) is connected to the Reset signal, and the SET input is connected to 0 (low level); the SET input of the D flip-flops DFF(5)~DFF(8) is connected to the Reset signal, and the RST input is connected to 0 (low level). The D flip-flops DFF(1)~DFF(8) are connected to the signal in the manner described above.

7. The synchronous unweighted code counter according to claim 6, characterized in that: The 3-bit synchronous unweighted code counter circuit is connected end to end. The output terminal Q of the D flip-flop DFF(8) is connected to the input terminal D of the D flip-flop DFF(1). The D flip-flops inside the circuit are connected so that the output Q of the previous stage D flip-flop is connected to the input D of the next stage D flip-flop, forming a ring shift counter. The outputs Q(0) to Q(3) of the positive inverting terminals of DFF(1) to DFF(4) constitute the number of bits of each unweighted code.

8. The synchronous unweighted code counter according to claim 6, characterized in that: When the 3-bit synchronous unweighted counter circuit is reset, it performs the operation of clearing the outputs of the first 4 D flip-flops to zero and setting the outputs of the last 4 D flip-flops to 1, thereby initializing the synchronous unweighted code counter circuit.

9. The synchronous unweighted code counter according to claim 6, characterized in that: The 3-bit synchronous unweighted code counter circuit includes a decoder circuit that maps a 4-bit unweighted code to a 3-bit ordinary binary code. The decoder contains multiple logic gates, and the logic expression at the output of the decoder circuit is as follows: 。 10. The decoder circuit according to claim 9, characterized in that: When the LATCH signal changes from low to high, Q(0)~Q(3) of the decoder circuit is 1111, and the data latched by the latch is also 1111. After decoding by the decoder, the D(0)~D(2) signals are 011. This 3-bit synchronous unweighted code counter realizes the function of a 3-bit binary number counter.

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