Silicon carbide epitaxial wafer and preparation method thereof, and semiconductor device and preparation method thereof

Abstract

The invention discloses a silicon carbide epitaxial wafer, a preparation method of the silicon carbide epitaxial wafer, a semiconductor device and a preparation method of the semiconductor device. The buffer layer is positioned on one side of the carbon surface of the silicon carbide substrate; the buffer layer is formed under a first preset pressure; the drift layer is located on one side, away from the silicon carbide substrate, of the buffer layer; the drift layer is formed under a second preset pressure. According to the invention, the uniformity of the doping concentration of the buffer layer and the drift layer can be effectively improved, and the background doping concentration is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a silicon carbide epitaxial wafer and a preparation method thereof, a semiconductor device and a preparation method thereof. BACKGROUND

[0002] Silicon carbide (SiC) is a typical third-generation semiconductor, which has a wide band gap and high temperature resistance. Silicon carbide-based power devices have been successfully developed and have started the industrialization process in the field of electric vehicles and power grids. For silicon carbide power devices, silicon carbide homoepitaxial layer is the core functional area, which is the key to ensure the reliable and stable performance of silicon carbide devices.

[0003] The existing epitaxial technology for growing epitaxial layers on the carbon surface based on silicon carbide is not mature. The N-doping efficiency of silicon carbide epitaxy on the carbon surface is high, resulting in high background doping concentration and difficulty in controlling the uniformity of the doping concentration. SUMMARY

[0004] The present application provides a silicon carbide epitaxial wafer and a preparation method thereof, a semiconductor device and a preparation method thereof, to solve the problem of high background doping concentration and difficulty in controlling the uniformity of the doping concentration of silicon carbide epitaxy on the carbon surface.

[0005] In a first aspect, the present application provides a silicon carbide epitaxial wafer, wherein the silicon carbide epitaxial wafer comprises:

[0006] a silicon carbide substrate;

[0007] a buffer layer located on the carbon side of the silicon carbide substrate; the buffer layer is formed under a first preset pressure;

[0008] a drift layer located on the side of the buffer layer away from the silicon carbide substrate; the drift layer is formed under a second preset pressure.

[0009] Optionally, the first preset pressure is less than or equal to 80 mbar, and the second preset pressure is less than or equal to 80 mbar.

[0010] In a second aspect, the present application provides a preparation method of a silicon carbide epitaxial wafer, the preparation method comprising:

[0011] providing a silicon carbide substrate;

[0012] forming a buffer layer on the carbon side of the silicon carbide substrate; the buffer layer is formed under a first preset pressure;

[0013] forming a drift layer on the side of the buffer layer away from the silicon carbide substrate; the drift layer is formed under a second preset pressure.

[0014] Optionally, forming a buffer layer on the carbon side of the silicon carbide substrate; the buffer layer is formed under a first preset pressure, comprising:

[0015] epitaxially growing a buffer layer on a carbon face side of the silicon carbide substrate at a pressure less than or equal to 80 mbar;

[0016] forming a drift layer on a side of the buffer layer away from the silicon carbide substrate, the drift layer formed at a second predetermined pressure, comprising:

[0017] epitaxially growing the drift layer on the side of the buffer layer away from the silicon carbide substrate at a pressure less than or equal to 80 mbar.

[0018] Optionally, providing the silicon carbide substrate comprises:

[0019] providing the silicon carbide substrate into the epitaxial reaction chamber;

[0020] forming the buffer layer on the carbon face side of the silicon carbide substrate comprises:

[0021] introducing a carbon source, a silicon source, and a dopant source into the epitaxial reaction chamber to form the buffer layer on the carbon face side of the silicon carbide substrate at a first predetermined pressure;

[0022] forming the drift layer on the side of the buffer layer away from the silicon carbide substrate comprises:

[0023] continuing to introduce the carbon source, the silicon source, and the dopant source into the epitaxial reaction chamber to form the drift layer on the side of the buffer layer away from the silicon carbide substrate at a second predetermined pressure;

[0024] after forming the drift layer on the side of the buffer layer away from the silicon carbide substrate, further comprising:

[0025] turning off the supply of the silicon source and the dopant source, maintaining the supply of the carbon source, and performing an in-situ carbon ambient anneal of the silicon carbide substrate, the buffer layer, and the drift layer.

[0026] Optionally, performing the in-situ carbon ambient anneal of the silicon carbide substrate, the buffer layer, and the drift layer comprises:

[0027] performing the in-situ carbon ambient anneal of the silicon carbide substrate, the buffer layer, and the drift layer at an anneal temperature of 1500 °C to 1750 °C for a time period of 5 min to 120 min.

[0028] Optionally, forming the buffer layer on the carbon face side of the silicon carbide substrate comprises:

[0029] growing the buffer layer on the carbon face side of the silicon carbide substrate using a physical vapor transport process or a high temperature chemical vapor deposition process;

[0030] forming the drift layer on the side of the buffer layer away from the silicon carbide substrate comprises:

[0031] The drift layer is grown on the side of the buffer layer away from the silicon carbide substrate by a physical vapor transport process or a high-temperature chemical vapor deposition process.

[0032] In a third aspect, the present application provides a semiconductor device, wherein the semiconductor device comprises:

[0033] a semiconductor body, the semiconductor body comprising a first surface and a second surface, the semiconductor body further comprising a silicon carbide substrate, a buffer layer, a drift layer, a well region and an emitter region, the silicon carbide substrate being located at the second surface, the buffer layer being located at a side of the silicon carbide substrate away from the second surface and at a side of a carbon face of the silicon carbide substrate, the drift layer being located at a side of the buffer layer away from the second surface, the well region being located at a side of the drift layer away from the second surface, and the emitter region being located at a side of the well region away from the second surface, the buffer layer being formed at a first preset pressure, and the drift layer being formed at a second preset pressure, the semiconductor body further comprising a first insulating layer, the first insulating layer being located at the first surface;

[0034] a first electrode and a second electrode located at the first surface, the second electrode being in contact with the emitter region through the first insulating layer, and the first electrode being in contact with the well region through the first insulating layer or the first electrode being located at a side of the first insulating layer away from the semiconductor body;

[0035] a third electrode located at the second surface.

[0036] In a fourth aspect, the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0037] providing a semiconductor body, the semiconductor body comprising a first surface and a second surface, the semiconductor body further comprising a silicon carbide substrate, a buffer layer, a drift layer, a well region and an emitter region, the silicon carbide substrate being located at the second surface, the buffer layer being located at a side of the silicon carbide substrate away from the second surface and at a side of a carbon face of the silicon carbide substrate, the drift layer being located at a side of the buffer layer away from the second surface, the well region being located at a side of the drift layer away from the second surface, and the emitter region being located at a side of the well region away from the second surface, the buffer layer being formed at a first preset pressure, and the drift layer being formed at a second preset pressure, the semiconductor body further comprising a first insulating layer, the first insulating layer being located at the first surface;

[0038] forming a first electrode and a second electrode at the first surface, the second electrode being in contact with the emitter region through the first insulating layer, and the first electrode being in contact with the well region through the first insulating layer or the first electrode being located at a side of the first insulating layer away from the semiconductor body;

[0039] forming a third electrode at the second surface.

[0040] Optionally, the semiconductor body is provided, comprising:

[0041] the silicon carbide substrate is provided;

[0042] epitaxially growing a buffer layer on a carbon face side of the silicon carbide substrate at a pressure less than or equal to 80 mbar;

[0043] epitaxially growing a drift layer on a side of the buffer layer distal from the silicon carbide substrate at a pressure less than or equal to 80 mbar;

[0044] forming a well region on a side of the drift layer distal from the silicon carbide substrate;

[0045] forming an emitter region on a side of the well region distal from the silicon carbide substrate;

[0046] forming a first insulating layer on a side of the well region and the emitter region distal from the silicon carbide substrate.

[0047] Optionally, providing the silicon carbide substrate comprises:

[0048] providing the silicon carbide substrate into the epitaxial reaction chamber;

[0049] epitaxially growing the buffer layer on a carbon face side of the silicon carbide substrate comprises:

[0050] continuing to supply the carbon source, the silicon source, and the dopant source into the epitaxial reaction chamber to epitaxially grow the drift layer on a side of the buffer layer distal from the silicon carbide substrate;

[0051] epitaxially growing the drift layer on a side of the buffer layer distal from the silicon carbide substrate comprises:

[0052] continuing to supply the carbon source, the silicon source, and the dopant source into the epitaxial reaction chamber to epitaxially grow the drift layer on a side of the buffer layer distal from the silicon carbide substrate;

[0053] prior to forming the well region on a side of the drift layer distal from the silicon carbide substrate, further comprising:

[0054] turning off the supply of the silicon source and the dopant source, maintaining the supply of the carbon source, and performing an in-situ carbon ambient anneal of the silicon carbide substrate, the buffer layer, and the drift layer.

[0055] Optionally, performing the in-situ carbon ambient anneal of the silicon carbide substrate, the buffer layer, and the drift layer comprises:

[0056] performing the in-situ carbon ambient anneal of the silicon carbide substrate, the buffer layer, and the drift layer at an anneal temperature of 1500 °C to 1750 °C for a time of 5 min to 120 min.

[0057] The buffer layer in the silicon carbide epitaxial wafer can be formed by epitaxial growth on one side of the silicon carbide substrate under a first preset pressure, and the drift layer can be formed by epitaxial growth on the side of the buffer layer away from the silicon carbide substrate under a second preset pressure. The first preset pressure and the second preset pressure are low pressures. The buffer layer and the drift layer are grown under a low pressure environment. Silicon source, doping source and carbon source can be provided during the formation of the buffer layer and the drift layer. The silicon source, the doping source and the carbon source can be supplied in the form of gas. The low pressure growth environment is beneficial to improve the average free path of gas molecules, reduce the collision between gas molecules, improve the uniformity and quality of the buffer layer and the drift layer, and effectively improve the uniformity of the doping concentration of the buffer layer and the drift layer and reduce the background doping concentration.

[0058] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0060] Figure 1 is a structural schematic diagram of a silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0061] Figure 2 is a flowchart of a preparation method of a silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0062] Figures 3-4 is a structural schematic diagram corresponding to part of the steps in a preparation method of a silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0063] Figure 5 is a flowchart of another preparation method of a silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0064] Figure 6 is a flowchart of still another preparation method of a silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0065] Figure 7 is a flowchart of still another preparation method of a silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0066] Figure 8 is a temperature-time curve diagram in a preparation process of a silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0067] Figure 9 is another temperature and time curve provided by the embodiment of the present application in the preparation process of the silicon carbide epitaxial wafer;

[0068] Figure 10 is a flow chart of another preparation method of the silicon carbide epitaxial wafer provided by the embodiment of the present application;

[0069] Figure 11 is a structure schematic diagram of a semiconductor device provided by the embodiment of the present application;

[0070] Figure 12 is another structure schematic diagram of a semiconductor device provided by the embodiment of the present application;

[0071] Figure 13 is a flow chart of a preparation method of a semiconductor device provided by the embodiment of the present application;

[0072] Figures 14-16 is a structure schematic diagram corresponding to part of steps in a preparation method of a semiconductor device provided by the embodiment of the present application;

[0073] Figure 17 is a flow chart of another preparation method of a semiconductor device provided by the embodiment of the present application;

[0074] Figures 18-19 is a structure schematic diagram corresponding to part of steps in another preparation method of a semiconductor device provided by the embodiment of the present application;

[0075] Figure 20 is a flow chart of yet another preparation method of a semiconductor device provided by the embodiment of the present application;

[0076] Figure 21 is a flow chart of yet another preparation method of a semiconductor device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0077] In order to make the personnel in the technical field better understand the present application scheme, the technical scheme in the embodiment of the present application will be described clearly and completely in combination with the drawings in the embodiment of the present application. Obviously, the described embodiment is only a part of the embodiment of the present application, but not all. Based on the embodiment in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the present application.

[0078] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting; it is also possible that the use of the same terms in different contexts can carry a different meaning. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0079] Figure 1 is a structural schematic diagram of a silicon carbide epitaxial wafer provided by an embodiment of the present application, as shown in Figure 1 The silicon carbide epitaxial wafer includes a silicon carbide substrate 11, a buffer layer 12 located on the carbon side of the silicon carbide substrate 11, the buffer layer 12 being formed under a first preset pressure. A drift layer 13 located on the side of the buffer layer 12 away from the silicon carbide substrate 11, the drift layer 13 being formed under a second preset pressure.

[0080] Specifically, the silicon carbide epitaxial wafer can include a silicon carbide substrate 11, a buffer layer 12, and a drift layer 13. The buffer layer 12 can include a silicon carbide buffer layer and can be epitaxially grown on one side of the silicon carbide substrate 11 under a first preset pressure. The drift layer 13 can include a silicon carbide drift layer and can be epitaxially grown on the side of the buffer layer 12 away from the silicon carbide substrate 11 under a second preset pressure. The first preset pressure and the second preset pressure are low pressures, and the first preset pressure and the second preset pressure can be the same or different. For example, the first preset pressure can be 5 mbar, 20 mbar, 40 mbar, or 80 mbar, and the second preset pressure can also be 5 mbar, 20 mbar, 40 mbar, or 80 mbar.

[0081] The conductivity type of the silicon carbide substrate 11, the buffer layer 12, and the drift layer 13 can be set arbitrarily to meet the preparation needs of different power devices. The conductivity type of the silicon carbide substrate 11 can include N-type and P-type, and the conductivity type of the buffer layer 12 can also include N-type and P-type. The conductivity type of the drift layer 13 can also include N-type and P-type. For example, the silicon carbide substrate 11 can be an N-type silicon carbide substrate, the buffer layer 12 can be an N-type buffer layer, and the drift layer 13 can also be an N-type drift layer, so as to facilitate the formation of a bipolar transistor (BJT) of an NPN structure later. The silicon carbide substrate 11 can be a P-type silicon carbide substrate, the buffer layer 12 can be an N-type buffer layer, and the drift layer 13 can also be an N-type drift layer, so as to facilitate the formation of an insulated gate bipolar transistor (IGBT) later.

[0082] For example, the forming process of the silicon carbide epitaxial wafer can include: placing the silicon carbide substrate 11 in an epitaxial reaction chamber, performing in-situ etching treatment on the carbon surface of the silicon carbide substrate 11 placed in the epitaxial reaction chamber, and thus eliminating scratches and damages on the carbon surface of the silicon carbide substrate 11. Then, the buffer layer 12 is epitaxially grown on the carbon surface of the silicon carbide substrate 11 under low pressure in the epitaxial reaction chamber, and the drift layer 13 is epitaxially grown on the side of the buffer layer 12 away from the silicon carbide substrate 11 under low pressure in the epitaxial reaction chamber. When the buffer layer 12 and the drift layer 13 are formed, a silicon source, a doping source and a carbon source can be provided into the epitaxial reaction chamber, and the silicon source, the doping source and the carbon source can be supplied in the form of gas. The corresponding doping sources of the buffer layer 12 and the drift layer 13 can be the same or different.

[0083] After the growth of the drift layer 13 is completed, the silicon source and the doping source supplied in the formation of the buffer layer 12 and the drift layer 13 are turned off, the carbon source is maintained to be supplied, the in-situ annealing treatment of the silicon carbide substrate 11, the buffer layer 12 and the drift layer 13 in a carbon-containing atmosphere is performed, the temperature is lowered to room temperature after the annealing is completed, and the silicon carbide epitaxial wafer is taken out. Finally, the prepared silicon carbide carbon surface epitaxial wafer is processed into a power device.

[0084] The buffer layer 12 in the silicon carbide epitaxial wafer can be epitaxially grown on one side of the silicon carbide substrate 11 under a first preset pressure, and the drift layer 13 can be epitaxially grown on the side of the buffer layer 12 away from the silicon carbide substrate 11 under a second preset pressure. The first preset pressure and the second preset pressure are low pressures. The buffer layer 12 and the drift layer 13 are epitaxially grown in a low pressure environment. Silicon source, doping source and carbon source can be provided during the formation of the buffer layer 12 and the drift layer 13, and the silicon source, the doping source and the carbon source can be supplied in the form of gas. The low pressure growth environment is beneficial to improve the average free path of gas molecules, reduce the collision between gas molecules, improve the uniformity and quality of the buffer layer 12 and the drift layer 13, effectively improve the uniformity of the doping concentration of the buffer layer 12 and the drift layer 13, and reduce the background doping concentration.

[0085] Optionally, based on each of the above embodiments, continuing to refer to Figure 1 The first preset pressure is less than or equal to 80 mbar, and the second preset pressure is less than or equal to 80 mbar.

[0086] Specifically, the buffer layer 12 can be epitaxially grown on one side of the silicon carbide substrate 11 under a first preset pressure, and the drift layer 13 can be epitaxially grown on the side of the buffer layer 12 away from the silicon carbide substrate 11 under a second preset pressure. Both the first and second preset pressures can be less than or equal to 80 mbar. During the formation of the buffer layer 12 and the drift layer 13, silicon sources, doping sources, and carbon sources can be provided. The silicon sources, doping sources, and carbon sources can be supplied in the form of gases. The low-pressure growth environment is beneficial to increasing the mean free path of gas molecules, reducing collisions between gas molecules, improving the uniformity and quality of the buffer layer 12 and the drift layer 13, and effectively improving the uniformity of the doping concentration of the buffer layer 12 and the drift layer 13 while reducing the background doping concentration.

[0087] Figure 2 This is a flowchart illustrating a method for preparing a silicon carbide epitaxial wafer according to an embodiment of the present invention. Figures 3-4 This is a schematic diagram of some steps in a method for preparing a silicon carbide epitaxial wafer according to an embodiment of the present invention, as shown below. Figure 2 As shown, the preparation method includes:

[0088] S100: Provides silicon carbide substrate.

[0089] Specifically, such as Figure 3 As shown, a silicon carbide substrate 11 is first provided. The silicon carbide substrate 11 can be placed in an epitaxial reaction chamber, and the carbon surface of the silicon carbide substrate 11 placed in the epitaxial reaction chamber can be etched in situ to eliminate scratches and damage to the carbon surface of the silicon carbide substrate 11. The conductivity type of the silicon carbide substrate 11 can include N-type and P-type to meet the fabrication requirements of different power devices.

[0090] S110: A buffer layer is formed on one side of the carbon surface of the silicon carbide substrate; the buffer layer is formed under a first preset pressure.

[0091] Specifically, such as Figure 4 As shown, within the epitaxial reaction chamber, a buffer layer 12 is epitaxially grown on the carbon surface of a silicon carbide substrate 11 under a first preset pressure, which is a low pressure. For example, the first preset pressure can be less than or equal to 80 mbar. The buffer layer 12 may include a silicon carbide buffer layer, and the conductivity type of the buffer layer 12 may include N-type and P-type. During the formation of the buffer layer 12, a silicon source, a dopant source, and a carbon source can be provided into the epitaxial reaction chamber, and these sources can be supplied in gaseous form.

[0092] S120: A drift layer is formed on the side of the buffer layer away from the silicon carbide substrate; the drift layer is formed under a second preset pressure.

[0093] Specifically, such as Figure 1As shown, the drift layer 13 is epitaxially grown on the side of the buffer layer 12 away from the silicon carbide substrate 11 at a second preset pressure in the epitaxial reaction chamber, and the second preset pressure is a low pressure. For example, the second preset pressure can be less than or equal to 80 mbar. The drift layer 13 can include a silicon carbide drift layer, and the conductivity type of the drift layer 13 can include N-type and P-type. When the drift layer 13 is formed, a silicon source, a doping source, and a carbon source can be provided in the epitaxial reaction chamber, and the silicon source, the doping source, and the carbon source can be supplied in the form of a gas.

[0094] The technical solutions of the embodiments of the present application can form the buffer layer 12 on the side of the silicon carbide substrate 11 at a first preset pressure, and form the drift layer 13 on the side of the buffer layer 12 away from the silicon carbide substrate 11 at a second preset pressure. The first preset pressure and the second preset pressure are low pressures, and the buffer layer 12 and the drift layer 13 are epitaxially grown in a low pressure environment. During the formation of the buffer layer 12 and the drift layer 13, a silicon source, a doping source, and a carbon source can be provided, and the silicon source, the doping source, and the carbon source can be supplied in the form of a gas. The low pressure growth environment is beneficial to improve the average free path of gas molecules, reduce collisions between gas molecules, and improve the uniformity and quality of the buffer layer 12 and the drift layer 13. The uniformity of the doping concentration of the buffer layer 12 and the drift layer 13 can be effectively improved, and the background doping concentration can be reduced.

[0095] Optionally, based on the above-mentioned embodiments, Figure 5 is a flowchart of another method for preparing a silicon carbide epitaxial wafer provided by the embodiments of the present application, as shown in Figure 5 The method comprises the following steps:

[0096] S200: providing a silicon carbide substrate.

[0097] S210: epitaxially growing a buffer layer on the side of the carbon face of the silicon carbide substrate at a pressure less than or equal to 80 mbar.

[0098] Specifically, as shown in Figure 4 The buffer layer 12 is epitaxially grown on the carbon face of the silicon carbide substrate 11 at a pressure less than or equal to 80 mbar in the epitaxial reaction chamber, and during the formation of the buffer layer 12, a silicon source, a doping source, and a carbon source can be provided in the epitaxial reaction chamber, and the silicon source, the doping source, and the carbon source can be supplied in the form of a gas.

[0099] S220: epitaxially growing a drift layer on the side of the buffer layer away from the silicon carbide substrate at a pressure less than or equal to 80 mbar.

[0100] Specifically, in the epitaxial reaction chamber, on the side of the buffer layer 12 away from the silicon carbide substrate 11, a drift layer 13 is epitaxially grown under a pressure of less than or equal to 80 mbar. When the drift layer 13 is formed, a silicon source, a doping source, and a carbon source can be provided to the epitaxial reaction chamber. The silicon source, the doping source, and the carbon source can be supplied in the form of gas.

[0101] The technical solution of this invention provides that a low-pressure growth environment of less than or equal to 80 mbar is beneficial to improving the mean free path of gas molecules, reducing collisions between gas molecules, improving the uniformity and quality of the buffer layer 12 and the drift layer 13, and effectively improving the uniformity of the doping concentration of the buffer layer 12 and the drift layer 13 and reducing the background doping concentration.

[0102] Optionally, based on the above embodiments, Figure 6 This is a flowchart of another method for preparing a silicon carbide epitaxial wafer provided in an embodiment of the present invention, as shown below. Figure 6 As shown, the preparation method includes:

[0103] S300: Provides a silicon carbide substrate to the epitaxial reaction chamber.

[0104] Specifically, such as Figure 3 As shown, a silicon carbide substrate 11 is first provided. The silicon carbide substrate 11 can be placed in an epitaxial reaction chamber, and the carbon surface of the silicon carbide substrate 11 placed in the epitaxial reaction chamber can be etched in situ to eliminate scratches and damage to the carbon surface of the silicon carbide substrate 11. The conductivity type of the silicon carbide substrate 11 can include N-type and P-type to meet the fabrication requirements of different power devices.

[0105] S310: A carbon source, a silicon source, and a doping source are introduced into the epitaxial reaction chamber to form a buffer layer on one side of the carbon surface of the silicon carbide substrate under a first preset pressure.

[0106] Specifically, such as Figure 4 As shown, when forming the buffer layer 12, a silicon source, a doping source, and a carbon source can be provided to the epitaxial reaction chamber. The silicon source, the doping source, and the carbon source can be supplied in the form of gas. In the epitaxial reaction chamber, the buffer layer 12 is epitaxially grown on the carbon surface of the silicon carbide substrate 11 under a first preset pressure.

[0107] S320: Continue to introduce carbon source, silicon source and doping source into the epitaxial reaction chamber to form a drift layer on the side of the buffer layer away from the silicon carbide substrate under a second preset pressure.

[0108] Specifically, such as Figure 1As shown in the formation of the drift layer 13, the silicon source, the doping source and the carbon source can be provided into the epitaxial reaction chamber, which can be supplied in the form of gas, and the drift layer 13 is epitaxially grown on the side of the buffer layer 12 away from the silicon carbide substrate 11 under a second preset pressure in the epitaxial reaction chamber.

[0109] S330: Close the supply of the silicon source and the doping source, maintain the supply of the carbon source, and perform in-situ carbon atmosphere annealing treatment on the silicon carbide substrate, the buffer layer and the drift layer.

[0110] Specifically, as shown in the figure, Figure 1 After the growth of the drift layer 13 is completed, the supply of the silicon source and the doping source is closed, the temperature is increased or decreased to a suitable in-situ annealing temperature, the silicon carbide substrate 11, the buffer layer 12 and the drift layer 13 are subjected to in-situ annealing treatment in a carbon-containing atmosphere, and then the temperature is decreased to room temperature, and the silicon carbide epitaxial wafer is taken out. Finally, the prepared silicon carbide carbon face epitaxial wafer is processed into a power device.

[0111] The minority carrier lifetime is an important parameter of a semiconductor material and a semiconductor device, and directly reflects whether the quality of the material and the characteristics of the device meet the requirements. For a bipolar device mainly relying on minority carrier transport (diffusion is dominant), the on-resistance can be effectively reduced by conductance modulation. In order to achieve effective conductance modulation of the bipolar device, the material is required to have a long enough minority carrier lifetime. During the carbon face homoepitaxy of silicon carbide, carbon vacancy defects are formed, which introduce deep level defects. Such deep level defects will become recombination centers of carriers, causing the minority carrier lifetime of the epitaxial layer to decrease, and the effective conductance modulation cannot be achieved. At present, the minority carrier lifetime of the silicon carbide carbon face epitaxial wafer is still improved by using the commonly used thermal oxidation method, carbon implantation and annealing method, carbon deposition and annealing method, and hydrogen annealing method. These methods are all secondary treatments of the silicon carbide epitaxial wafer after the material growth is completed, which increases the process complexity and is easy to contaminate the material.

[0112] The technical scheme of the embodiment of the present application can effectively reduce the carbon vacancy density in the buffer layer 12 and the drift layer 13 and reduce the recombination centers of minority carriers by performing in-situ annealing treatment on the silicon carbide carbon face epitaxial wafer in a carbon atmosphere. Through the in-situ annealing treatment in the carbon atmosphere, interstitial carbon atoms diffuse in the silicon carbide and meet carbon vacancies to be compensated, thereby reducing the carbon vacancy density, effectively improving the minority carrier lifetime of the carbon face silicon carbide epitaxial wafer, and preparing a high-quality silicon carbide carbon face epitaxial wafer.

[0113] Optionally, based on the above-mentioned embodiments, Figure 7 is a flow chart of another method for preparing a silicon carbide epitaxial wafer provided by the embodiment of the present application, as shown in the figure, Figure 7 the preparation method comprises:

[0114] S400: providing the silicon carbide substrate into an epitaxial reaction chamber.

[0115] S410: introducing a carbon source, a silicon source and a doping source into the epitaxial reaction chamber to form a buffer layer on one side of the carbon face of the silicon carbide substrate at a first preset pressure.

[0116] S420: continuing to introduce the carbon source, the silicon source and the doping source into the epitaxial reaction chamber to form a drift layer on the side of the buffer layer away from the silicon carbide substrate at a second preset pressure.

[0117] S430: performing in-situ carbon atmosphere annealing treatment on the silicon carbide substrate, the buffer layer and the drift layer at an annealing temperature of 1500-1750°C, and the annealing treatment time is 5-120 minutes.

[0118] Specifically, as shown in FIG. 1, after the growth of the drift layer 13 is completed, the supply of the silicon source and the doping source is turned off, and the temperature is increased or decreased to a suitable in-situ annealing temperature, which ranges from 1500°C to 1750°C. The silicon carbide substrate 11, the buffer layer 12 and the drift layer 13 are subjected to in-situ annealing treatment in a carbon-containing atmosphere, and the annealing time can be 5-120 minutes. After the annealing is completed, the temperature is decreased to room temperature, and the silicon carbide epitaxial wafer is taken out. Finally, the prepared silicon carbide carbon face epitaxial wafer is processed into a power device. Figure 1

[0119] -1750°C, the silicon carbide substrate 11, the buffer layer 12 and the drift layer 13 are subjected to in-situ annealing treatment in a carbon-containing atmosphere, and the annealing time can be 5-120 minutes. After the annealing is completed, the temperature is decreased to room temperature, and the silicon carbide epitaxial wafer is taken out. Finally, the prepared silicon carbide carbon face epitaxial wafer is processed into a power device.

[0120] Figure 8 is a temperature-time curve provided by an embodiment of the present application in a process of preparing a silicon carbide epitaxial wafer, Figure 9 is another temperature-time curve provided by an embodiment of the present application in a process of preparing a silicon carbide epitaxial wafer, referring to Figure 1 and Figure 8 In the process of preparing the silicon carbide epitaxial wafer, the silicon carbide substrate 11 is first placed in the epitaxial reaction chamber, and then the temperature in the epitaxial reaction chamber is increased to perform in-situ etching treatment on the carbon face of the silicon carbide substrate 11 placed in the epitaxial reaction chamber. The buffer layer 12 is epitaxially grown on the carbon face of the silicon carbide substrate 11 in the epitaxial reaction chamber at a first preset pressure, and then the temperature in the epitaxial reaction chamber is decreased (Ramping down) to epitaxially grow the drift layer 13 on the side of the buffer layer 12 away from the silicon carbide substrate 11 at a second preset pressure. Then the temperature in the epitaxial reaction chamber is increased (Ramping up) to a suitable in-situ annealing temperature, and only the carbon source is supplied to perform in-situ annealing treatment on the silicon carbide substrate 11, the buffer layer 12 and the drift layer 13 in a carbon-containing atmosphere. After the annealing is completed, the temperature is decreased to room temperature.

[0121] Referring to Figure 1 and Figure 9 ​In the process of preparing a silicon carbide epitaxial wafer, a silicon carbide substrate 11 is first placed in an epitaxial reaction chamber. Then, the temperature in the epitaxial reaction chamber is increased to perform in-situ etching on the carbon surface of the silicon carbide substrate 11. Inside the epitaxial reaction chamber, a buffer layer 12 is epitaxially grown on the carbon surface of the silicon carbide substrate 11 under a first preset pressure. Then, the temperature in the epitaxial reaction chamber is reduced, and a drift layer 13 is epitaxially grown on the side of the buffer layer 12 away from the silicon carbide substrate 11 under a second preset pressure. Then, the temperature in the epitaxial reaction chamber is increased to a suitable in-situ annealing temperature, and only the carbon source supply is maintained. The silicon carbide substrate 11, the buffer layer 12, and the drift layer 13 are subjected to in-situ annealing in a carbon-containing atmosphere. After annealing, the temperature is cooled to room temperature.

[0122] Optionally, based on the above embodiments, Figure 10 This is a flowchart of another method for preparing a silicon carbide epitaxial wafer provided in an embodiment of the present invention, as shown below. Figure 10 As shown, the preparation method includes:

[0123] S500: Provides silicon carbide substrate.

[0124] S510: A buffer layer is grown on one side of the carbon surface of a silicon carbide substrate using physical vapor transport or high-temperature chemical vapor deposition.

[0125] Specifically, such as Figure 4 As shown, a physical vapor transport process or a high-temperature chemical vapor deposition process is used to provide a silicon source, a dopant source, and a carbon source into the epitaxial reaction chamber, so that a buffer layer 12 is epitaxially grown on the carbon surface of the silicon carbide substrate 11 in the epitaxial reaction chamber under a first preset pressure.

[0126] S520: A drift layer is grown on the side of the buffer layer away from the silicon carbide substrate using physical vapor transport or high-temperature chemical vapor deposition.

[0127] Specifically, such as Figure 1 As shown, a silicon source, a doping source, and a carbon source are provided into the epitaxial reaction chamber using a physical vapor transport process or a high-temperature chemical vapor deposition process, so that a drift layer 13 is epitaxially grown in the epitaxial reaction chamber on the side of the buffer layer 12 away from the silicon carbide substrate 11 under a second preset pressure.

[0128] Figure 11 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. Figure 12 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention, such as... Figure 11 and Figure 12As shown, the semiconductor device comprises a semiconductor body 1, the semiconductor body 1 comprises a first surface 101 and a second surface 102, and the semiconductor body 1 further comprises a silicon carbide substrate 11, a buffer layer 12, a drift layer 13, a well region 14 and an emitter region 15. The silicon carbide substrate 11 is located at the second surface 102, the buffer layer 12 is located at a side of the silicon carbide substrate 11 away from the second surface 102 and at a side of a carbon face of the silicon carbide substrate 11, the drift layer 13 is located at a side of the buffer layer 12 away from the second surface 102, the well region 14 is located at a side of the drift layer 13 away from the second surface 102, and the emitter region 15 is located at a side of the well region 14 away from the second surface 102. The buffer layer 12 is formed under a first preset pressure, and the drift layer 13 is formed under a second preset pressure. The semiconductor body 1 further comprises a first insulating layer 16, and the first insulating layer 16 is located at the first surface 101. A first electrode 2 and a second electrode 3 are located at the first surface 101, and the second electrode 3 is in contact with the emitter region 15 through the first insulating layer 16. The first electrode 2 is in contact with the well region 14 through the first insulating layer 16 or the first electrode 2 is located at a side of the first insulating layer 16 away from the semiconductor body 1. A third electrode 4 is located at the second surface 102.

[0129] The semiconductor device of the embodiment of the present application comprises a bipolar junction transistor (BJT) as shown in Figure 11 The semiconductor device of the embodiment of the present application comprises an insulate-gate bipolar transistor (IGBT) as shown in Figure 12 The semiconductor device of the embodiment of the present application comprises an insulate-gate bipolar transistor (IGBT) as shown in

[0130] In some embodiments of the present application, the semiconductor device of the embodiment of the present application can further comprise a planar MOSFET semiconductor device, a single-trench MOSFET semiconductor device and a double-trench MOSFET semiconductor device, and the semiconductor device of the embodiment of the present application can further comprise a Schottky barrier diode (SBD).

[0131] In some embodiments of the present application, the semiconductor device of the embodiment of the present application can further comprise a planar MOSFET semiconductor device, a single-trench MOSFET semiconductor device and a double-trench MOSFET semiconductor device, and the semiconductor device of the embodiment of the present application can further comprise a Schottky barrier diode (SBD). Figure 11In the illustrated BJT semiconductor device, the BJT semiconductor device can include a BJT semiconductor device of NPN structure and a BJT semiconductor device of PNP structure. Taking the BJT semiconductor device of NPN structure as an example, the silicon carbide substrate 11 can be an N-type silicon carbide substrate, the buffer layer 12 can be an N-type buffer layer, the drift layer 13 can be an N-type drift layer, the well region 14 can also be referred to as a base region, the well region 14 can be a P-type well region, and the emitter region 15 can be an N+ emitter region. The first electrode 2 is a base electrode, the first electrode 2 contacts the well region 14 through the first insulating layer 16, the second electrode 3 is an emitter electrode, the second electrode 3 contacts the emitter region 15 through the first insulating layer 16, and the third electrode 4 is a collector electrode, the third electrode 4 is located on the second surface 102.

[0132] In Figure 12 In the illustrated IGBT semiconductor device, the IGBT semiconductor device can include an N-type IGBT semiconductor device and a P-type IGBT semiconductor device. Taking the N-type IGBT semiconductor device as an example, the silicon carbide substrate 11 can be a P-type silicon carbide substrate, the buffer layer 12 can be an N-type buffer layer, the drift layer 13 can be an N-type drift layer, the well region 14 can be a P-type well region, and the emitter region 15 can be an N+ emitter region. The first electrode 2 is a gate electrode, the first electrode 2 is located on the side of the first insulating layer 16 away from the semiconductor body 1, and does not contact the well region 14, the second electrode 3 is an emitter electrode, the second electrode 3 contacts the emitter region 15 through the first insulating layer 16, and the third electrode 4 is a collector electrode, the third electrode 4 is located on the second surface 102.

[0133] For the BJT semiconductor device and the IGBT semiconductor device, the silicon carbide substrate 11, the buffer layer 12, and the drift layer 13 in the semiconductor body 1 constitute the silicon carbide epitaxial wafer provided by any of the above embodiments of the application. The buffer layer 12 can include a silicon carbide buffer layer, and the buffer layer 12 can be formed by epitaxial growth on one side of the silicon carbide substrate 11 under a first preset pressure. The drift layer 13 can include a silicon carbide drift layer, and the drift layer 13 can be formed by epitaxial growth on the side of the buffer layer 12 away from the silicon carbide substrate 11 under a second preset pressure. The first preset pressure and the second preset pressure are low pressures, and the first preset pressure and the second preset pressure can be the same or different. For example, the first preset pressure can be 5 mbar, 20 mbar, 40 mbar, or 80 mbar, and the second preset pressure can also be 5 mbar, 20 mbar, 40 mbar, or 80 mbar.

[0134] For example, the forming process of the silicon carbide epitaxial wafer in the semiconductor body 1 can include: placing the silicon carbide substrate 11 in an epitaxial reaction chamber, performing in-situ etching treatment on the carbon surface of the silicon carbide substrate 11 placed in the epitaxial reaction chamber, and thus eliminating scratches and damage on the carbon surface of the silicon carbide substrate 11. Then, under low pressure, the buffer layer 12 is epitaxially grown on the carbon surface of the silicon carbide substrate 11 in the epitaxial reaction chamber, and under low pressure, the drift layer 13 is epitaxially grown on the side of the buffer layer 12 away from the silicon carbide substrate 11 in the epitaxial reaction chamber. When forming the buffer layer 12 and the drift layer 13, a silicon source, a doping source and a carbon source can be provided in the epitaxial reaction chamber, and the silicon source, the doping source and the carbon source can be supplied in the form of a gas.

[0135] After the growth of the drift layer 13 is completed, the silicon source and the doping source supplied during the formation of the buffer layer 12 and the drift layer 13 are turned off, the carbon source is maintained, the silicon carbide substrate 11, the buffer layer 12 and the drift layer 13 are subjected to in-situ annealing treatment in a carbon-containing atmosphere, and after the annealing is completed, the temperature is lowered to room temperature, and the silicon carbide epitaxial wafer is taken out. Finally, the prepared silicon carbide carbon surface epitaxial wafer is processed into a power device.

[0136] The technical solution of the embodiment of the present application is that for a BJT semiconductor device and an IGBT semiconductor device, the buffer layer 12 in the semiconductor body 1 can be epitaxially grown on one side of the silicon carbide substrate 11 under a first preset pressure, and the drift layer 13 can be epitaxially grown on the side of the buffer layer 12 away from the silicon carbide substrate 11 under a second preset pressure. The first preset pressure and the second preset pressure are low pressures, and the buffer layer 12 and the drift layer 13 are epitaxially grown in a low pressure environment. Silicon source, doping source and carbon source can be provided during the formation of the buffer layer 12 and the drift layer 13, and the silicon source, the doping source and the carbon source can be supplied in the form of a gas. The low pressure growth environment is beneficial to improve the average free path of gas molecules, reduce the collision between gas molecules, improve the uniformity and quality of the buffer layer 12 and the drift layer 13, and effectively improve the uniformity of the doping concentration of the buffer layer 12 and the drift layer 13 and reduce the background doping concentration.

[0137] Figure 13 is a flowchart of a semiconductor device preparation method provided by an embodiment of the present application, Figures 14-16 is a structure schematic diagram corresponding to part of the steps in the semiconductor device preparation method provided by an embodiment of the present application, as Figure 13 shown, the preparation method includes:

[0138] S600: Provides a semiconductor body; the semiconductor body includes a first surface and a second surface, and the semiconductor body also includes a silicon carbide substrate, a buffer layer, a drift layer, a well region and an emitter region; the silicon carbide substrate is located on the second surface, the buffer layer is located on the side of the silicon carbide substrate away from the second surface and on the side of the carbon surface of the silicon carbide substrate, the drift layer is located on the side of the buffer layer away from the second surface, the well region is located on the side of the drift layer away from the second surface, and the emitter region is located on the side of the well region away from the second surface; the buffer layer is formed under a first preset pressure, and the drift layer is formed under a second preset pressure; the semiconductor body also includes a first insulating layer, which is located on the first surface.

[0139] Specifically, such as Figure 14 As shown, taking an NPN-structured BJT semiconductor device as an example, the silicon carbide substrate 11 can be an N-type silicon carbide substrate, the buffer layer 12 can be an N-type buffer layer, the drift layer 13 can be an N-type drift layer, the well region 14 can also be called the base region, the well region 14 can be a P-type well region, and the emitter region 15 can be an N+ emitter region.

[0140] Taking an N-type IGBT semiconductor device as an example, the silicon carbide substrate 11 can be a P-type silicon carbide substrate, the buffer layer 12 can be an N-type buffer layer, the drift layer 13 can be an N-type drift layer, the well region 14 can be a P-type well region, and the emitter region 15 can be an N+ emitter region.

[0141] For BJT and IGBT semiconductor devices, the silicon carbide substrate 11, buffer layer 12, and drift layer 13 in the semiconductor body 1 constitute the silicon carbide epitaxial wafer provided in any of the above embodiments of the present invention. The buffer layer 12 may include a silicon carbide buffer layer, which can be epitaxially grown on one side of the silicon carbide substrate 11 under a first preset pressure. The drift layer 13 may include a silicon carbide drift layer, which can be epitaxially grown on the side of the buffer layer 12 away from the silicon carbide substrate 11 under a second preset pressure. The first and second preset pressures are low pressures; for example, the first preset pressure can be 5 mbar, 20 mbar, 40 mbar, or 80 mbar, and the second preset pressure can be 5 mbar, 20 mbar, 40 mbar, or 80 mbar.

[0142] For example, the formation process of the silicon carbide epitaxial wafer in the semiconductor body 1 may include: placing a silicon carbide substrate 11 in an epitaxial reaction chamber, and performing in-situ etching on the carbon surface of the silicon carbide substrate 11 placed in the epitaxial reaction chamber to eliminate scratches and damage on the carbon surface of the silicon carbide substrate 11. Then, within the epitaxial reaction chamber, a buffer layer 12 is epitaxially grown under low pressure on the carbon surface of the silicon carbide substrate 11, and a drift layer 13 is epitaxially grown under low pressure on the side of the buffer layer 12 away from the silicon carbide substrate 11 within the epitaxial reaction chamber. During the formation of the buffer layer 12 and the drift layer 13, a silicon source, a dopant source, and a carbon source may be provided to the epitaxial reaction chamber, and the silicon source, dopant source, and carbon source may be supplied in the form of gas.

[0143] After the drift layer 13 is grown, the silicon source and doping source supplied to form the buffer layer 12 and drift layer 13 are turned off, while the carbon source supply is maintained. The silicon carbide substrate 11, buffer layer 12 and drift layer 13 are subjected to in-situ annealing in a carbon atmosphere. After annealing, the temperature is lowered to room temperature, and the silicon carbide epitaxial wafer is taken out. Finally, the prepared silicon carbide carbon surface epitaxial wafer is processed into a high-yield device.

[0144] S610: A first electrode and a second electrode are formed on the first surface, the second electrode passes through the first insulating layer and contacts the emitter region; the first electrode passes through the first insulating layer and contacts the well region, or the first electrode is located on the side of the first insulating layer away from the semiconductor body.

[0145] Specifically, such as Figure 15 As shown, for a BJT semiconductor device, the first electrode 2 is the base electrode, which passes through the first insulating layer 16 and contacts the well region 14. The second electrode 3 is the emitter electrode, which passes through the first insulating layer 16 and contacts the emitter region 15.

[0146] like Figure 16 As shown, for an IGBT semiconductor device, the first electrode 2 is the gate, located on the side of the first insulating layer 16 away from the semiconductor body 1, and does not contact the well region 14. The second electrode 3 is the emitter, passing through the first insulating layer 16 and contacting the emitter region 15.

[0147] S620: A third electrode is formed on the second surface.

[0148] Specifically, such as Figure 11 and Figure 12 As shown, for BJT semiconductor devices and IGBT semiconductor devices, the third electrode 4 is the collector electrode, and the third electrode 4 is located on the second surface 102.

[0149] The technical scheme of the embodiment of the present application is for the BJT semiconductor device and the IGBT semiconductor device, and the buffer layer 12 and the drift layer 13 are grown in a low-pressure environment, and silicon source, doping source and carbon source can be provided in the forming process of the buffer layer 12 and the drift layer 13, the silicon source, the doping source and the carbon source can be supplied in the form of gas, and the low-pressure growth environment is beneficial to improve the average free path of gas molecules, reduce the collision between gas molecules, improve the uniformity and quality of the buffer layer 12 and the drift layer 13, and effectively improve the uniformity of the doping concentration of the buffer layer 12 and the drift layer 13 and reduce the background doping concentration.

[0150] Optionally, based on each of the above embodiments, Figure 17 is a flowchart of another semiconductor device preparation method provided by the embodiment of the present application, Figures 18-19 is a structure schematic diagram corresponding to part of steps in another semiconductor device preparation method provided by the embodiment of the present application, as shown in the figure, Figure 17 The preparation method comprises the following steps:

[0151] S700: providing a silicon carbide substrate.

[0152] Specifically, as shown in the figure, Figure 3 First, the silicon carbide substrate 11 is provided, and the carbon face of the silicon carbide substrate 11 placed in the epitaxial reaction chamber can be in-situ etched to eliminate scratches and damage on the carbon face of the silicon carbide substrate 11.

[0153] S710: epitaxially growing a buffer layer on one side of the carbon face of the silicon carbide substrate under a pressure less than or equal to 1-80 mbar.

[0154] Specifically, as shown in the figure, Figure 4 The buffer layer 12 is epitaxially grown on the carbon face of the silicon carbide substrate 11 in the epitaxial reaction chamber under a first preset pressure, and the first preset pressure is a low pressure. For example, the first preset pressure can be less than or equal to 80 mbar. The buffer layer 12 can include a silicon carbide buffer layer, and silicon source, doping source and carbon source can be provided in the epitaxial reaction chamber when the buffer layer 12 is formed, and the silicon source, the doping source and the carbon source can be supplied in the form of gas.

[0155] S720: epitaxially growing a drift layer on the side of the buffer layer away from the silicon carbide substrate under a pressure less than or equal to 80 mbar.

[0156] Specifically, as shown in the figure, Figure 1As shown, within the epitaxial reaction chamber, on the side of the buffer layer 12 away from the silicon carbide substrate 11, a drift layer 13 is epitaxially grown under a second preset pressure, which is a low pressure. For example, the second preset pressure can be less than or equal to 80 mbar. The drift layer 13 may include a silicon carbide drift layer. During the formation of the drift layer 13, a silicon source, a dopant source, and a carbon source can be provided into the epitaxial reaction chamber. The silicon source, dopant source, and carbon source can be supplied in gaseous form.

[0157] S730: A trap region is formed on the side of the drift layer away from the silicon carbide substrate.

[0158] Specifically, such as Figure 18 As shown, a well region 14 is formed on the side of the drift layer 13 away from the silicon carbide substrate 11. The well region 14 can be prepared by doping the drift region 13.

[0159] S740: An emitter region is formed on the side of the well region away from the silicon carbide substrate.

[0160] Specifically, such as Figure 19 As shown, an emitter region 15 is formed on the side of the well region 14 away from the silicon carbide substrate 11. The emitter region 15 can be prepared by doping the well region 14.

[0161] S750: A first insulating layer is formed on the side of the well region and emitter region away from the silicon carbide substrate.

[0162] Specifically, such as Figure 14 As shown, a first insulating layer 16 is formed on the side of the well region 14 and the emitter region 15 away from the silicon carbide substrate 11. For example, the first insulating layer 16 may include a silicon dioxide insulating layer.

[0163] S760: A first electrode and a second electrode are formed on the first surface, the second electrode passing through the first insulating layer and contacting the emitter region; the first electrode passing through the first insulating layer and contacting the well region, or the first electrode being located on the side of the first insulating layer away from the semiconductor body.

[0164] S770: A third electrode is formed on the second surface.

[0165] Optionally, based on the above embodiments, Figure 20 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention, such as... Figure 20 As shown, the preparation method includes:

[0166] S800: Provides a silicon carbide substrate to the epitaxial reaction chamber.

[0167] Specifically, such as Figure 3As shown, first, the silicon carbide substrate 11 is provided, and the silicon carbide substrate 11 can be placed in the epitaxial reaction chamber first, and the carbon surface of the silicon carbide substrate 11 placed in the epitaxial reaction chamber is subjected to in-situ etching treatment, so as to eliminate scratches and damage of the carbon surface of the silicon carbide substrate 11.

[0168] S810: The carbon source, the silicon source and the doping source are introduced into the epitaxial reaction chamber under a pressure less than or equal to 80 mbar to epitaxially grow a buffer layer on one side of the carbon surface of the silicon carbide substrate.

[0169] Specifically, as shown in the figure, Figure 4 When the buffer layer 12 is formed, the silicon source, the doping source and the carbon source can be provided into the epitaxial reaction chamber, and the silicon source, the doping source and the carbon source can be supplied in the form of gas, and the buffer layer 12 is epitaxially grown on the carbon surface of the silicon carbide substrate 11 in the epitaxial reaction chamber under a first preset pressure.

[0170] S820: The carbon source, the silicon source and the doping source are continuously introduced into the epitaxial reaction chamber under a pressure less than or equal to 80 mbar to epitaxially grow a drift layer on a side of the buffer layer away from the silicon carbide substrate.

[0171] Specifically, as shown in the figure, Figure 1 When the drift layer 13 is formed, the silicon source, the doping source and the carbon source can be provided into the epitaxial reaction chamber, and the silicon source, the doping source and the carbon source can be supplied in the form of gas, and the drift layer 13 is epitaxially grown on a side of the buffer layer 12 away from the silicon carbide substrate 11 in the epitaxial reaction chamber under a second preset pressure.

[0172] S830: The supply of the silicon source and the doping source is stopped, the supply of the carbon source is maintained, and the silicon carbide substrate, the buffer layer and the drift layer are subjected to in-situ annealing treatment in a carbon atmosphere.

[0173] Specifically, as shown in the figure, Figure 1 After the growth of the drift layer 13 is completed, the supply of the silicon source and the doping source is stopped, the temperature is increased or decreased to a suitable in-situ annealing temperature, the silicon carbide substrate 11, the buffer layer 12 and the drift layer 13 are subjected to in-situ annealing treatment in a carbon-containing atmosphere, the temperature is decreased to room temperature after the annealing is completed, and the silicon carbide epitaxial wafer is taken out, and finally, the prepared silicon carbide carbon surface epitaxial wafer is processed into a power device.

[0174] The technical scheme of the embodiment of the present application can effectively reduce the carbon vacancy density in the buffer layer 12 and the drift layer 13 and reduce the recombination center of the minority carriers by performing in-situ annealing treatment on the silicon carbide carbon surface epitaxial wafer in a carbon atmosphere. Through the in-situ annealing treatment in the carbon atmosphere, the interstitial atomic carbon diffuses in the silicon carbide and meets the carbon vacancies to be compensated, the carbon vacancy density is reduced, and the minority carrier lifetime of the carbon surface silicon carbide epitaxial wafer is effectively improved, and a high-quality silicon carbide carbon surface epitaxial wafer is prepared.

[0175] S840: A trap region is formed on the side of the drift layer away from the silicon carbide substrate.

[0176] S850: An emitter region is formed on the side of the well region away from the silicon carbide substrate.

[0177] S860: A first insulating layer is formed on the side of the well region and emitter region away from the silicon carbide substrate.

[0178] S870: A first electrode and a second electrode are formed on the first surface, the second electrode passes through the first insulating layer and contacts the emitter region; the first electrode passes through the first insulating layer and contacts the well region, or the first electrode is located on the side of the first insulating layer away from the semiconductor body.

[0179] S880: A third electrode is formed on the second surface.

[0180] Optionally, based on the above embodiments, Figure 21 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention, such as... Figure 21 As shown, the preparation method includes:

[0181] S900: Provides silicon carbide substrate to the epitaxial reaction chamber.

[0182] S910: Under a pressure of less than or equal to 80 mbar, a carbon source, a silicon source, and a dopant source are introduced into the epitaxial reaction chamber to epitaxially grow a buffer layer on one side of the carbon surface of a silicon carbide substrate.

[0183] S920: Under a pressure of less than or equal to 80 mbar, carbon source, silicon source and dopant source are continuously introduced into the epitaxial reaction chamber to epitaxially grow a drift layer on the side of the buffer layer away from the silicon carbide substrate.

[0184] S930: Turn off the supply of silicon source and doping source, maintain the supply of carbon source, and perform in-situ carbon atmosphere annealing on silicon carbide substrate, buffer layer and drift layer at annealing temperature of 1500℃-1750℃ for 5min-120min.

[0185] Specifically, such as Figure 1 As shown, after the growth of drift layer 13 is completed, the supply of silicon source and doping source is turned off, and the temperature is increased or decreased to a suitable in-situ annealing temperature. The in-situ annealing temperature range is 1500℃-1750℃. The silicon carbide substrate 11, buffer layer 12 and drift layer 13 are subjected to in-situ annealing treatment in a carbon-containing atmosphere. The annealing time can be 5min-120min. After annealing, the temperature is cooled to room temperature, and the silicon carbide epitaxial wafer is removed. Finally, the prepared silicon carbide carbon-surface epitaxial wafer is processed into a high-yield device.

[0186] S940: A trap region is formed on the side of the drift layer away from the silicon carbide substrate.

[0187] S950: Forming an emission region on the side of the well region away from the silicon carbide substrate.

[0188] S960: Forming a first insulating layer on the side of the well region and the emission region away from the silicon carbide substrate.

[0189] S970: Forming a first electrode and a second electrode on the first surface, the second electrode being in contact with the emission region through the first insulating layer; the first electrode being in contact with the well region through the first insulating layer or the first electrode being on the side of the first insulating layer away from the semiconductor body.

[0190] S980: Forming a third electrode on the second surface.

[0191] The embodiment of the present application provides a power module, wherein the power module comprises a substrate and at least one semiconductor device provided by any one of the above-mentioned embodiments of the present application, and the substrate is used for carrying the at least one semiconductor device provided by any one of the above-mentioned embodiments of the present application.

[0192] The power module provided by any one of the above-mentioned embodiments of the present application comprises the semiconductor device provided by any one of the above-mentioned embodiments of the present application, and has the beneficial effects of the semiconductor device provided by any one of the above-mentioned embodiments of the present application.

[0193] The embodiment of the present application provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion and power factor correction.

[0194] The power conversion circuit comprises a circuit board and at least one semiconductor device provided by any one of the above-mentioned embodiments of the present application, and the semiconductor device is electrically connected with the circuit board.

[0195] The power conversion circuit provided by any one of the above-mentioned embodiments of the present application comprises the semiconductor device provided by any one of the above-mentioned embodiments of the present application, and has the beneficial effects of the semiconductor device provided by any one of the above-mentioned embodiments of the present application.

[0196] The embodiment of the present application provides a vehicle, wherein the vehicle comprises a load and a power conversion circuit provided by any one of the above-mentioned embodiments of the present application, and the power conversion circuit is used for converting alternating current into direct current, converting alternating current into alternating current, converting direct current into direct current or converting direct current into alternating current and then inputting to the load.

[0197] The vehicle provided by any one of the above-mentioned embodiments of the present application comprises the power conversion circuit provided by any one of the above-mentioned embodiments of the present application, and the power conversion circuit provided by any one of the above-mentioned embodiments of the present application comprises the semiconductor device provided by any one of the above-mentioned embodiments of the present application, so the vehicle provided by any one of the above-mentioned embodiments of the present application has the beneficial effects of the semiconductor device provided by any one of the above-mentioned embodiments of the present application.

[0198] It should be understood that the various forms of flow shown above can be used to reorder, add, or remove steps. For example, the steps recited in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0199] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A silicon carbide epitaxial wafer, characterized in that, include: silicon carbide substrate; A buffer layer located on the carbon side of the silicon carbide substrate; The buffer layer is formed under a first preset pressure; A drift layer located on the side of the buffer layer away from the silicon carbide substrate; the drift layer is formed under a second preset pressure.

2. The silicon carbide epitaxial wafer according to claim 1, characterized in that, The first preset pressure is less than or equal to 80 mbar, and the second preset pressure is less than or equal to 80 mbar.

3. A method for preparing a silicon carbide epitaxial wafer, characterized in that, include: Provide silicon carbide substrates; A buffer layer is formed on one side of the carbon surface of the silicon carbide substrate; The buffer layer is formed under a first preset pressure; A drift layer is formed on the side of the buffer layer away from the silicon carbide substrate; the drift layer is formed under a second preset pressure.

4. The method for preparing a silicon carbide epitaxial wafer according to claim 3, characterized in that, A buffer layer is formed on one side of the carbon surface of the silicon carbide substrate; The buffer layer is formed under a first preset pressure and includes: The buffer layer is epitaxially grown on one side of the carbon surface of the silicon carbide substrate under a pressure of less than or equal to 80 mbar. A drift layer is formed on the side of the buffer layer away from the silicon carbide substrate; the drift layer is formed under a second preset pressure and includes: The drift layer is epitaxially grown on the side of the buffer layer away from the silicon carbide substrate under a pressure of less than or equal to 80 mbar.

5. The method for preparing a silicon carbide epitaxial wafer according to claim 3, characterized in that, The silicon carbide substrates provided include: The silicon carbide substrate is provided into the epitaxial reaction chamber; Forming a buffer layer on one side of the carbon surface of the silicon carbide substrate includes: A carbon source, a silicon source, and a doping source are introduced into the epitaxial reaction chamber to form a buffer layer on one side of the carbon surface of the silicon carbide substrate under a first preset pressure. Forming a drift layer on the side of the buffer layer away from the silicon carbide substrate includes: A carbon source, a silicon source, and a doping source are continuously introduced into the epitaxial reaction chamber to form a drift layer on the side of the buffer layer away from the silicon carbide substrate under a second preset pressure. After forming a drift layer on the side of the buffer layer away from the silicon carbide substrate, the method further includes: The silicon source and doping source are shut off, while the carbon source is maintained. The silicon carbide substrate, the buffer layer, and the drift layer are then subjected to in-situ carbon atmosphere annealing.

6. The method for preparing a silicon carbide epitaxial wafer according to claim 5, characterized in that, The silicon carbide substrate, the buffer layer, and the drift layer undergo in-situ carbon atmosphere annealing, including: The silicon carbide substrate, the buffer layer, and the drift layer are subjected to in-situ carbon atmosphere annealing at an annealing temperature of 1500℃-1750℃ for a duration of 5 min-120 min.

7. The method for preparing a silicon carbide epitaxial wafer according to claim 3, characterized in that, A buffer layer is formed on one side of the carbon surface of the silicon carbide substrate, comprising: The buffer layer is grown on one side of the carbon surface of the silicon carbide substrate using a physical vapor transport process or a high-temperature chemical vapor deposition process. A drift layer is formed on the side of the buffer layer away from the silicon carbide substrate, comprising: The drift layer is grown on the side of the buffer layer away from the silicon carbide substrate using a physical vapor transport process or a high-temperature chemical vapor deposition process.

8. A semiconductor device, characterized in that, include: The semiconductor body includes a first surface and a second surface, and further includes a silicon carbide substrate, a buffer layer, a drift layer, a well region, and an emitter region. The silicon carbide substrate is located on the second surface; the buffer layer is located on the side of the silicon carbide substrate away from the second surface and on one side of the carbon surface of the silicon carbide substrate; the drift layer is located on the side of the buffer layer away from the second surface; the well region is located on the side of the drift layer away from the second surface; and the emitter region is located on the side of the well region away from the second surface. The buffer layer is formed under a first preset pressure, and the drift layer is formed under a second preset pressure. The semiconductor body further includes a first insulating layer located on the first surface. A first electrode and a second electrode are located on the first surface, with the second electrode passing through the first insulating layer and contacting the emission region; The first electrode passes through the first insulating layer and contacts the well region, or the first electrode is located on the side of the first insulating layer away from the semiconductor body; The third electrode is located on the second surface.

9. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor body is provided; the semiconductor body includes a first surface and a second surface, and further includes a silicon carbide substrate, a buffer layer, a drift layer, a well region, and an emitter region; the silicon carbide substrate is located on the second surface, the buffer layer is located on the side of the silicon carbide substrate away from the second surface and on one side of the carbon surface of the silicon carbide substrate, the drift layer is located on the side of the buffer layer away from the second surface, the well region is located on the side of the drift layer away from the second surface, and the emitter region is located on the side of the well region away from the second surface; the buffer layer is formed under a first preset pressure, and the drift layer is formed under a second preset pressure; the semiconductor body further includes a first insulating layer, which is located on the first surface; A first electrode and a second electrode are formed on the first surface, and the second electrode passes through the first insulating layer and contacts the emission region. The first electrode passes through the first insulating layer and contacts the well region, or the first electrode is located on the side of the first insulating layer away from the semiconductor body; A third electrode is formed on the second surface.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, Provide semiconductor bodies, including: Provide silicon carbide substrates; The buffer layer is epitaxially grown on one side of the carbon surface of the silicon carbide substrate under a pressure of less than or equal to 80 mbar. The drift layer is epitaxially grown on the side of the buffer layer away from the silicon carbide substrate under a pressure of less than or equal to 80 mbar. A well region is formed on the side of the drift layer away from the silicon carbide substrate; An emission region is formed on the side of the well region away from the silicon carbide substrate; A first insulating layer is formed on the side of the trap region and the emitter region away from the silicon carbide substrate.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The silicon carbide substrates provided include: The silicon carbide substrate is provided into the epitaxial reaction chamber; An epitaxial buffer layer is grown on one side of the carbon plane of the silicon carbide substrate, comprising: A carbon source, a silicon source, and a doping source are introduced into the epitaxial reaction chamber to epitaxially grow a buffer layer on one side of the carbon surface of the silicon carbide substrate. An epitaxial drift layer is grown on the side of the buffer layer away from the silicon carbide substrate, comprising: A carbon source, a silicon source, and a doping source are continuously introduced into the epitaxial reaction chamber to epitaxially grow a drift layer on the side of the buffer layer away from the silicon carbide substrate; Before forming a well region on the side of the drift layer away from the silicon carbide substrate, the method further includes: The silicon source and doping source are shut off, while the carbon source is maintained. The silicon carbide substrate, the buffer layer, and the drift layer are then subjected to in-situ carbon atmosphere annealing.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The silicon carbide substrate, the buffer layer, and the drift layer undergo in-situ carbon atmosphere annealing, including: The silicon carbide substrate, the buffer layer, and the drift layer are subjected to in-situ carbon atmosphere annealing at an annealing temperature of 1500℃-1750℃ for a duration of 5 min-120 min.

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