Radio frequency switch circuit and forming method
By increasing the air gap between the first two MOSFETs in the RF switching circuit, the problem of uneven bias voltage was solved, the bias voltage uniformity of the MOSFETs was improved, and the performance and stability of the RF switching circuit were enhanced.
Patent Information
- Application Number
- CN202511065464.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2025-11-18
AI Technical Summary
In RF switching circuits, uneven bias voltages in the first two stages of MOSFETs can lead to breakdown and affect circuit performance.
In RF switching circuits, bias uniformity is increased by forming a large air gap in the first two stages of MOSFETs. Dry and wet etching techniques are used to expand the size of the air gap, forming the first and second air gaps to reduce bias non-uniformity.
It improves the bias uniformity of MOSFETs, enhances the performance of RF switching circuits, avoids MOSFET breakdown, and improves the stability and reliability of the circuit.
Smart Images
Figure CN120980952A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a radio frequency switch circuit and its fabrication method. Background Technology
[0002] In radio frequency (RF) front-end circuits, RF switches are essential components. RF switches are used to electrically connect antennas to the transmit or receive paths of an RF system, allowing multiple components to be connected to the antenna. Typically, RF switches are configured using a stack of multiple transistors (such as field-effect transistors (FETs)). When an RF switch is in the OFF state, it can be considered as acting as a shunt "high" impedance about ground. Such an OFF stacked RF switch generally presents both capacitance and impedance. With the development of mobile communication technology, multiple communication standards coexist. Therefore, it is necessary to integrate RF power amplifiers of multiple modes and different frequency bands, and to select the required RF power amplifier through RF switch circuits to establish RF signal reception and transmission channels, enabling switching between different communication networks.
[0003] However, when the RF switch is off, it was found that the bias voltage (Vds) of the two MOSFETs in the stack is high, significantly higher than the bias voltage (Vds) of the remaining MOSFETs in the subsequent stages, resulting in uneven bias voltages across all MOSFETs. Consequently, when the voltage is increased in the RF switch circuit, several MOSFETs in the preceding stages may break down. Summary of the Invention
[0004] The purpose of this invention is to provide a radio frequency switch circuit and its formation method, which can reduce the bias voltage of the first two MOS transistors in the stack and improve the uniformity of the bias voltage of all MOS transistors in the stack, thereby improving the performance of the radio frequency switch circuit.
[0005] To achieve the above objectives, the present invention provides a method for forming a radio frequency switch circuit, comprising:
[0006] An SOI is provided, the SOI comprising a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially.
[0007] Multiple spaced MOS gate structures are formed on the surface of the top silicon layer. Each MOS gate structure includes a gate located on the surface of the top silicon layer, and a source terminal and a drain terminal located on both sides of the gate in the top silicon layer.
[0008] A first interlayer dielectric layer is formed on the surface of the MOS gate structure;
[0009] A first metal line and a second metal line are formed at intervals on the surface of the interlayer dielectric layer, with a portion of the surface of the first interlayer dielectric layer exposed between the first metal line and the second metal line. The first metal line is electrically connected to the source terminal, and the second metal line is electrically connected to the drain terminal.
[0010] A first nitride layer, a second interlayer dielectric layer, and a second nitride layer are sequentially formed on the surfaces of the first metal line, the second metal line, and the first interlayer dielectric layer. The second nitride layer fills the gap formed by the first metal line and the second metal line. A first air gap is formed inside the second interlayer dielectric layer located between the first metal line and the second metal line.
[0011] The gate structures of the first two MOS transistors starting from the signal input terminal are selected, and a portion of the first nitride layer and a portion of the second interlayer dielectric layer between the first metal line and the second metal line are etched to expose the opening of the first air gap.
[0012] The remaining second dielectric layer located between the first and second metal lines is etched to increase the size of the first air gap;
[0013] A third interlayer dielectric layer is formed on the surface of the second interlayer dielectric layer, and the third interlayer dielectric layer forms a second air gap above the first air gap.
[0014] Optionally, in the method of forming the radio frequency switch circuit, a portion of the first nitride layer and a portion of the second interlayer dielectric layer between the first metal line and the second metal line are dry etched to expose the opening of the first air gap.
[0015] Optionally, in the method of forming the radio frequency switch circuit, the remaining second dielectric layer located between the first metal line and the second metal line is wet-etched to increase the size of the first air gap.
[0016] Optionally, in the method for forming the radio frequency switch circuit, the MOS transistor gate structure further includes sidewalls located on both sides of the gate.
[0017] Optionally, in the method for forming the radio frequency switch circuit, the top silicon layer includes an adjacent active region and a shallow trench isolation structure, the gate structure of the MOS transistor is formed on the surface of the active region, and the source and drain terminals are both formed within the active region.
[0018] Optionally, in the method of forming the radio frequency switch circuit, an oxide is deposited on the surface of the MOS gate structure to form a first interlayer dielectric layer on the surface of the MOS gate structure.
[0019] Optionally, in the method of forming the radio frequency switch circuit, oxides are deposited on the surfaces of the first metal line, the second metal line and the interlayer dielectric layer to form a second interlayer dielectric layer on the surfaces of the first metal line, the second metal line and the interlayer dielectric layer.
[0020] Optionally, in the method of forming the radio frequency switch circuit, an oxide is deposited on the surface of the second interlayer dielectric layer to form a third interlayer dielectric layer on the surface of the second interlayer dielectric layer.
[0021] Optionally, in the method of forming the radio frequency switch circuit, the aspect ratio of the gap formed between the first metal line and the second metal line is greater than 1:1.
[0022] The present invention also provides a radio frequency switching circuit, comprising:
[0023] SOI, wherein the SOI comprises a bottom silicon layer, a buried oxide layer and a top silicon layer stacked sequentially;
[0024] A plurality of spaced MOS gate structures are located on the surface of the top silicon layer, each of the MOS gate structures including a gate located on the surface of the top silicon layer, and a source terminal and a drain terminal located on both sides of the gate in the top silicon layer.
[0025] The first interlayer dielectric layer located on the surface of the MOS transistor gate structure;
[0026] A first metal line and a second metal line are spaced apart on the surface of the interlayer dielectric layer, with a portion of the surface of the first interlayer dielectric layer exposed between the first metal line and the second metal line. The first metal line is electrically connected to the source end, and the second metal line is electrically connected to the drain end.
[0027] A first nitride layer, a second interlayer dielectric layer, and a second nitride layer are sequentially located on the surfaces of the first metal line, the second metal line, and the first interlayer dielectric layer. The second nitride layer fills the gap formed by the first metal line and the second metal line. A first air gap is formed inside the second interlayer dielectric layer located between the first metal line and the second metal line. The size of the first air gap in the gate structure of the first two MOS transistors is larger than the size of the first air gap in the gate structure of the remaining MOS transistors.
[0028] A third interlayer dielectric layer is located on the surface of the second interlayer dielectric layer, and the third interlayer dielectric layer has a second air gap formed above the first air gap.
[0029] In the method for forming the radio frequency switch circuit provided by the present invention, a first air gap and a second air gap are formed in the first two stages of MOS transistors, and the size of the first air gap is increased, thereby increasing the size of the entire air gap, reducing the bias voltage of the first two stages of MOS transistors in the stack, improving the uniformity of the bias voltage of all MOS transistors in the stack, and thus improving the performance of the radio frequency switch circuit. Attached Figure Description
[0030] Figure 1 This is a flowchart of a method for forming a radio frequency switch circuit according to an embodiment of the present invention;
[0031] Figures 2 to 7 This is a schematic diagram of the formation process of the radio frequency switch circuit according to an embodiment of the present invention;
[0032] In the diagram: 201-bottom silicon, 202-buried oxide layer, 203-top silicon, 204-active region, 205-shallow trench isolation structure, 206-gate, 207-sidewall, 208-source terminal, 209-drain terminal, 210-first interlayer dielectric layer, 211-contact hole, 212-first metal line, 213-second metal line, 214-first nitride layer, 215-second interlayer dielectric layer, 216-first air gap, 217-second nitride layer, 218-patterned photoresist layer, 219-third interlayer dielectric layer, 220-second air gap. Detailed Implementation
[0033] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0034] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.
[0035] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.
[0036] Please refer to Figure 1 The present invention provides a method for forming a radio frequency switch circuit, comprising:
[0037] S11: Provides SOI, which includes a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially.
[0038] S12: A plurality of spaced MOS gate structures are formed on the surface of the top silicon layer. Each MOS gate structure includes a gate located on the surface of the top silicon layer, and a source terminal and a drain terminal located on both sides of the gate in the top silicon layer.
[0039] S13: Form the first interlayer dielectric layer on the surface of the gate structure of the MOS transistor;
[0040] S14: A first metal line and a second metal line are formed at intervals on the surface of the interlayer dielectric layer, with a portion of the surface of the first interlayer dielectric layer exposed between the first metal line and the second metal line. The first metal line is electrically connected to the source end, and the second metal line is electrically connected to the drain end.
[0041] S15: A first nitriding layer, a second interlayer dielectric layer and a second nitriding layer are sequentially formed on the surfaces of the first metal wire, the second metal wire and the first interlayer dielectric layer. The second nitriding layer fills the gap formed by the first metal wire and the second metal wire. A first air gap is formed inside the second interlayer dielectric layer located between the first metal wire and the second metal wire.
[0042] S16: Select the gate structure of the first two MOS transistors starting from the signal input terminal, and etch part of the first nitride layer and part of the second interlayer dielectric layer between the first metal line and the second metal line to expose the opening of the first air gap;
[0043] S17: Etch the remaining second dielectric layer located between the first metal line and the second metal line to increase the size of the first air gap;
[0044] S18: A third interlayer dielectric layer is formed on the surface of the second interlayer dielectric layer, and the third interlayer dielectric layer forms a second air gap above the first air gap.
[0045] Please refer to Figure 2 and Figure 3First, an SOI (Solid Oxide Insulation) is provided, comprising a bottom silicon layer 201, a buried oxide layer 202, and a top silicon layer 203 stacked sequentially. Ions are implanted into the top silicon layer 203 to form an active region 204. The active region 204 is etched to form multiple spaced shallow trenches. Then, oxides, such as silicon dioxide, are filled into the shallow trenches to form multiple spaced shallow trench isolation structures 205, which divide the active region 204 into multiple layers. Next, a gate polysilicon material layer is formed on the surface of each active region 204, and the gate polysilicon material is etched to form a gate 206 covering a portion of the active region surface. Then, sidewalls 207 are formed on both sides of the gate 206, located on the surface of a portion of the active region 204.
[0046] Next, ions are implanted into the active regions 204 on both sides of the gate to form source terminals 208 and drain terminals 209 within the active regions 204 on both sides of the gate. The gate 206, sidewall 207, source terminal 208, and drain terminal 209 serve as the gate structure of the MOS transistor. This forms multiple spaced MOS transistor gate structures, which are stacked to form an RF switching circuit.
[0047] Next, a first interlayer dielectric layer 210 is formed on the surface of the MOS transistor gate structure. The first interlayer dielectric layer 210 can be formed by depositing an oxide, such as silicon dioxide. Next, spaced contact holes 211 are formed in the first interlayer dielectric layer 210. One contact hole 211 is electrically connected to the source terminal 208, and the other contact hole 211 is electrically connected to the drain terminal 209.
[0048] Next, a first metal line 212 and a second metal line 213 are formed at intervals on the surfaces of the contact hole 211 and the first interlayer dielectric layer 210. A portion of the surface of the first interlayer dielectric layer 210 is exposed between the first metal line 212 and the second metal line 213, and the aspect ratio of the gap formed between the first metal line 212 and the second metal line 213 is greater than 1:1. The first metal line 212 is electrically connected to the source terminal 208 through the contact hole 211, and the second metal line 213 is electrically connected to the drain terminal 209 through the contact hole 211.
[0049] Next, a first nitride layer 214, a second interlayer dielectric layer 215, and a second nitride layer 217 are sequentially formed on the surfaces of the first metal line 212, the second metal line 213, and the first interlayer dielectric layer 210. The second interlayer dielectric layer 215 fills the gap between the first metal line 212 and the second metal line 213. The second interlayer dielectric layer 215 can be formed by depositing an oxide, such as silicon dioxide, and both the first nitride layer 214 and the second nitride layer 217 can be formed by depositing nitrides. Since the depth-to-width ratio of the gap between the first metal line 212 and the second metal line 213 is greater than 1:1, a first air gap 216 is formed between the first metal line 212 and the second metal line 213. The shape of the first air gap 216 is such that its width near the surface of the second interlayer dielectric layer 215 is smaller than its width away from the surface of the second interlayer dielectric layer 215; specifically, its shape may be an equilateral triangle.
[0050] Next, please refer to Figure 4 The gate structures of the first two MOS transistors, starting from the signal input terminal, are selected. A patterned photoresist layer 218 is formed on the surface of the second nitride layer 217. The patterned photoresist layer 218 is used as a mask for dry etching of a portion of the second nitride layer 217 and the second interlayer dielectric layer 215 to expose the opening of the first air gap 216. Then the patterned photoresist layer 218 is removed.
[0051] Next, please refer to Figure 5 The remaining second interlayer dielectric layer 215 between the first metal line 212 and the second metal line 213 is further etched using a wet etching method to increase the size of the first air gap 216. The increased size of the first air gap 216 can be rectangular. At this time, the first nitride layer 214 can serve as a barrier layer for wet etching. Furthermore, the wet etching can be an isotropic etching method, thus expanding the first air gap while simultaneously allowing the second nitride layer to cover a portion of the expanded first air gap 216.
[0052] Next, please refer to Figure 6 A third interlayer dielectric layer 219 is formed on the surface of the second nitride layer 217. The third interlayer dielectric layer 219 can be formed by depositing an oxide, such as silicon dioxide. Therefore, a second air gap 220 is formed above the third interlayer dielectric layer 219 and above the first air gap 216. Increasing the first air gap 216 and forming the second air gap 220 only applies to the first two stages of the MOS transistor gate structure. For other MOS transistor gate structures, it is not necessary to increase the size of the first air gap 216 or form the second air gap 220. Figure 7 .
[0053] The present invention also provides a radio frequency switching circuit, comprising: an SOI, wherein the SOI includes a bottom silicon, a buried oxide layer, and a top silicon stacked sequentially; a plurality of spaced MOS transistor gate structures located on the surface of the top silicon, each MOS transistor gate structure including a gate located on the surface of the top silicon, and a source terminal and a drain terminal located on both sides of the gate in the top silicon; a first interlayer dielectric layer located on the surface of the MOS transistor gate structures; a first metal line and a second metal line spaced apart on the surface of the interlayer dielectric layer, wherein a portion of the surface of the first interlayer dielectric layer is exposed between the first metal line and the second metal line, the first metal line being electrically connected to the source terminal, and the second metal line being... The line is electrically connected to the drain terminal; a first nitride layer, a second interlayer dielectric layer, and a second nitride layer are sequentially located on the surfaces of the first metal line, the second metal line, and the first interlayer dielectric layer. The second nitride layer fills the gap formed by the first metal line and the second metal line. A first air gap is formed inside the second interlayer dielectric layer located between the first metal line and the second metal line. The size of the first air gap in the gate structure of the first two MOS transistors is larger than the size of the first air gap in the gate structure of the remaining MOS transistors. A third interlayer dielectric layer is located on the surface of the second interlayer dielectric layer. A second air gap is formed above the first air gap in the third interlayer dielectric layer.
[0054] In summary, in the RF switch circuit and forming method provided in the embodiments of the present invention, a first air gap and a second air gap are formed in the first two stages of MOS transistors, and the size of the first air gap is increased, thereby increasing the size of the entire air gap, reducing the bias voltage of the first two stages of MOS transistors in the stack, improving the uniformity of the bias voltage of all MOS transistors in the stack, and thus improving the performance of the RF switch circuit.
[0055] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A method for forming a radio frequency switching circuit, characterized in that, include: An SOI is provided, the SOI comprising a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially. Multiple spaced MOS gate structures are formed on the surface of the top silicon layer. Each MOS gate structure includes a gate located on the surface of the top silicon layer, and a source terminal and a drain terminal located on both sides of the gate in the top silicon layer. A first interlayer dielectric layer is formed on the surface of the MOS gate structure; A first metal line and a second metal line are formed at intervals on the surface of the interlayer dielectric layer, with a portion of the surface of the first interlayer dielectric layer exposed between the first metal line and the second metal line. The first metal line is electrically connected to the source terminal, and the second metal line is electrically connected to the drain terminal. A first nitride layer, a second interlayer dielectric layer, and a second nitride layer are sequentially formed on the surfaces of the first metal line, the second metal line, and the first interlayer dielectric layer. The second nitride layer fills the gap formed by the first metal line and the second metal line. A first air gap is formed inside the second interlayer dielectric layer located between the first metal line and the second metal line. The gate structures of the first two MOS transistors starting from the signal input terminal are selected, and a portion of the first nitride layer and a portion of the second interlayer dielectric layer between the first metal line and the second metal line are etched to expose the opening of the first air gap. The remaining second dielectric layer located between the first and second metal lines is etched to increase the size of the first air gap; A third interlayer dielectric layer is formed on the surface of the second interlayer dielectric layer, and the third interlayer dielectric layer forms a second air gap above the first air gap.
2. The method for forming the radio frequency switch circuit as described in claim 1, characterized in that, Dry etching is used to etch a portion of the first nitride layer and a portion of the second interlayer dielectric layer between the first metal line and the second metal line to expose the opening of the first air gap.
3. The method for forming the radio frequency switch circuit as described in claim 1, characterized in that, Wet etching is used to etch the remaining second dielectric layer located between the first and second metal lines to increase the size of the first air gap.
4. The method for forming the radio frequency switch circuit as described in claim 1, characterized in that, The MOS transistor gate structure also includes sidewalls located on both sides of the gate.
5. The method for forming the radio frequency switch circuit as described in claim 1, characterized in that, The top silicon layer includes an adjacent active region and a shallow trench isolation structure. The gate structure of the MOS transistor is formed on the surface of the active region, and the source and drain terminals are both formed within the active region.
6. The method for forming the radio frequency switch circuit as described in claim 1, characterized in that, An oxide is deposited on the surface of the MOS gate structure to form a first interlayer dielectric layer on the surface of the MOS gate structure.
7. The method for forming the radio frequency switch circuit as described in claim 1, characterized in that, Oxides are deposited on the surfaces of the first metal line, the second metal line, and the interlayer dielectric layer to form a second interlayer dielectric layer on the surfaces of the first metal line, the second metal line, and the interlayer dielectric layer.
8. The method for forming the radio frequency switch circuit as described in claim 1, characterized in that, An oxide is deposited on the surface of the second interlayer dielectric layer to form a third interlayer dielectric layer on the surface of the second interlayer dielectric layer.
9. The method for forming the radio frequency switch circuit as described in claim 1, characterized in that, The aspect ratio of the gap formed between the first metal wire and the second metal wire is greater than 1:
1.
10. A radio frequency switch circuit formed using the method for forming a radio frequency switch circuit according to any one of claims 1 to 9, characterized in that, include: SOI, wherein the SOI comprises a bottom silicon layer, a buried oxide layer and a top silicon layer stacked sequentially; A plurality of spaced MOS gate structures are located on the surface of the top silicon layer, each of the MOS gate structures including a gate located on the surface of the top silicon layer, and a source terminal and a drain terminal located on both sides of the gate in the top silicon layer. The first interlayer dielectric layer located on the surface of the MOS transistor gate structure; A first metal line and a second metal line are spaced apart on the surface of the interlayer dielectric layer, with a portion of the surface of the first interlayer dielectric layer exposed between the first metal line and the second metal line. The first metal line is electrically connected to the source end, and the second metal line is electrically connected to the drain end. A first nitride layer, a second interlayer dielectric layer, and a second nitride layer are sequentially located on the surfaces of the first metal line, the second metal line, and the first interlayer dielectric layer. The second nitride layer fills the gap formed by the first metal line and the second metal line. A first air gap is formed inside the second interlayer dielectric layer located between the first metal line and the second metal line. The size of the first air gap in the gate structure of the first two MOS transistors is larger than the size of the first air gap in the gate structure of the remaining MOS transistors. A third interlayer dielectric layer is located on the surface of the second interlayer dielectric layer, and the third interlayer dielectric layer has a second air gap formed above the first air gap.