Cell structure, cell array, chip structure and generation method

Abstract

The invention relates to the technical field of semiconductors, in particular to a unit structure, a unit array, a chip structure and a generation method, the unit structure comprises a unit boundary, an active region and a preset number of grids, the active region and the preset number of grids are located in the unit boundary, each grid extends along a first direction, and the active region is located in the unit boundary. Each grid electrode is intersected with the active region; the distance between the center line of each grid electrode in the first direction and the boundary of a target unit is greater than or equal to the distance between the center lines of two adjacent grid electrodes in the first direction, and a space for accommodating a new grid electrode is formed between each grid electrode and the boundary of the target unit; the target unit boundaries are boundaries which are close to the grids and are parallel to the first direction. According to the embodiment of the invention, the density of the grid electrode is variable, so that the local density uniformity of pattern layout can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and in particular to a cell structure, cell array, chip structure, and method for its fabrication. Background Technology

[0002] Dummy patterns are typically used to reduce pattern layout variations and improve pattern uniformity. For example... Figure 1 As shown, the size, spacing, and density of each dummy cell and the dummy pattern in the cell array are fixed, which cannot be compatible with the design of high-density and low-density system-on-a-chip (SOC), resulting in poor local density uniformity of the pattern layout. Each cell structure includes an active area (AA)1 and a gate (poly)2.

[0003] like Figure 2 As shown, in order to improve the local uniformity of pattern layout, related technologies provide unit structures with different densities and add unit structures with different densities near different SOC patterns. However, related technologies greatly increase the number of unit structures, resulting in longer pattern layout time and increased process complexity. In addition, the complex process also limits the flexible design of density uniformity of pattern layout. Summary of the Invention

[0004] This application provides a cell structure, cell array, chip structure, and generation method to at least solve the aforementioned problems existing in the related technologies.

[0005] To solve the above-mentioned technical problems, the technical solution of this application is as follows:

[0006] According to a first aspect of the embodiments of this application, a cell structure is provided, including a cell boundary, an active region and a preset number of gates, wherein the active region and the preset number of gates are located within the cell boundary, each gate extends along a first direction, and each gate intersects with the active region.

[0007] The distance between the center line of each gate in the first direction and the boundary of the target cell is greater than or equal to the distance between the center lines of two adjacent gates in the first direction. A space for accommodating a new gate is formed between each gate and the boundary of the target cell. The boundary of the target cell is a boundary that is close to each gate and parallel to the first direction.

[0008] A second aspect of this application provides a unit array, the unit array including a preset number of unit structures as described in any of the above embodiments, the preset number of unit structures being arranged along a second direction, and adjacent unit structures being spliced ​​together with corresponding target unit boundaries as splicing lines, the second direction being perpendicular to the first direction.

[0009] A third aspect of the present application provides a chip structure including a first chip region and a second chip region, wherein the first chip region includes a system-on-a-chip and the second chip region is provided with a cell array as described in any of the above embodiments.

[0010] The position of the cell array in the second chip region is determined based on the density of the gate and active regions in the first chip region.

[0011] A fourth aspect of this application provides a method for generating a unit structure, the method being used to generate a unit structure as described in any of the above embodiments, the method comprising:

[0012] An initial cell structure is provided; the initial cell structure includes an initial cell boundary, an active region, and a preset number of gates; the active region and the preset number of gates are located within the cell boundary, each gate extends along a first direction, and each gate intersects with the active region;

[0013] The initial unit boundary is extended along the second direction by a first preset distance to obtain the unit boundary, thereby generating the unit structure;

[0014] Wherein, the second direction is perpendicular to the first direction, and the first preset distance is greater than or equal to 1 / 2 the distance between the center lines of two adjacent gates in the first direction.

[0015] A fifth aspect of this application provides a method for generating a cell array, the method being used to generate a cell array as described in the above embodiments, the method comprising:

[0016] Provides a preset number of unit structures;

[0017] A predetermined number of the unit structures are arranged along the second direction, and adjacent unit structures are spliced ​​together with the corresponding target unit boundary as the splicing line to obtain the unit array.

[0018] A sixth aspect of this application provides a method for generating a chip structure. The method generates the chip structure described in the above embodiments, the chip structure including a first chip region and a second chip region, wherein the first chip region is provided with a system-on-a-chip (SoC). The generation method includes:

[0019] Insert the cell array as described in the above embodiment into the second chip region;

[0020] Determine the density of active regions and gates in the first chip region;

[0021] Based on the density of the active region and the gate, the cell array is density transformed to obtain the density-transformed chip structure.

[0022] A seventh aspect of this application provides an electronic device, characterized in that the electronic device includes the chip structure described in the above embodiments.

[0023] The technical solutions provided by the embodiments of this application have at least the following beneficial effects:

[0024] The cell structure provided in this application includes a cell boundary, an active region, and a predetermined number of gates. The active region and the predetermined number of gates are located within the cell boundary. Each gate extends along a first direction and intersects with the active region. Since the distance between the centerline of each gate and the target cell boundary is greater than or equal to the distance between the centerlines of two adjacent gates, the reserved space of the cell boundary is enlarged. This space is used to accommodate new gates, thereby making the gate density variable. This improves the local density uniformity of the pattern layout. Furthermore, the cell structure provided in this application is of only this type, thereby reducing pattern layout time and lowering the process complexity of pattern layout. The lower complexity process also improves the flexibility of designing local density uniformity of the pattern.

[0025] The unit array provided in this application embodiment is obtained by splicing a preset number of unit structures in a second direction. The spliced ​​unit array is composed of one of the unit structures described above, thereby reducing the unit array layout time and lowering the process complexity of pattern layout. In addition, since the density of the pattern in the unit array is variable, the density of the unit array is also variable, thereby further improving the local density uniformity of the pattern layout.

[0026] The chip structure provided in this application includes a first chip region and a second chip region. The second chip region is provided with unit structures of different density variations, thereby enabling the acquisition of density gain through the unit structure of the type described above, and improving the local density uniformity of the chip structure.

[0027] The cell structure generation method provided in this application generates the cell structure by extending the initial cell boundary along a second direction by a first preset distance to obtain the cell boundary. The first preset distance is greater than or equal to 1 / 2 the distance between the center lines of two adjacent gates, so that the distance between the center line of each gate and the target cell boundary is greater than or equal to the distance between the center lines of two adjacent gates, thereby enlarging the reserved space of the cell boundary. This space is used to accommodate new gates, thereby making the gate density variable. As a result, the local density uniformity of the pattern layout can be improved.

[0028] The method for generating a unit array provided in this application obtains the unit array by splicing the target unit boundaries of each unit structure in a second direction, so that the spliced ​​unit array is composed of a single unit structure, thereby reducing the unit array layout time and lowering the process complexity of pattern layout.

[0029] The chip structure generation method provided in this application embodiment inserts a cell array into the second chip region, determines the density of the active region and gate in the first chip region, and performs density transformation on the cell array according to the density of the active region and gate to obtain a density-transformed chip structure. This allows for automatic determination of whether density transformation of the cell array is needed based on the density of the active region and gate, and the acquisition of multiple density variants from the cell array based on the density calculation results. This enables the acquisition of density gain through a cell structure of the type described above, thereby improving the local density uniformity of the chip structure.

[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.

[0032] Figure 1 This is a schematic diagram of the unit structure and unit array in related technologies.

[0033] Figure 2 This is a schematic diagram of adding unit structures of different densities near different SOC patterns in related technologies.

[0034] Figure 3 This is a schematic diagram illustrating a unit structure according to an exemplary embodiment.

[0035] Figure 4 This is a schematic diagram of a cell array according to an exemplary embodiment.

[0036] Figure 5 This is a schematic diagram illustrating a gate density transformation according to an exemplary embodiment.

[0037] Figure 6 This is a schematic diagram illustrating an active region density transformation according to an exemplary embodiment.

[0038] Figure 7 This is a schematic diagram illustrating a chip structure according to an exemplary embodiment.

[0039] Figure 8 This is a flowchart illustrating a method for generating a unit structure according to an exemplary embodiment.

[0040] Figure 9 This is a schematic diagram illustrating a method for generating a unit structure by extending unit boundaries, according to an exemplary embodiment.

[0041] Figure 10 This is a flowchart illustrating a method for generating a cell array according to an exemplary embodiment. Figure 1 .

[0042] Figure 11 This is a schematic diagram illustrating a process for generating a target gate according to an exemplary embodiment.

[0043] Figure 12 This is a schematic diagram illustrating the generation of a target gate according to an exemplary embodiment.

[0044] Figure 13 This is a flowchart illustrating a method for generating a cell array according to an exemplary embodiment. Figure 2 .

[0045] Figure 14 This is a schematic diagram illustrating the generation of an active region according to an exemplary embodiment.

[0046] Figure 15 This is a flowchart illustrating a method for generating a chip structure according to an exemplary embodiment. Figure 1

[0047] Figure 16 This is a flowchart illustrating a method for generating a chip structure according to an exemplary embodiment. Figure 2 .

[0048] Figure 17 This is a schematic diagram illustrating a transformation of the density of a cell array according to an exemplary embodiment.

[0049] The following is a supplementary explanation of the reference numerals in the accompanying drawings:

[0050] 1-Active region, 2-Gate, 3-Target gate, 4-Target active region, 5-Initial gate, 6-Candidate gate, 7-Active region. Detailed Implementation

[0051] The following provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below in a simplified manner. Of course, these elements and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances throughout this application. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0052] Additionally, spatial relative terms, such as “below,” “under,” “lower part,” “above,” “upper part,” “front,” “back,” “above,” and similar terms, may be used in this application for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures.

[0053] This application provides a unit structure, which includes a unit boundary, an active region, and a preset number of gates. The active region and the preset number of gates are located within the unit boundary, and each gate extends along a first direction and intersects with the active region.

[0054] The distance between the center line of each gate in the first direction and the boundary of the target cell is greater than or equal to the distance between the center lines of two adjacent gates in the first direction. A space for accommodating a new gate is formed between each gate and the boundary of the target cell. The boundary of the target cell is a boundary that is close to each gate and parallel to the first direction.

[0055] In this embodiment, the unit structure includes a unit boundary, an active region 1 located within the unit boundary, and a predetermined number of gates 2. It should be noted that the active region in the unit structure refers to the pattern corresponding to the active region, which is used to generate the active region in the substrate during the semiconductor fabrication process. The gate in the unit structure refers to the pattern corresponding to the gate, which is used to generate a polysilicon gate in the substrate during the semiconductor fabrication process.

[0056] Optionally, the preset number of gates 2 can be set according to actual needs, and there is no specific limitation thereto. The preset number of gates 2 intersect with the active region 1 respectively.

[0057] Optionally, the first direction of each gate 2 refers to the length direction of each gate 2, and the center line of each gate 2 in the first direction refers to the center line parallel to the length direction of each gate 2.

[0058] In one embodiment, the shape enclosed by the cell boundary is a regular shape, such as a rectangle. When the shape enclosed by the cell boundary is a regular shape, the target cell boundary is a boundary close to each of the gates and parallel to the first direction.

[0059] It should be noted that, since there are a predetermined number of gates 2, each of which intersects with the active region 1, and there is a certain distance between the center lines of adjacent gates 2 in the first direction, the distance between the center line of each gate 2 in the first direction and the boundary of the target cell needs to be greater than or equal to the distance between the center lines of adjacent gates 2 in the first direction. This enlarges the reserved space at the cell boundary, which is used to accommodate at least one new gate 2. Therefore, the gate density can be variable, thereby improving the local density uniformity of the pattern layout. Furthermore, the cell structure provided in this embodiment has only one type (i.e., the distance between the center line of each gate in the first direction and the boundary of the target cell is greater than or equal to the distance between the center lines of adjacent gates in the first direction, and a space is formed between each gate and the boundary of the target cell to accommodate a new gate), thereby reducing the pattern layout time and the process complexity of the pattern layout. The lower complexity process also improves the flexibility of designing the local density uniformity of the pattern layout.

[0060] In an optional embodiment, the preset number of gates 2 is two, and the number of active regions 1 is one, with the two gates 2 intersecting with one active region 1. By setting an intersecting active region and two gates in the cell structure, density gain is achieved through a fixed type of cell structure, improving the local density uniformity of the chip structure, thereby reducing patterning time and lowering the process complexity of patterning. The lower complexity process also improves the flexibility of designing the local density uniformity of the pattern layout.

[0061] In an optional embodiment, the distance between the center line of each gate 2 in the first direction and the boundary of the target cell is a preset number multiple of the distance between the center lines of two adjacent gates 2 in the first direction, and a space for accommodating a target number of new gates is formed between each gate 2 and the boundary of the target cell, wherein the target number is a number corresponding to the preset number multiple, and the preset number multiple is an integer multiple greater than or equal to 1.

[0062] In this embodiment, when the preset multiple is 1, it means that when the distance between the center line of each gate in the first direction and the boundary of the target unit is equal to the distance between the center lines of two adjacent gates in the first direction, the reserved space of the unit boundary is enlarged (equivalent to being able to accommodate half a gate). When the unit structure is spliced ​​together with another unit structure, since the reserved space of the unit boundary of the other unit structure is also enlarged (equivalent to being able to accommodate half a gate), when the two unit structures are spliced ​​together, the reserved space obtained is just enough to accommodate a new gate, and the size of the new gate is the same as the size of the original gate, and the distance between each gate is also the same, thereby reducing the gate density and making the gate density variable, thereby improving the local density uniformity of the pattern layout.

[0063] When the preset multiple is greater than or equal to 2, the space is used to accommodate a number of new gates corresponding to the preset multiple. The reserved space at the unit boundary is further enlarged. When the unit structure is spliced ​​with another unit structure, since the reserved space at the unit boundary of the other unit structure is also further enlarged, the reserved space obtained when the two unit structures are spliced ​​together can accommodate at least two new gates. The size of the new gate is the same as the size of the original gate, and the distance between each gate is also the same. This further reduces the gate density, making the gate density more variable, thereby further improving the local density uniformity of the pattern layout.

[0064] Taking a preset quantity multiple of 2 as an example, with this setting, the reserved space formed by one unit structure can accommodate 1 gate plus half a gate, and the reserved space formed by another unit structure can also accommodate 1 gate plus half a gate. Combining these two structures, the reserved space can accommodate 3 gates. With a preset quantity multiple of 3, the space formed by one unit structure can accommodate 2 gates plus half a gate, and the reserved space formed by another unit structure can also accommodate 2 gates plus half a gate. Combining these two structures, the reserved space can accommodate 5 gates. That is, when the preset quantity multiple is greater than or equal to 2, combining two unit structures can accommodate a maximum of 2N+1 new gates, where N is the preset quantity multiple.

[0065] Figure 3 This is a schematic diagram illustrating a unit structure according to an exemplary embodiment, such as... Figure 3 Assuming the shape enclosed by the cell boundaries is rectangular, there are two gates 2 and one active region 1. The two gates 2 are the first gate and the second gate, respectively. The center line of the first gate in the first direction (e.g., the Y direction) is the first center line, and the center line of the second gate in the first direction (e.g., the Y direction) is the second center line. The target cell boundary of the first gate is the first boundary, and the target cell boundary of the second gate is the second boundary. Then, the distance between the first center line and the first boundary is greater than or equal to the distance between the first center line and the second center line, and the distance between the second center line and the second boundary is also greater than or equal to the distance between the first center line and the second center line.

[0066] Continue as Figure 3 As shown, when the distance between the first center line and the first boundary is equal to the distance between the first center line and the second center line, and the distance between the second center line and the second boundary is also equal to the distance between the first center line and the second center line, the space between the first gate and the corresponding first boundary is enlarged, and the reserved space between the gate 2 and the corresponding second boundary is enlarged. This reserved space is equivalent to accommodating half a gate. When this unit structure is spliced ​​with another unit structure, the reserved space corresponding to the other unit structure can also accommodate half a gate. When the two are spliced ​​together, a new gate can be accommodated.

[0067] When the distance between the first center line and the first boundary is greater than the distance between the first center line and the second center line (assumed to be twice the distance between the first center line and the second center line), and the distance between the second center line and the second boundary is also greater than the distance between the first center line and the second center line (assumed to be twice the distance between the first center line and the second center line), the space between the first gate and the corresponding first boundary is further enlarged, and the space between the gate 2 and the corresponding second boundary is also further enlarged. This space is used to accommodate a new gate + half a gate. When this unit structure is spliced ​​together with another unit structure (the space corresponding to the other gate is also used to accommodate a new gate + half a gate), the two spliced ​​together can accommodate three gates.

[0068] This application provides a unit array, which includes a preset number of unit structures as described in any of the above embodiments. The preset number of unit structures are arranged along a second direction, and adjacent unit structures are spliced ​​together with the corresponding target unit boundary as the splicing line. The second direction is perpendicular to the first direction.

[0069] In this embodiment, the second direction is perpendicular to the first direction. Assuming the cell structure is rectangular, the first direction is the Y direction, and the second direction is the X direction. The target cell boundary is a boundary close to each of the gates and parallel to the first direction.

[0070] It should be noted that this preset quantity can be set according to actual business needs, and there is no specific limit to it.

[0071] Figure 4 This is a schematic diagram of a cell array according to an exemplary embodiment. Assuming there are three cell structures, the second direction is perpendicular to the first direction, and the target cell boundary is a boundary parallel to the extension direction of the gate 2, the target cell boundaries corresponding to the three cell structures are spliced ​​together in the second direction to obtain a cell array. Since the cell array obtained by this splicing consists of one type of cell structure, the cell array layout time is reduced, and the process complexity of the pattern layout is lowered. Simultaneously, since the density of poly in the cell structure is variable, the density of the pattern in the cell array is also variable, thereby further improving the local density uniformity of the pattern layout. Furthermore, embodiments of this application can splice any number of cell structures in the above manner, thereby facilitating the generation of cell variants with different densities, further improving the local density uniformity of the pattern layout, and making the design of the local density uniformity of the pattern layout more flexible.

[0072] In an optional embodiment, in order to achieve density transformation of the unit structure, a number of unit structures with at least two consecutive splices can be obtained from a preset number of unit structures spliced ​​to form a unit array. For example, two consecutive splices of unit structures, three consecutive splices of unit structures, four consecutive splices of unit structures, etc.

[0073] A target gate 3 is disposed around the splicing line of the at least two consecutive spliced ​​unit structures, and the center line of the target gate 3 is the splicing line of the at least two consecutive spliced ​​unit structures.

[0074] It should be noted that the size of the target gate 3 is the same as the size of the gate 2 included in each unit structure, and the distance between the target gate 3 and other gates is the same as the distance between the gates 2 included in each unit structure.

[0075] Figure 5 This is a schematic diagram illustrating a gate density transformation according to an exemplary embodiment, such as... Figure 5 As shown, this unit array is formed by splicing together 6 unit structures in the second direction. Figure 5 The density of gate 2 and active region 1 in the reference cell array (i.e., the cell array without adding new gates) is low.

[0076] Continue as Figure 5 As shown, when "at least two consecutively spliced ​​unit structures" are two consecutively spliced ​​unit structures, the six unit structures can be divided into three groups. For each group of two consecutively spliced ​​unit structures, a target gate 3 can be set around its splicing line to increase the poly density and obtain a density unit variant with variable poly density, namely the second unit array. The poly density in the second unit array is higher than the poly density in the reference unit array.

[0077] Continue as Figure 5 As shown, in cases where "at least two consecutively spliced ​​unit structures" refers to two consecutively spliced ​​unit structures and four consecutively spliced ​​unit structures, the six unit structures can be divided into two groups. One group has four consecutively spliced ​​unit structures, and the other group has two consecutively spliced ​​unit structures. For the four consecutively spliced ​​unit structures, a target gate 3 can be set around their splicing lines. For the two consecutively spliced ​​unit structures, a target gate 3 can also be set around their splicing lines, thereby further increasing the poly density and obtaining a density unit variant with variable poly density, namely the third unit array. The poly density in this third unit array is higher than the poly density in the second unit array.

[0078] And so on, continuing as follows Figure 5 As shown, in the case where "at least two consecutively spliced ​​unit structures" are spliced ​​to obtain a unit array of 6 unit structures, the 6 unit structures can be divided into a group, and a target gate 3 can be generated on each splicing line, thereby further reducing the poly density and obtaining a density unit variant with variable poly density, namely the Nth unit array, in which the poly density is the highest.

[0079] It should be noted that the second, third, and Nth cell arrays can be considered as non-reference cell arrays.

[0080] Therefore, by setting target gates around the splicing line of at least two consecutive spliced ​​unit structures, the gate density can be increased to different degrees, that is, the gate density can be changed to different degrees, thereby generating unit variants with different densities, which can further improve the local density uniformity of the pattern layout and make the design of the local density uniformity of the pattern layout more flexible.

[0081] In an optional embodiment, this application can increase not only the density of the poly but also the density of the active region. To increase the density of the active region, active regions can be merged at the boundary. Specifically, the gates closest to the target gate in two adjacent unit structures can be designated as candidate gates, and an active region is formed between the center lines of the candidate gates. A target active region is formed in the active region, and the target active region intersects with the target gate.

[0082] Figure 6 This is a schematic diagram illustrating an active region density transformation according to an exemplary embodiment, continuing as follows: Figure 6 As shown, for the second cell array, the gates closest to the target gate 3 in two adjacent cell structures can be identified as candidate gates. An active region is formed between the center lines of the candidate gates, and a target active region 4 is formed within this active region, such that the target active region 4 intersects with the target gate 3. The AA density in this second cell array is higher than the AA density in the reference cell array.

[0083] Continue as Figure 6 As shown, for the third cell array, the gates closest to the target gate 3 in four adjacent cell structures can be designated as candidate gates. An active region is formed between the center lines of the candidate gates, and a target active region 4 is formed within this active region, such that the target active region 4 intersects with the target gate 3. Similarly, the gates closest to the target gate 3 in two adjacent cell structures can be designated as candidate gates. An active region is formed between the center lines of the candidate gates, and a target active region 4 is formed within this active region, such that the target active region 4 intersects with the target gate 3. The AA density in this third cell array is higher than the AA density in the second cell array.

[0084] Continue as Figure 6 As shown, for the Nth cell array, the gates closest to the target gate 3 in the six adjacent cell structures can be identified as candidate gates. An active region is formed between the center lines of the candidate gates, and a target active region 4 is formed in this active region, such that the target active region 4 intersects with the target gate 3. The density of AA is the highest in this Nth cell array.

[0085] Therefore, by forming an active region between the center lines of the candidate gates in two adjacent cell structures, and forming a target active region 4 in the active region, the AA density can be increased to different degrees, that is, the density of AA can be changed to different degrees, thereby generating cell variants with different densities, and further improving the local density uniformity of the pattern layout, making the design of the local density uniformity of the pattern layout more flexible.

[0086] This application also provides a chip structure, which includes a first chip region and a second chip region. The first chip region includes a system-on-a-chip, and the second chip region is provided with the reference cell array described in the above embodiments.

[0087] The position of the cell array in the second chip region is determined based on the density of the gate and active regions in the first chip region.

[0088] Optionally, the first chip area is a system-on-a-chip area, and the second chip area is a non-system-on-a-chip area, which is an area where no system-on-a-chip is installed.

[0089] In this embodiment, the density of the gate and active regions in the first chip region can be pre-calculated, and the position of the cell array in the second chip region can be determined based on this density, as well as the position of the reference cell array in the second chip region. Thus, based on the existing AA and poly densities in the chip structure, it is possible to determine which cell arrays need density transformation and which do not, thereby improving the local density uniformity of the chip structure by filling cell arrays with different AA and poly densities.

[0090] In an optional embodiment, a target gate is disposed around the splicing line of at least two consecutively spliced ​​unit structures, the center line of the target gate being the splicing line of the spliced ​​unit structures, and the unit array disposed with the target gate is located in a first region of the second chip region; no target gate is disposed around the splicing line of at least two consecutively spliced ​​unit structures, and the unit array without the target gate is located in a second region of the second chip region.

[0091] The first region is located near the region in the first chip region where the density of the gate and active regions is greater than or equal to the density threshold, and the second region is located near the region in the first chip region where the density of the gate and active regions is less than the density threshold.

[0092] In this embodiment, regions where the density of the gate and active regions in the first chip region is less than a density threshold can be determined based on the density of the gate and active regions in the first chip region, and regions where the density of the gate and active regions in the first chip region is greater than or equal to the density threshold. A first region in the second chip region adjacent to the region with a density greater than or equal to the density threshold is also determined, as well as a second region in the second chip region where the density is less than the density threshold. The non-reference cell array is located in the first region of the second chip region, and the reference cell array is located in the second region of the second chip region. The reference cell array refers to a cell array without a target gate, i.e., the area around the splicing line of at least two consecutively spliced ​​cell structures is not provided with a target gate. The non-reference cell array refers to a cell array with the target gate, i.e., a cell array with a target gate provided around the splicing line of at least two consecutively spliced ​​cell structures. It should be noted that "the splicing line of two consecutively spliced ​​unit structures is surrounded by a target gate" includes the fact that the splicing line of any two consecutively spliced ​​unit structures is surrounded by a target gate. When the splicing line of any two consecutively spliced ​​unit structures is surrounded by a target gate, the density of gates and active regions in the unit array reaches its maximum.

[0093] Because the density of AA and poly in the reference cell array is low, placing the reference cell array near the region where the density of the gate and active regions in the first chip region is less than the density threshold can improve the density uniformity of this region. Conversely, because the density of AA and poly in the non-reference cell array is high, placing the non-reference cell array near the region where the density of the gate and active regions in the first chip region is greater than or equal to the density threshold can improve the density uniformity of this region. Thus, by filling cell arrays with different AA and poly densities, the local density uniformity of the chip structure is improved.

[0094] Figure 7 This is a schematic diagram illustrating a chip structure according to an exemplary embodiment, such as... Figure 7 As shown, in the second chip region, near the first chip region where the density of the gate and active regions is less than the density threshold, a reference cell array with low AA and poly densities is provided. In the first chip region, near the first chip region where the density of the gate and active regions is greater than or equal to the density threshold, a non-reference cell array with high AA and poly densities is provided.

[0095] It should be noted that, Figure 7 This is merely one example; in other implementations, the non-referenced cell array disposed in the second region can be...Figure 6 Any non-reference cell array in the array.

[0096] Figure 8 This is a flowchart illustrating a method for generating a unit structure according to an exemplary embodiment, such as... Figure 8 As shown, the method for generating this unit structure may include:

[0097] S11. Provide an initial cell structure; the initial cell structure includes an initial cell boundary, an active region, and a preset number of gates; the active region and the preset number of gates are located within the initial cell boundary, each gate extends along a first direction, and each gate intersects with the active region.

[0098] S12. Extend the initial cell boundary along the second direction by a first preset distance to obtain the cell boundary, thereby generating the cell structure; wherein, the second direction is perpendicular to the first direction, and the first preset distance is greater than or equal to 1 / 2 the distance between the center lines of two adjacent gates in the first direction.

[0099] It should be noted that the dimensions of the active region and the gate included in this initial unit structure, as well as the positional relationship between them, are the same as those of the active region 1 and the gate 2 included in the unit structure.

[0100] Optionally, the second direction is perpendicular to the first direction. For example, if the first direction is the Y direction, then the second direction is the X direction.

[0101] Optionally, the first preset distance is greater than or equal to half the distance between the center lines of two adjacent gates in the first direction.

[0102] In this embodiment, after extending the initial cell boundary along the second direction by a first preset distance to obtain the cell boundary, the AA and poly elements located within the cell boundary can be used to generate the cell structure. It should be noted that the size and position of the AA and poly elements do not change during boundary extension, thus increasing the reserved space within the cell boundary after extension. This space is used to accommodate new gates. Therefore, the gate density can be increased, making the gate density variable, thereby improving the local density uniformity of the pattern layout.

[0103] In an optional embodiment, the first preset distance being greater than or equal to half the distance between the center lines of two adjacent gates 2 in the first direction can refer to: the first preset distance being a preset multiple of half the distance between the center lines of the gates 2 in the first direction, wherein the preset multiple is an integer multiple greater than or equal to 1.

[0104] In one embodiment, when the first preset distance is equal to half the distance between the center lines of two adjacent gates 2 in the first direction (corresponding to the distance between the center line of each gate in the first direction and the target unit boundary being equal to the distance between the center lines of two adjacent gates in the first direction), the initial unit boundary is extended along the second direction by half the distance between the center lines. The reserved space of the unit boundary is enlarged (equivalent to being able to accommodate half a gate). When the unit structure is spliced ​​together with another unit structure, since the reserved space of the unit boundary of the other unit structure is also enlarged (equivalent to being able to accommodate half a gate), the reserved space of the two spliced ​​unit structures can just accommodate a new gate, and the size of the new gate is the same as the size of the original gate, and the distance between each gate is also the same, thereby increasing the gate density, making the gate density variable, and thus improving the local density uniformity of the pattern layout.

[0105] Taking AA as one unit and poly as two units as an example, the process of generating unit structures is explained. Figure 9 This is a schematic diagram illustrating a method for generating a unit structure by extending unit boundaries, according to an exemplary embodiment. Figure 9 As shown, the initial cell boundary is extended by half the distance between the center lines in the second direction and stops at the center line of the subsequently generated new target gate, thereby enlarging the reserved space of the cell boundary.

[0106] In another embodiment, when the first preset distance is greater than half the distance between the center lines of two adjacent gates 2 in the first direction (corresponding to the distance between the center line of each gate in the first direction and the target unit boundary being greater than the distance between the center lines of two adjacent gates in the first direction), the initial unit boundary is extended along the second direction by a preset number of times the half distance between the center lines. The reserved space of the unit boundary is further enlarged. When the unit structure is spliced ​​together with another unit structure, since the reserved space of the unit boundary of the other unit structure is also further enlarged, the reserved space of the two spliced ​​unit structures can accommodate at least one new gate, and the size of the new gate is the same as the size of the original gate, and the distance between each gate is also the same, thereby increasing the gate density, making the gate density variable, and thus improving the local density uniformity of the pattern layout.

[0107] Figure 10 This is a flowchart illustrating a method for generating a cell array according to an exemplary embodiment. Figure 1 ,like Figure 10As shown, this application embodiment also provides a method for generating a cell array. This method is used to generate the reference cell array in the above embodiments. The method for generating the cell structure includes:

[0108] S21. Provides a preset number of unit structures.

[0109] S22. Arrange a preset number of the unit structures along the second direction, and splice adjacent unit structures together with the corresponding target unit boundary as the splicing line to obtain the unit array.

[0110] In this embodiment, the second direction is perpendicular to the first direction. Assuming the unit structure is rectangular, the first direction is the Y direction, and the second direction is the X direction, the target unit boundary is the boundary close to each of the gates and parallel to the first direction. It should be noted that this preset quantity can be set according to actual business needs and is not specifically limited thereto.

[0111] Because the resulting unit array is composed of a single type of unit structure, the unit array layout time is reduced, and the process complexity of pattern layout is lowered. Simultaneously, since the density of poly units in the unit structure is variable, the density of the pattern in the unit array is also variable, thereby further improving the local density uniformity of the pattern layout. Furthermore, embodiments of this application can splice any number of unit structures in the above manner, which facilitates the generation of unit variants with different densities, further improving the local density uniformity of the pattern layout and making the design of the local density uniformity of the pattern layout more flexible.

[0112] Figure 11 This is a schematic diagram illustrating a process for generating a target gate according to an exemplary embodiment, such as... Figure 11 As shown, the method for generating the target gate includes:

[0113] S21. Provides a preset number of unit structures.

[0114] S22. Arrange a preset number of the unit structures along the second direction, and splice adjacent unit structures together with the corresponding target unit boundary as the splicing line to obtain the unit array.

[0115] S23. The splicing line of at least two consecutively spliced ​​unit structures is grown a second preset distance in the second direction to obtain an initial gate.

[0116] S24. The initial gate is compressed in a first direction to obtain the target gate.

[0117] The preset number of unit structures includes at least two consecutively spliced ​​unit structures, the center line of the target gate is the splicing line of the spliced ​​unit structures, and the second preset distance is half the width of the gate included in the unit structure.

[0118] In this embodiment, to achieve density transformation of the unit structure, a number of at least two consecutively spliced ​​unit structures can be obtained from a predetermined number of unit structures spliced ​​together to form a unit array. For example, two consecutively spliced ​​unit structures, three consecutively spliced ​​unit structures, four consecutively spliced ​​unit structures, etc. Then, using the splicing line of the at least two consecutively spliced ​​unit structures as the initial position, a second predetermined distance is grown in a second direction to obtain an initial gate 5. Optionally, the second predetermined distance is half the width of the gate 2 included in the unit structure. Next, the initial gate 5 is compressed in a first direction so that the length of the compressed gate is equal to the length of the gate 2 included in the unit structure, to obtain the target gate 3.

[0119] Continue as Figure 5 In the case where "at least two consecutively spliced ​​unit structures" are two consecutively spliced ​​unit structures, the six unit structures can be divided into three groups. For each group of two consecutively spliced ​​unit structures, the splicing line can be grown a second preset distance in the second direction to obtain an initial gate, and then compressed in the first direction to obtain a target gate. Thus, three target gates 3 can be obtained.

[0120] The following explanation uses a cell array comprising two cell structures as an example to illustrate the process of generating the target gate:

[0121] Figure 12 This is a schematic diagram illustrating the generation of a target gate according to an exemplary embodiment, such as... Figure 12 As shown, the splicing line of two consecutively spliced ​​unit structures is grown a second preset distance in the second direction to obtain an initial gate 5. The initial gate 5 is compressed in the first direction so that the length of the compressed gate is equal to the length of the gate 2 included in the unit structure to obtain the target gate 3.

[0122] Therefore, by growing the splicing line a second preset distance in the second direction and compressing it in the first direction to generate the target gate, the generation difficulty of the target gate can be reduced and the generation efficiency of the target gate can be improved, thereby reducing the pattern layout time and the process complexity of the pattern layout. The process with lower complexity also improves the flexibility of the design of the local density uniformity of the pattern layout. In addition, by setting the target gate around the splicing line of at least two consecutive spliced ​​unit structures, the gate density can be reduced to different degrees, that is, the gate density can be changed to different degrees, thereby generating unit variants with different densities, which can further improve the local density uniformity of the pattern layout and make the design of the local density uniformity of the pattern layout more flexible.

[0123] Figure 13 This is a flowchart illustrating a method for generating a cell array according to an exemplary embodiment. Figure 2 ,like Figure 13 As shown, this generation method is used to generate the non-reference cell array in the above embodiments. The method for generating the cell array includes:

[0124] S21. Provides a preset number of unit structures.

[0125] S22. Arrange a preset number of the unit structures along the second direction, and splice adjacent unit structures together with the corresponding target unit boundary as the splicing line to obtain the unit array.

[0126] S23. The splicing line of at least two consecutively spliced ​​unit structures is grown a second preset distance in the second direction to obtain an initial gate.

[0127] S24. The initial gate is compressed in a first direction to obtain the target gate.

[0128] S25. Determine the center line of the candidate gate in two adjacent cell structures.

[0129] S26. The active region is determined by the distance between the center lines as the length and the width of the active region included in the unit structure as the width.

[0130] S27. Generate a target active region in the active region.

[0131] Wherein, the candidate gate is the gate closest to the target gate in two adjacent unit structures, and the target active region intersects with the target gate.

[0132] Optionally, embodiments of this application can change not only the density of the poly region but also the density of the active region. To change the density of the active region, the active regions can be merged at the boundaries.

[0133] The following explanation uses at least two consecutively joined unit structures as an example to illustrate the process of generating the target active region:

[0134] Figure 14 This is a schematic diagram illustrating the generation of an active region according to an exemplary embodiment, such as... Figure 14 As shown, after obtaining the target gate 3, the gates closest to the target gate 3 in two adjacent unit structures can be identified as candidate gates 6. The active regions within the candidate gates 6 are then connected to obtain the target active region 4. Specifically, an active region region 7 can be defined with the distance between the center lines as its length and the width of the active region 1 included in the unit structure as its width. The target active region 4 is then generated within the active region region 7. The target active region 4 intersects with the target gate 3.

[0135] Therefore, by defining the active region region 7 with the distance between the center lines as the length and the width of the active region 1 included in the unit structure as the width, and generating the target active region 4 in the active region region 7, the generation difficulty of the target active region 4 can be reduced, the generation efficiency of the target active region can be improved, thereby reducing the pattern layout time and the process complexity of the pattern layout. The process with lower complexity also improves the flexibility of the design of the local density uniformity of the pattern layout. In addition, by forming the active region region 7 between the center lines of the candidate gates 6 in two adjacent unit structures, and forming the target active region 4 in the active region region 7, the AA density can be increased by different magnitudes, that is, the density of AA can be changed to different degrees, thereby generating unit variants with different densities, which can further improve the local density uniformity of the pattern layout, making the design of the local density uniformity of the pattern layout more flexible.

[0136] Figure 15 This is a flowchart illustrating a method for generating a chip structure according to an exemplary embodiment. Figure 1 ,like Figure 15 As shown, the chip structure includes a first chip region and a second chip region, wherein the first chip region is provided with a system-on-a-chip (SoC), and the generation method includes:

[0137] S31. Insert the reference cell array described in any of the above embodiments into the second chip region.

[0138] S32. Determine the density of the active region and gate in the first chip region.

[0139] S33. Based on the density of the active region and the gate, perform density transformation on the cell array to obtain the density-transformed chip structure.

[0140] In this embodiment, the chip structure includes a first chip area and a second chip area. The first chip area is provided with a system-on-a-chip (SoC), and the second chip area is a region without a SoC. For example, the first chip area is a SoC area, and the second chip area is a non-SoC area.

[0141] Optionally, a reference cell array can be inserted into the second chip region first, and then the density of the active region and gate in the first chip region can be determined. Based on this density, it can be determined which cell arrays need density transformation and which do not. For cell arrays that need density transformation, density transformation processing is performed according to the above-described method of generating poly and merging AA, resulting in a density-transformed chip structure. Thus, based on the existing AA and poly densities in the chip structure, it is possible to determine which cell arrays need density transformation and which do not, thereby improving the local density uniformity of the chip structure by filling cell arrays with different AA and poly densities.

[0142] Figure 16 This is a flowchart illustrating a method for generating a chip structure according to an exemplary embodiment. Figure 2 ,like Figure 16 As shown, in an optional embodiment, in step S33 above, the density transformation of the cell array based on the density of the active region and the gate may include:

[0143] S331. Based on the density of the active region and the gate, determine the region in the first chip region where the density of the gate and the active region is less than a density threshold, and determine the region in the first chip region where the density of the gate and the active region is greater than or equal to the density threshold.

[0144] S333. Determine a first region in the second chip region that is close to the region with a density greater than or equal to the density threshold, and determine a second region in the second chip region that is close to the region with a density less than the density threshold.

[0145] S335. Maintain the cell array located in the second region and perform density transformation processing on the cell array located in the first region to obtain a density-transformed cell array, so as to adjust the local density uniformity of the chip structure.

[0146] In this embodiment, regions in the first chip region where the density of the gate and active regions is less than a density threshold can be determined based on the density of the gate and active regions in the first chip region, and regions where the density of the gate and active regions in the first chip region is greater than or equal to the density threshold. Furthermore, a second region in the second chip region adjacent to the region where the density is less than the density threshold, and a first region in the second chip region where the density is greater than or equal to the density threshold, can be determined.

[0147] Since the density of poly and AA in regions with a density less than the density threshold is low, achieving local density uniformity requires that the density of poly and AA in their surrounding regions also be low. Because the density of the reference cell array is low, density transformation is not necessary for the reference cell array in the second region. Conversely, since the density of poly and AA in regions with a density greater than or equal to the density threshold is high, achieving local density uniformity requires that the density of poly and AA in their surrounding regions also be high. Because the density of the reference cell array is low, achieving high-density local uniformity is not possible. Therefore, density transformation can be performed on the reference cell array in the first region to obtain a density-transformed cell array, thereby adjusting the local density uniformity of the chip structure.

[0148] In other embodiments, the density of the cell array located in the second region can also be varied so that the density of poly and AA in the cell array after density variation matches the density of poly and AA in the region where the density is less than the density threshold.

[0149] Because the density of AA and poly in the reference cell array is low, placing the reference cell array near the region where the density of the gate and active regions in the first chip region is less than the density threshold can improve the density uniformity of this region. Conversely, because the density of AA and poly in the non-reference cell array is high, placing the reference cell array near the region where the density of the gate and active regions in the first chip region is greater than or equal to the density threshold can improve the density uniformity of this region. Thus, by filling cell arrays with different AA and poly densities, the local density uniformity of the chip structure is improved.

[0150] In an optional embodiment, the second virtual cell array is obtained by splicing together a preset number of cell structures; then, in step S355 above, the density transformation processing of the cell array located in the first region to obtain a density-transformed cell array may include:

[0151] The splicing line of at least two consecutively spliced ​​unit structures is grown in a second direction by a second preset distance to obtain an initial gate.

[0152] The initial gate is compressed in the first direction to obtain the target gate.

[0153] Determine the centerline of the candidate gate included in two adjacent unit structures in the at least two consecutively spliced ​​unit structures.

[0154] The active region is defined by the distance between the center lines as the length and the width of the active region included in the unit structure as the width.

[0155] A target active region is generated in the active region to obtain a cell array that has undergone density transformation.

[0156] The preset number of unit structures include at least two consecutively spliced ​​unit structures, the candidate gate is the gate of two adjacent unit structures that is closer to the target gate, the target active region intersects with the target gate, and the second preset distance is half the width of the gate included in the unit structure.

[0157] In this embodiment, the splicing line of at least two consecutively spliced ​​unit structures can be used as the initial position, and a second preset distance can be grown in a second direction to obtain an initial gate. Optionally, the second preset distance is half the width of the gate included in the unit structure. Then, the initial gate is compressed in a first direction so that the length of the compressed gate is equal to the length of the gate included in the unit structure, to obtain a target gate. After obtaining the target gate, the gates of two adjacent unit structures that are close to the target gate can be identified as candidate gates, and the center line of the candidate gates included in the two adjacent unit structures can be determined. The active region is determined with the distance between the center lines as the length and the width of the active region included in the unit structure as the width. A target active region is generated in the active region, and the target active region intersects with the target gate, thereby realizing the transformation of the density of poly and AA in the second unit array to obtain a unit array with density transformation processing.

[0158] It should be noted that the number of at least two consecutively spliced ​​unit structures can be set according to actual application needs, and this application embodiment does not make a specific limitation on this.

[0159] By generating the target gate by growing the splicing line a second preset distance in the second direction and compressing it in the first direction, the generation difficulty of the target gate can be reduced and the generation efficiency of the target gate can be improved, thereby reducing the pattern layout time and the process complexity of the pattern layout. The process with lower complexity also improves the flexibility of designing the local density uniformity of the pattern layout. Furthermore, by determining the active region region with the distance between the center lines as the length and the width of the active region included in the unit structure as the width, and generating the target active region in the active region region, the generation difficulty of the target active region can be reduced and the generation efficiency of the target active region can be improved, thereby reducing the pattern layout time and the process complexity of the pattern layout. The process with lower complexity also improves the flexibility of designing the local density uniformity of the pattern layout.

[0160] Figure 17 This is a schematic diagram illustrating a transformation of the density of a cell array according to an exemplary embodiment, such as... Figure 17 As shown in Figure 'a', assuming the reference cell array is obtained by splicing together 6 cell structures, a preset number of reference cell arrays can be inserted into the second chip region. Next, the densities of the active region and gate in the first chip region are determined. Based on the densities of the active region and gate, regions in the first chip region where the density of the gate and active region is less than a density threshold (i.e., low-density regions) and regions in the first chip region where the density of the gate and active region is greater than or equal to the density threshold (i.e., high-density regions) are determined.

[0161] Since the second region is close to the low-density region in the first chip region, the density of the first cell array located in the second region can be maintained, or the density of the first cell array in the second region can be slightly increased to match the low-density region. For example, "slightly increasing the density of the first cell array in the second region" can be: dividing two consecutive cell structures in the first cell array into a group and performing a density transformation.

[0162] Since the first region is close to the high-density region in the first chip region, the second cell array located in the first region can be subjected to density transformation processing to match the high-density region. For example, a plurality of cell structures in the second cell array (e.g., Figure 17 The six unit structures are grouped together and subjected to density transformation, i.e., each splicing line is grown a second preset distance in a second direction to obtain an initial gate; the initial gate is compressed in the first direction to obtain a target gate; the center line of the candidate gates included in two adjacent unit structures in the at least two consecutively spliced ​​unit structures is determined; the active region is determined with the distance between the center lines as the length and the width of the active region included in the unit structure as the width, and the target active region is generated in the active region to obtain the unit array after density transformation, i.e., the desired active region is obtained. Figure 17 b in the text.

[0163] It should be noted that the method embodiments of this application and the structural embodiments described above belong to the same inventive concept.

[0164] This application also provides an electronic device that includes the chip structure described in any of the above embodiments.

[0165] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0166] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A unit structure, characterized in that, It includes a cell boundary, an active region, and a predetermined number of gates. The active region and the predetermined number of gates are located within the cell boundary. Each gate extends along a first direction and intersects with the active region. The distance between the center line of each gate in the first direction and the boundary of the target cell is greater than or equal to the distance between the center lines of two adjacent gates in the first direction. A space for accommodating a new gate is formed between each gate and the boundary of the target cell. The boundary of the target cell is a boundary that is close to each gate and parallel to the first direction.

2. The unit structure according to claim 1, characterized in that, The distance between the center line of each gate in the first direction and the boundary of the target unit is a preset number of times the distance between the center lines of two adjacent gates in the first direction; A space is formed between each of the gates and the boundary of the target cell to accommodate a target number of new gates, the target number being a number corresponding to a preset multiple, the preset multiple being an integer multiple greater than or equal to 1.

3. The unit structure according to claim 2, characterized in that, The space is used to accommodate a new gate when the distance between the center line of each gate in the first direction and the boundary of the target cell is equal to the distance between the center lines of two adjacent gates in the first direction.

4. The unit structure according to any one of claims 1 to 3, characterized in that, The preset number of gates is two, the number of active regions is one, and the two gates intersect with the one active region.

5. A unit array, characterized in that, The unit array includes a predetermined number of unit structures as described in any one of claims 1 to 4, the predetermined number of unit structures are arranged along a second direction, and adjacent unit structures are spliced ​​together with the corresponding target unit boundary as the splicing line, the second direction being perpendicular to the first direction.

6. The cell array according to claim 5, characterized in that, A target gate is provided around the splicing line of at least two consecutively spliced ​​unit structures, and the center line of the target gate is the splicing line of the spliced ​​unit structures. The preset number of unit structures includes at least two consecutively spliced ​​unit structures.

7. The cell array according to claim 6, characterized in that, A target active region is formed between the center lines of the candidate gates in two adjacent unit structures, and the target active region intersects with the target gate; The candidate gate is the gate closest to the target gate in two adjacent unit structures.

8. A chip structure, characterized in that, It includes a first chip area and a second chip area, wherein the first chip area includes a system-on-a-chip and the second chip area is provided with the cell array as described in claim 5; The position of the cell array in the second chip region is determined based on the density of the gate and active regions in the first chip region.

9. The chip structure according to claim 8, characterized in that, At least two consecutively spliced ​​unit structures are surrounded by a target gate, the center line of which is the splicing line of the unit structures. The unit array with the target gate is located in the first region of the second chip region. At least two consecutively spliced ​​unit structures are not surrounded by a target gate, and the unit array without the target gate is located in the second region of the second chip region. The first region is located near the region in the first chip region where the density of the gate and active regions is greater than or equal to the density threshold, and the second region is located near the region in the first chip region where the density of the gate and active regions is less than the density threshold.

10. A method for generating a unit structure, characterized in that, The generation method is used to generate the unit structure as described in any one of claims 1 to 4, the method comprising: An initial cell structure is provided; the initial cell structure includes an initial cell boundary, an active region, and a preset number of gates; the active region and the preset number of gates are located within the cell boundary, each gate extends along a first direction, and each gate intersects with the active region; The initial unit boundary is extended along the second direction by a first preset distance to obtain the unit boundary, thereby generating the unit structure; Wherein, the second direction is perpendicular to the first direction, and the first preset distance is greater than or equal to 1 / 2 the distance between the center lines of two adjacent gates in the first direction.

11. A method for generating a cell array, characterized in that, The generation method is used to generate the cell array as described in claim 5, the method comprising: Provides a preset number of unit structures; A predetermined number of the unit structures are arranged along the second direction, and adjacent unit structures are spliced ​​together with the corresponding target unit boundary as the splicing line to obtain the unit array.

12. The generation method according to claim 11, characterized in that, After obtaining the cell array, the method further includes: The splicing line of at least two consecutively spliced ​​unit structures is grown a second preset distance in the second direction to obtain an initial gate; The initial gate is compressed in a first direction to obtain the target gate; The preset number of unit structures includes at least two consecutively spliced ​​unit structures, the center line of the target gate is the splicing line of the spliced ​​unit structures, and the second preset distance is half the width of the gate included in the unit structure.

13. The generation method according to claim 12, characterized in that, After compressing the initial gate in a first direction to obtain the target gate, the method further includes: Determine the center line of the candidate gates in two adjacent unit structures; The active region is defined by the distance between the center lines as the length and the width of the active region included in the unit structure as the width. Generate a target active region within the active region; Wherein, the candidate gate is the gate closest to the target gate in two adjacent unit structures, and the target active region intersects with the target gate.

14. A method for generating a chip structure, characterized in that, The generation method is used to generate the chip structure according to claim 8, the chip structure including a first chip region and a second chip region, wherein the first chip region is provided with a system-on-a-chip, and the generation method includes: Insert the cell array as described in claim 5 into the second chip region; Determine the density of active regions and gates in the first chip region; Based on the density of the active region and the gate, the cell array is density transformed to obtain the density-transformed chip structure.

15. The generation method according to claim 14, characterized in that, The step of performing density transformation on the cell array based on the density of the active region and the gate includes: Based on the density of the active region and the gate, determine the regions in the first chip region where the density of the gate and the active region is less than the density threshold, and determine the regions in the first chip region where the density of the gate and the active region is greater than or equal to the density threshold. A first region in the second chip region that is close to the region with a density greater than or equal to the density threshold is determined, and a second region in the second chip region that is close to the region with a density less than the density threshold is determined; The density of the cell array located in the second region is maintained, and the density transformation process is performed on the cell array located in the first region to obtain a density-transformed cell array, so as to adjust the local density uniformity of the chip structure.

16. The generation method according to claim 15, characterized in that, The cell array located in the first region is obtained by splicing together a preset number of cell structures; the step of performing density transformation processing on the cell array located in the first region to obtain a density-transformed cell array includes: The splicing line of at least two consecutively spliced ​​unit structures is grown in a second direction by a second preset distance to obtain an initial gate; The initial gate is compressed in the first direction to obtain the target gate; Determine the center line of the candidate gate included in two adjacent unit structures in the at least two consecutively spliced ​​unit structures; The active region is defined by the distance between the center lines as the length and the width of the active region included in the unit structure as the width. A target active region is generated in the active region to obtain a cell array that has undergone density transformation. The preset number of unit structures include at least two consecutively spliced ​​unit structures, the candidate gate is the gate of two adjacent unit structures that is closer to the target gate, the target active region intersects with the target gate, and the second preset distance is half the width of the gate included in the unit structure.

17. An electronic device, characterized in that, The electronic device includes the chip structure as described in claim 8 or 9.

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