Integrated device and method of forming integrated device

Abstract

Some embodiments relate to an integrated device comprising: a substrate comprising a first doped region; the interconnection structure is located on the substrate and comprises a plurality of wiring layers and through hole layers; a first lower contact layer extending between the substrate and the interconnect structure; a first bonding layer over the interconnect structure; a first upper contact layer extending between the interconnect structure and the first bonding layer; and a capacitor in the interconnect structure, where the capacitor extends over the plurality of wiring layers and an uppermost wiring layer of the via layer. The embodiment of the invention also relates to a method for forming the integrated device.

Description

Technical Field

[0001] This application relates to integrated devices and methods for forming integrated devices. Background Technology

[0002] Integrated circuits (ICs) with image sensors are widely used in modern electronic devices such as cameras and mobile phones. Capacitors are used to store electrical charge in the circuit. The capacitors used within pixel circuits are limited by the dimensional constraints based on the lateral dimensions of the pixel circuit and the height of the surrounding interconnect structures. Summary of the Invention

[0003] One aspect of this application relates to an integrated device, comprising: a substrate including a first doped region; an interconnect structure located on the substrate and including a plurality of wiring layers and a plurality of via layers; a first lower contact layer extending between the substrate and the interconnect structure; a first bonding layer located above the interconnect structure; a first upper contact layer extending between the interconnect structure and the first bonding layer; and a capacitor located in the interconnect structure, wherein the capacitor includes: a bottom electrode having a bottom surface connected to the bottom surface of the first doped region, a top electrode extending above the top wiring layer of the plurality of wiring layers, and an insulating layer separating the bottom electrode from the top electrode.

[0004] Another aspect of this application relates to an integrated device comprising: a first substrate; a capacitor located above the first substrate and including a bottom electrode and a top electrode; a first bonding layer located above the capacitor; a second bonding layer bonded to the first bonding layer; a first lower contact layer connected to the first substrate and flush with the bottom electrode; a first upper contact layer connected to the first bonding layer and flush with the top electrode; and a low-k layer surrounding the capacitor and extending from the first lower contact layer to the first upper contact layer.

[0005] Another aspect of this application relates to a method of forming an integrated device, comprising: forming a doped region on a substrate; forming an interconnect structure on the substrate surrounded by a first plurality of interlayer dielectric layers; forming an opening extending through the first plurality of interlayer dielectric layers; filling the opening with a low-k layer; forming a capacitor within the low-k layer, the capacitor extending above the uppermost wiring layer of the interconnect structure; and forming a first bonding layer, the first bonding layer including a first bonding structure electrically connected to the capacitor.

[0006] This application also relates to enhanced capacitors for image sensors. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] FIG. 1A , FIG. 1B , FIG. 1C , FIG. 1D ,and FIG. 1E Cross-sectional views of some embodiments of a capacitor extending between a first lower contact layer at a substrate and a first upper contact layer at a first bonding layer are shown.

[0009] FIG. 2A , FIG. 2B , FIG. 2C ,and FIG. 2D It shows having FIGS. 1A-1D The image sensor portion of the capacitor embodiment shown in the figure is a cross-sectional view.

[0010] FIG. 3A and FIG. 3B Cross-sectional views of some embodiments of an image sensor in a dual-wafer stack configuration having capacitors located on a first wafer or a second wafer are shown respectively;

[0011] FIGS. 4A-19B This illustrates a structure extending from the first doped region to the first upper contact layer, formed between the first bonding layer and the interconnect structure. FIG. 1A and FIG. 1B A series of cross-sectional views of some embodiments of the capacitor method;

[0012] FIGS. 20A-31B This illustrates a structure extending from a first lower contact layer to a first upper contact layer, formed between the first bonding layer and the interconnect structure. FIG. 1C and FIG. 1D A series of cross-sectional views of some embodiments of the capacitor method;

[0013] FIGS. 32-43 The first upper contact layer formed between the first bonding layer and the interconnect structure is shown. FIG. 1E A series of cross-sectional views of some embodiments of the capacitor method;

[0014] FIG. 44 Flowcharts illustrating some embodiments of a method for forming a capacitor extending between a first lower contact layer at a substrate and a first upper contact layer at a first bonding layer are shown. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to readily describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] It should be understood that in this written specification and the following claims, the terms "first," "second," "third," etc., are merely general identifiers used to facilitate the description of differences between different elements in the drawings or a series of drawings. In themselves, these terms do not imply any temporal order or structural proximity of these elements, nor are they intended to describe corresponding elements in different illustrated and / or unshown embodiments. For example, a "first dielectric layer" described in conjunction with the first drawing may not necessarily correspond to a "first dielectric layer" described in conjunction with another drawing, and may not necessarily correspond to a "first dielectric layer" in embodiments not shown.

[0018] An image sensor includes a pixel array having multiple photodetectors and multiple pixel circuits connected to the photodetectors. The multiple pixel circuits include a floating diffusion node, a transfer transistor extending between the floating diffusion node and the photodetectors, a reset transistor having source / drain terminals connected to the floating diffusion node, and an output stage connected to the floating diffusion node. One or more capacitors are included in the pixel circuits to enhance charge retention at different stages of reading the acquired signal and transmitting it to an image signal processor circuit.

[0019] In some embodiments, the image sensor spans multiple substrates bonded together by a bonding layer. For example, in some embodiments, a reset transistor and an output stage are located on a first substrate, while a photodetector and a floating diffusion node are located within a second substrate connected to the first substrate via metal-to-metal and dielectric-to-dielectric bonding. The floating diffusion node is connected to the output stage via metal bonding pads within the first bonding layer. One or more capacitors are formed on the first or second substrate. In some embodiments, an application-specific integrated circuit (ASIC) for interpreting signals received from the output stage is located on a third substrate connected to the back side of the first substrate.

[0020] Some pixel circuits have capacitors confined between the lowest and highest wiring layers of an interconnect structure, allowing the capacitors to be electrically connected to the pixel circuit. Reducing the pixel circuit size provides higher resolution images and smaller cameras for integrated devices. Simultaneously, bonding multiple substrates together reduces the number of wiring layers used in the interconnect structures on the first and second substrates, as the pixel circuit uses paths extending between the first and second interconnect structures to form the same paths previously formed in a single interconnect structure. The reduced pixel size decreases the lateral dimension available for the pixel circuit capacitors, and the use of multiple interconnect structures forming capacitors within either the first or second interconnect structure reduces the available height. The reduction in both the lateral and vertical dimensions of the available space for back-end line (BEOL) devices in both the first and second interconnect structures reduces the available space for capacitors within the pixel circuit, leading to decreased capacitance and performance degradation as miniaturization continues. Therefore, capacitors with increased capacitance are ideal without increasing the pixel circuit size.

[0021] This invention provides a capacitor extending from a first lower contact layer on a substrate to a first upper contact layer at a first bonding layer of a first substrate or a second substrate. The bottom electrode of the capacitor is directly electrically connected to a contact in the first lower contact layer, or directly electrically connected to a first doped region of the substrate, extending to be flush with or beyond the bottom surface of the lowest wiring layer of the interconnect structure. Additionally, the top electrode of the capacitor is directly connected to a contact in the first upper contact layer extending between the first bonding layer and the interconnect structure, or directly connected to the first bonding layer. The top surface of the top electrode extends above the top surface of the top wiring layer of the interconnect structure. Increasing the height of the capacitor by extending beyond the upper and lower limits of the interconnect structure increases the capacitance of the capacitor and improves the charge retention of the pixel circuitry. The increased charge retention improves the conversion gain and reduces readout noise of the image sensor, while simultaneously reducing costs by omitting unnecessary metal layers in the manufacturing process.

[0022] FIG. 1A , FIG. 1B , FIG. 1C , FIG. 1D ,and FIG. 1E Cross-sectional views 100a, 100b, 100c, 100d, and 100e show some embodiments of a capacitor extending between a first lower contact layer at a substrate and a first upper contact layer at a first bonding layer.

[0023] like FIG. 1A As shown in cross-sectional view 100a, capacitor 104 is located above first substrate 102. Capacitor 104 has a top electrode 106, a bottom electrode 108, and an insulating layer 110 (e.g., a high-k dielectric material or silicon dioxide) extending between the top electrode 106 and the bottom electrode 108. A first plurality of semiconductor devices 109 are located on the first substrate 102. In some embodiments, the first plurality of semiconductor devices 109 are or include transistor devices (e.g., planar FETs, FinFETs, gate-all-around (GAA) devices, etc.). The bottom electrode 108 has a base portion 108a extending to a first lower contact layer 111 and electrically connected to a first doped region 112 in the first substrate 102. The bottom electrode also includes a sleeve portion 108b extending upward from the base portion 108a, and a collar portion 108c including an upper laterally outwardly extending portion of the sleeve portion 108b. In a further embodiment, the bottom electrode 108 extends to the first substrate 102 and is electrically connected to the first doped region 112 through direct contact. In some embodiments, the top electrode 106 extends to the first upper contact layer 114 and is electrically connected to the first bonding layer 116. In a further embodiment, the top electrode 106 includes a protrusion 106a present within the sleeve portion 108b of the bottom electrode, and a collar portion 106b extending laterally outward from the upper portion of the protrusion 106a and extending upward out of the sleeve portion 108b. The top electrode 106 is electrically connected to the first bonding layer 116 through a first upper contact 118 of the first upper contact layer 114.

[0024] A first interconnect structure 120 extends between and connects to a first lower contact layer 111 and a first upper contact layer 114. The first interconnect structure 120 includes: a plurality of wiring layers 122, including a lowest wiring layer 124 and a highest wiring layer 126; and one or more via layers 128 extending between the plurality of wiring layers 122. Wiring in the highest wiring layer 126 is electrically connected to a first bonding layer 116 via contacts in the first upper contact layer 114. Wiring in the lowest wiring layer 124 is electrically connected to a plurality of first semiconductor devices 109 via contacts in the first lower contact layer 111. In some embodiments, a protrusion 106a of the top electrode 106 has an uppermost portion located above the upper surface of the highest wiring layer 126 and a lowermost portion located directly below the bottom surface of the via layer 128 below the highest wiring layer 126.

[0025] Capacitor 104 extends below the bottom surface of the lowest wiring layer 124 and above the top surface of the highest wiring layer 126. In some embodiments, the bottom electrode 108 has a bottom surface extending through the first lower contact layer 111 to the first doped region 112. This extension significantly increases the height of capacitor 104 compared to embodiments where the top electrode 106 is connected to a wiring layer of multiple wiring layers 122 via contacts within one or more via layers 128, or compared to embodiments where the bottom electrode 108 is connected to a wiring layer of multiple wiring layers 122. Since the capacitance of a capacitor depends on the surface area of ​​the electrodes, the increased capacitor height increases the capacitance, resulting in greater charge retention in the pixel circuitry, improved conversion gain, and lower readout noise in the image sensor.

[0026] Furthermore, omitting the metal layer between capacitor 104 and the first bonding layer 116 can reduce the lateral footprint of the pixel circuitry. For example, in embodiments where an additional metal layer is formed above interconnect structure 120 and below the first bonding layer 116, the additional metal layer is thicker than the wiring layers of interconnect structure 120. The increased thickness of the additional metal layer imposes design limitations on how close the wiring layers of the additional metal layer can be to each other. Therefore, removing the additional metal layer and using a metal layer of similar thickness can reduce the size limitations of the pixel circuitry, thereby increasing the flexibility of image sensor design and reducing the lateral footprint of individual pixel circuitry.

[0027] like FIG. 1BAs shown in cross-sectional view 100b, in some embodiments, the bottom electrode 108 of the capacitor 104 extends to the first lower contact 130 of the first lower contact layer 111. In some embodiments, the lowermost surface of the bottom electrode 108 is flush with the uppermost surface of the first lower contact 130 of the first lower contact layer 111. The first lower contact 130 extends beyond the outer edge of the bottommost surface of the bottom electrode 108. A plurality of interlayer dielectric (ILD) layers 132 surround the first lower contact layer 111 and the first interconnect structure 120. A low-k layer 134 extends over the plurality of ILD layers 132 and surrounds the outer sidewalls of the capacitor 104. The low-k layer 134 spaces the sidewalls of the capacitor from the plurality of ILD layers 132. The low-k layer extends from the first lower contact layer 111 to the first upper contact layer 114. In some embodiments, the plurality of ILD layers 132 are porous and trap moisture during the manufacturing process. The low-k layer 134 spaces the capacitor from the plurality of ILD layers 132 to mitigate any unreliability that may be caused by trapped moisture during the manufacture of the capacitor 104. In some embodiments, the outer wall of the low-k layer 134 is directly above (e.g., aligned with) the outer wall of the first lower contact 130.

[0028] In some embodiments, the uppermost surface of the top electrode 106 is covered with a covering oxide layer 136, a silicon oxynitride (SiON) layer 138, and a silicon nitride (Si3N4) layer 140. The combination of layers covering the top electrode 106 mitigates damage to the top electrode 106 caused by multiple etching processes used to form the openings of the first upper contact layer 114 and the first bonding layer 116.

[0029] like FIG. 1C As shown in cross-sectional view 100c, in some embodiments, the top electrode 106 of capacitor 104 extends to and is in direct contact with the first bonding structure 142 of the first bonding layer 116. In some embodiments, the first bonding structure 142 has a first thickness t1, and a second bonding structure 144, which is directly located on and electrically connected to the interconnect structure 128, has a second thickness t2, which is greater than the first thickness t1. In a further embodiment, the top electrode 106 is covered by a silicon nitride (Si3N4) layer 140, while the covering oxide layer is omitted (see [link to documentation]). FIG. 1B 136) and silicon oxynitride layer (see ... FIG. 1B (138). The reduced number of etching steps extending to capacitor 104 results in a reduced amount of insulating layer used to cover top electrode 106. In some embodiments, top electrode 106 has an uppermost surface located above the bottom surface of the first bonding structure 142 of the first bonding layer 116. In other embodiments, the uppermost surface of top electrode 106 is flush with the bottom surface of the first bonding structure 142 of the first bonding layer 116.

[0030] like FIG. 1D As shown in cross-sectional view 100d, in some embodiments, capacitor 104 directly contacts both the first engagement structure 142 and the first lower contact 130. FIG. 1E As shown in cross-sectional view 100e, in some embodiments, capacitor 104 is connected between the first bonding structure 142 and the wiring 148 of the interconnect structure 120. In a further embodiment, wiring 148 is part of the uppermost wiring layer of the interconnect structure 120. Connecting the capacitor between the first bonding structure 142 and the wiring 148 in the interconnect structure 120 creates a structure with different capacitances based on the wiring layer in which wiring 148 is located, while retaining the advantage of omitting a metal layer between capacitor 104 and the first bonding layer 116.

[0031] FIG. 2A , FIG. 2B , FIG. 2C ,and FIG. 2D It shows having FIGS. 1A-1D Cross-sectional views 200a, 200b, 200c, and 200d show portions of the image sensor in the capacitor embodiment. FIG. 2A , FIG. 2B , FIG. 2C ,and FIG. 2D A description will be provided simultaneously.

[0032] In some embodiments, the second substrate 202 is mechanically connected to the first substrate 102 via a second bonding layer 204 connected to the first bonding layer 116. The second bonding layer 204 is mechanically bonded to the first bonding layer 116 via a combination of metal-to-metal bonding and oxide-to-oxide bonding. The bonding interface layer 203 of the first bonding layer 116 is bonded to the second oxide capping layer 205 of the second bonding layer 204.

[0033] The second interconnect structure 206 extends between the second substrate 202 and the second bonding layer 204. The second interconnect structure 206 includes a second plurality of wiring layers 208 and a second plurality of via layers 210, the second plurality of via layers 210 extending between and connecting the wiring of the second plurality of wiring layers 208. A second upper contact layer 212 connects the bonding structure of the second bonding layer 204 to the second interconnect structure 206. The second interconnect structure 206 is electrically connected to the conductive path of the first interconnect structure 120 via the first bonding layer 116 and the second bonding layer 204, such that the conductive path extends into the second interconnect structure 206, and increases the number of wiring layers and via layers for routing conductive paths within the circuit.

[0034] The second plurality of semiconductor devices 214 are located on the second substrate 202. In some embodiments, the second plurality of semiconductor devices 214 are or include transistor devices (e.g., planar FETs, FinFETs, gate-all-around (GAA) devices, etc.). The second lower contact layer 216 connects the second plurality of semiconductor devices 214 to the second interconnect structure 206. In some embodiments, a photodetector 218 is located in the second substrate 202, and the combination of the photodetector 218, the second plurality of semiconductor devices 214, the conductive path, the capacitor 104, and the first plurality of semiconductor devices 109 forms a pixel circuit.

[0035] In some embodiments, a deep trench isolation (DTI) structure 220 surrounds the photodetector 218. The DTI structure 220 isolates the photodetector 218 from other surrounding photodetectors 219, mitigating crosstalk and interference caused by the proximity of different photodetectors. A plurality of color filters 222 extend above the photodetectors 218, 219. In some embodiments, the plurality of color filters 222 have different colors (e.g., red, blue, and green), which are organized in a repeating pattern on the image sensor and separated by an isolation grid 224 to reduce interference between pixels.

[0036] In some embodiments, a plurality of microlenses 226 are distributed on a second substrate 202. The plurality of microlenses 226 are positioned and fabricated to guide light into a photodetector. For example, in some embodiments, an aperture smaller than that of an image sensor is used to isolate the image to be recorded by the image sensor. In this embodiment, the plurality of microlenses 226 are configured to guide light radially downward from the aperture into the pixel. To this end, microlenses near the outer edge of the image sensor are configured to guide light toward the photodetector at a narrower angle (e.g., a first angle measured from the bottom of the second substrate 202) rather than at a wider angle (e.g., a second angle measured from the bottom of the second substrate, where the second angle is greater than the first angle) than toward the photodetector 218. The plurality of microlenses 226 may have rectangular, triangular, convex, stepped, or any other cross-sectional profile.

[0037] FIG. 3A and FIG. 3B Cross-sectional views 300a and 300b show some embodiments of an image sensor in a dual-wafer stack configuration having capacitors located on a first wafer or a second wafer, respectively.

[0038] like FIG. 3A As shown in cross-sectional view 300a, in some embodiments, FIGS. 1A-1DThe capacitor 104 is used in a dual-wafer stacked image sensor configuration, wherein a first plurality of semiconductor devices 109 on a first substrate 102 form an image processing circuit (ISP) 302, and a second plurality of semiconductor devices 214 on a second substrate 202 form a pixel circuit 304. In some embodiments, a portion of the first plurality of semiconductor devices 109 on the first substrate is also part of the pixel circuit 304. In some embodiments, the capacitor 104 in the dual-wafer stacked image sensor configuration extends from a first upper contact layer 114 to a first lower contact layer 111. In other embodiments, the capacitor 104 in a three-wafer stacked image sensor configuration extends from a first upper contact layer 114 to a first lower contact layer 111, wherein the ISP 302 is located on a third substrate (not shown), and the pixel circuit 304 has components on the first substrate 102 and the second substrate 202. FIG. 3B As shown in cross-sectional view 300b, in some embodiments, capacitor 104 extends between a second lower contact layer 216 and a second upper contact layer 212 on a second substrate 202 in a dual-wafer stack configuration.

[0039] FIGS. 4A-19B This illustrates a structure extending from the first doped region to the first upper contact layer, formed between the first bonding layer and the interconnect structure. FIG. 1A and FIG. 1B A series of cross-sectional views 400a-1900b show some embodiments of the capacitor method. Although FIGS. 4A-19B The actions are described as a series of actions, but it should be understood that these actions are not limiting; the order of the actions may be changed in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted, either wholly or in part.

[0040] like FIG. 4A As shown in cross-sectional view 400a, a first doped region 112, a first plurality of semiconductor devices 109, and a first interconnect structure 120 are formed over a first substrate 102. The first doped region 112 includes an n-type or p-type dopant at a higher concentration than the surrounding first substrate 102. In some embodiments, the first doped region is formed by one or more doping processes, implantation processes, etc. In some embodiments, the first plurality of semiconductor devices 109 are formed by one or more implantation processes (to form source / drain regions within the first substrate 102), multiple deposition processes (to form gate dielectrics, gate terminals, and spacers on the first substrate 102), and multiple etching processes (to pattern the gate dielectrics, gate terminals, and spacers). In some embodiments, photolithography is used to form one or more mask layers to protect portions of the first substrate 102 and the gate terminals during the implantation and patterning processes.

[0041] In some embodiments, one or more damascene processes are used to form the first interconnect structure 120 and the first lower contact layer. Specifically, an ILD layer 402 of a plurality of ILD layers 132 is formed over a first substrate 102. Multiple openings are formed in the ILD layer 402 by patterning a mask layer and etching the ILD layer 402 based on the pattern of the mask layer. The mask layer is then removed before depositing a metal layer to fill the multiple openings. A planarization process (e.g., chemical mechanical planarization (CMP)) is then used to remove portions of the metal layer above the ILD layer 402. An etch stop layer 404 is formed over the ILD layer 402, and this process is repeated one or more times to form the first interconnect structure 120. In some embodiments, a dual damascene process is used to form one or more wiring layers and via layers of the first interconnect structure 120. In a further embodiment, a second insulating layer 406 is formed over the etch stop layer 404 before performing the dual damascene process to better protect the underlying wiring layers.

[0042] In some embodiments, the gate terminals of the first plurality of semiconductor devices 109, the contacts of the first lower contact layer 111, the plurality of wiring layers 122, and the plurality of via layers 128 are or include conductive materials, such as copper, nickel, aluminum, tungsten, titanium, titanium nitride, metal alloys, combinations of the above materials, etc. In some embodiments, the ILD layer 132 is or includes an insulating material, such as silicon oxide (SiO2), etc. In some embodiments, the etch stop layer 404 is or includes an insulating material, such as silicon carbide (SiC), etc. In some embodiments, the second insulating layer 406 is or includes tetraethyl orthosilicate (TEOS), etc. In some embodiments, a contact etch stop layer (CESL) 408 is formed on the first substrate 102 before forming the plurality of ILD layers 132. FIG. 4B As shown in cross-sectional view 400b, in some embodiments, the first lower contact 130 is formed simultaneously with other contacts forming the first lower contact layer 111. The first figure of each drawing number (e.g., FIGS. 5A-19A The diagram (represented by "A") continues the tradition of... FIG. 4A The embodiment represented, in which the first lower contact 130 is omitted. The second figure of each figure number (e.g., FIGS. 5B-19B The diagram (represented by "B") continues the tradition of... FIG. 4B The represented embodiment, wherein the capacitor (see FIG. 1B 104) is connected to the first lower contact 130.

[0043] like FIG. 5A and FIG. 5BAs shown in cross-sectional views 500a and 500b, a first mask layer 502 is formed over a plurality of ILD layers 132. In some embodiments, the first mask layer 502 is or includes photoresist and is patterned using photolithography. The first mask layer 502 is patterned to have a low-k layer (see [reference]) that extends through the plurality of ILD layers 132. FIG. 1B The opening corresponding to the extension of 134).

[0044] like FIG. 5A As shown, after the formation of the first mask layer 502, a first etching process 504 is performed, etching through multiple ILD layers 132 to CESL 408. FIG. 5B As shown, a first etching process 504 etches through multiple ILD layers 132 to the first lower contact 130. In some embodiments, the first etching process 504 is or includes dry etching, etc. The first etching process 504 creates a first opening 506 extending through the multiple ILD layers 132. The first opening 506 corresponds to an opening in the first mask layer 502. The first mask layer 502 is then removed.

[0045] like FIG. 6A and FIG. 6B As shown in cross-sectional views 600a and 600b, a low-k layer 134 is formed over a first substrate 102. The low-k layer 134 fills the first opening 506 and extends over the upper surfaces of the plurality of ILD layers 132. In some embodiments, the low-k layer 134 is or includes a low-k insulating material (e.g., a material having a small dielectric constant relative to silicon dioxide (SiO2), such as porous silicon dioxide (SiO2), organosilicon glass (OSG), etc. In some embodiments, the low-k layer 134 is formed using one or more of physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. In some embodiments, after the low-k layer 134 is formed, a planarization process (e.g., CMP process) is used to remove portions of the low-k layer 134, such that the low-k layer 134 has a substantially flat upper surface.

[0046] like FIG. 7A and FIG. 7B As shown in cross-sectional views 700a and 700b, a second mask layer 702 is formed over a plurality of ILD layers 132. In some embodiments, the second mask layer 702 is or includes photoresist and is patterned using photolithography. The second mask layer 702 is patterned to have a shape similar to that of a capacitor (see...). FIG. 1A The 104) extends through the corresponding opening of the lower k layer 134.

[0047] like FIG. 7AAs shown, after the formation of the second mask layer 702, a second etching process 704 is performed, etching through the low-k layer 134 and CESL 408. FIG. 7B As shown, the second etching process 704 etches to the first lower contact 130. In some embodiments, the second etching process 704 is or includes dry etching, etc. The second etching process 704 creates a second opening 706 extending through the low-k layer 134 and CESL 408. The second opening 706 corresponds to an opening in the second mask layer 702. The second mask layer 702 is then removed.

[0048] like FIG. 8A and FIG. 8B As shown in cross-sectional views 800a and 800b, a first conformal metal layer 802, a first conformal high-k insulating layer 804, and a second conformal metal layer 806 are formed above the first substrate 102. The first conformal metal layer 802, the first conformal high-k insulating layer 804, and the second conformal metal layer 806 together fill the second opening 706 and extend above the upper surface of the low-k layer 134. In some embodiments, the first conformal metal layer 802 and the second conformal metal layer 806 are or include conductive metals, such as titanium (Ti), titanium nitride (TiN), copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), tantalum (Ta), tantalum nitride (TaN), metal alloys, combinations of the above materials, etc. In some embodiments, the first conformal high-k insulating layer 804 is or includes a high-k insulating material (e.g., an insulating material having a high dielectric constant relative to silicon dioxide (SiO2),) such as hafnium oxide (HfO2), hafnium silicate (HfSiO4), zirconium dioxide (ZrO2), zirconium silicate (ZrSiO4), aluminum oxide (Al2O3), etc. In some embodiments, one or more of PVD, ALD, CVD, etc., are used to form the first conformal metal layer 802, the first conformal high-k insulating layer 804, and the second conformal metal layer 806. FIG. 8A As shown, the first conformal metal layer 802 extends to the first substrate 102. FIG. 8B As shown, the first conformal metal layer 802 extends to the first lower contact 130.

[0049] like FIG. 9A and FIG. 9BAs shown in cross-sectional views 900a and 900b, a first conformal covering oxide layer 902, a conformal silicon oxynitride (SiON) layer 904, and a first conformal silicon nitride (Si3N4) layer 906 are formed over the second conformal metal layer 806. The first conformal covering oxide layer 902 is or includes an oxide, such as silicon oxide (SiO2). In some embodiments, one or more of PVD, ALD, CVD, etc., are used to form the first conformal covering oxide layer 902, the conformal silicon oxynitride (SiON) layer 904, and the first conformal silicon nitride (Si3N4) layer 906.

[0050] like FIG. 10A and FIG. 10B As shown in cross-sectional views 1000a and 1000b, in some embodiments, a third mask layer 1002 is formed over the first conformal silicon nitride (Si3N4) layer (see 906 in FIG. 9). The third mask layer 1002 is patterned using capacitor top metal (CTM) mask lithography and has a pattern corresponding to the lateral dimensions of the top electrode 106. Additionally, a third etching 1004 is performed on the substrate to remove portions of the second conformal metal layer (see 806 in FIG. 8), the first conformal cover oxide layer (see 902 in FIG. 9), the conformal silicon oxynitride (SiON) layer (see 904 in FIG. 9), and the first conformal silicon nitride (Si3N4) layer (see 906 in FIG. 9). After the third etching 1004, the top electrode 106, the cover oxide layer 136, the silicon oxynitride (SiON) layer 138, and the silicon nitride (Si3N4) layer 140 remain on the first substrate 102. In embodiments that include a third mask layer 1002, the third mask layer 1002 is subsequently removed.

[0051] like FIG. 11A and FIG. 11B As shown in cross-sectional views 1100a and 1100b, a second conformal overlay oxide layer 1102 and a second conformal silicon nitride (Si3N4) layer 1104 are formed above the exposed surfaces of the silicon nitride (Si3N4) layer 140 and the first conformal high-k insulating layer 804. In some embodiments, the second conformal overlay oxide layer 1102 comprises the same material as the overlay oxide layer 136. In some embodiments, one or more of PVD, ALD, CVD, etc., are used to form the second conformal overlay oxide layer 1102 and the second conformal silicon nitride (Si3N4) layer 1104.

[0052] like FIG. 12A and FIG. 12BAs shown in cross-sectional views 1200a and 1200b, a blanket etching 1201 is performed over the first substrate 102. The blanket etching 1201 removes portions of the second conformal overlay oxide layer (see 1102 in FIG. 11), the second conformal silicon nitride (Si3N4) layer (see 1104 in FIG. 11), the first conformal high-k insulating layer (see 804 in FIG. 8), and the first conformal metal layer (see 802 in FIG. 8). After the blanket etching 1201, the bottom electrode 108, the insulating layer 110, the oxide spacer 1202, and the silicon nitride (Si3N4) spacer 1204 remain on the first substrate 102, and the low-k layer 134 is exposed. In some embodiments, the low-k layer 134 is partially etched such that the low-k layer 34 has an upper surface recessed below the collar portion 108c of the bottom electrode 108. The capacitor 104 remains on the first substrate 102.

[0053] like FIG. 13A and FIG. 13B As shown in cross-sectional views 1300a and 1300b, an additional low-k material is deposited above capacitor 104, and a low-k layer 134 extends above capacitor 104. One or more of PVD, ALD, CVD, etc., are used to form the additional low-k material. In some embodiments, after depositing the additional low-k material, a planarization process (e.g., CMP process) is performed to remove portions of the low-k layer 134, forming a substantially flat upper surface.

[0054] like FIG. 14A and FIG. 14B As shown in cross-sectional views 1400a and 1400b, a second etch stop layer 1402, an oxide filler layer 1404, and a bonding interface layer 203 are deposited over a low-k layer 134. In some embodiments, the second etch stop layer 1402 is or includes an insulating material other than silicon dioxide (SiO2), such as silicon nitride (Si3N4), silicon oxynitride (SiON), etc. In some embodiments, the oxide filler layer 1404 is or includes silicon dioxide (SiO2), a low-k oxide material, etc. In some embodiments, the bonding interface layer 203 is or includes an insulating material, such as silicon oxynitride (SiON), etc. In some embodiments, one or more of PVD, ALD, CVD, etc., are used to form the second etch stop layer 1402, the oxide filler layer 1404, and the bonding interface layer 203.

[0055] like FIG. 15A and FIG. 15BAs shown in cross-sectional views 1500a and 1500b, a fourth mask layer 1502 is formed above the bonding interface layer 203. In some embodiments, the fourth mask layer 1502 is or includes photoresist and is patterned using photolithography. The fourth mask layer 1502 is patterned to have a contact layer with the first upper contact layer (see...). FIG. 1A The opening corresponding to the contact element of (114).

[0056] After forming the fourth mask layer 1502, a fourth etching process 1504 is performed, etching through the bonding interface layer 203, the oxide filling layer 1404, the second etch stop layer 1402, and the low-k layer 134. In some embodiments, the fourth etching process 1504 is or includes dry etching, etc. The fourth etching process 1504 creates a third opening 1506. The third opening 1506 is connected to the opening in the fourth mask layer 1502 and the first upper contact layer (see...). FIG. 1A The positions of the contacts (114) correspond to those of the contacts. Then the fourth mask layer 1502 is removed.

[0057] like FIG. 16A and FIG. 16B As shown in cross-sectional views 1600a and 1600b, a fifth mask layer 1602 is formed above the bonding interface layer 203 and in the third opening 1506. In some embodiments, the fifth mask layer 1602 is or includes photoresist and is patterned using photolithography. The fifth mask layer 1602 is patterned to have an interface with the first bonding layer (see...). FIG. 1A The opening corresponding to the bonding structure of the 116). In some embodiments, a portion of the fifth mask layer 1602 forms an insulating plug 1604, which reduces the amount of material removed in the lower part of the third opening 1506 during subsequent etching processes.

[0058] like FIG. 17A and FIG. 17B As shown in cross-sectional views 1700a and 1700b, after forming the fifth mask layer 1602, a fifth etching process 1702 is performed. The fifth etching process 1702 enlarges the third opening 1506 and removes portions of the bonding interface layer 203 and the insulating plug 1604. In some embodiments, the fifth etching process 1702 is or includes dry etching, etc. After the fifth etching process, the first upper contact element (see...) is... FIG. 1A The third opening 1506, corresponding to the position of (118), extends to the top electrode 106 and connects with the first upper contact layer (see...). FIG. 1B The third opening 1506, corresponding to the location of other contacts in (114), extends to the uppermost fabric line 126 of the first interconnect structure 120. Additionally, for the first bonding layer (see...) FIG. 1C The upper part of the third opening corresponding to the bonding structure of 116) is etched. Then the fifth mask layer 1602 is removed.

[0059] like FIG. 18A and FIG. 18B As shown in cross-sectional views 1800a and 1800b, a third conformal metal layer 1802 is formed above the bonding interface layer 203. The third conformal metal layer is or includes a conductive material, such as copper, nickel, aluminum, tungsten, titanium, titanium nitride, metal alloys, or combinations thereof. The third conformal metal layer 1802 extends into the third opening 1506 and above the upper surface of the bonding interface layer 203. In some embodiments, one or more of PVD, ALD, CVD, etc., are used to form the third conformal metal layer 1802.

[0060] like FIG. 19A and FIG. 19B As shown in cross-sectional views 1900a and 1900b, a planarization process (e.g., CMP process) is performed. The planarization process removes a portion of the third conformal metal layer (see 1802 in FIG. 18) above the bonding interface layer 203. After the planarization process, the bonding structure of the first bonding layer 116 and the contacts of the first upper contact layer 114 remain on the first substrate 102.

[0061] FIGS. 20A-31B This illustrates a structure extending from a first lower contact layer to a first upper contact layer, formed between the first bonding layer and the interconnect structure. FIG. 1C and FIG. 1D A series of cross-sectional figures 2000a-3100b show some embodiments of the capacitor method. Although FIGS. 20A-31B The actions are described as a series of actions, but it should be understood that these actions are not limiting; the order of the actions may be changed in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted, either wholly or in part.

[0062] like FIG. 20A and FIG. 20BAs shown in cross-sectional views 2000a and 2000b, a low-k layer 134 and a third etch stop layer 2002 are formed over a first substrate 102. The low-k layer 134 fills the first opening 506 (shown in dashed lines) and extends over the upper surfaces of the plurality of ILD layers 132. In some embodiments, the low-k layer 134 is or comprises a low-k insulating material, such as porous silica (SiO2), organosilicon glass (OSG), etc. In some embodiments, the low-k layer 134 is formed using one or more of physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. In some embodiments, after the low-k layer 134 is formed, a planarization process (e.g., CMP process) is used to remove portions of the low-k layer 134, such that the low-k layer 134 has a substantially flat upper surface. Then, the third etch stop layer 2002 is formed over the substantially flat upper surface of the low-k layer 134. In some embodiments, the third etch stop layer 2002 is or includes silicon nitride, silicon oxynitride, etc.

[0063] like FIG. 21A and FIG. 21B As shown in cross-sectional views 2100a and 2100b, a second mask layer 702 is formed above the third etch stop layer 2002. In some embodiments, the second mask layer 702 is or includes photoresist and is patterned using photolithography. The second mask layer 702 is patterned to have a shape similar to that of a capacitor (see...). FIG. 1C The 104) extends through the corresponding opening of the lower k layer 134.

[0064] like FIG. 21A As shown, after the formation of the second mask layer 702, a second etching process 704 is performed, etching through the third etch stop layer 2002, the low-k layer 134, and CESL 408. FIG. 21B As shown, the second etching process 704 etches through the third etch stop layer 2002 and the low-k layer 134 to the first lower contact 130. In some embodiments, the second etching process 704 is or includes dry etching, etc. The second etching process 704 creates a second opening 706 extending through the low-k layer 134. The second opening 706 corresponds to an opening in the second mask layer 702. The second mask layer 702 is then removed.

[0065] like FIG. 22A and FIG. 22BAs shown in cross-sectional views 2200a and 2200b, a first conformal metal layer 802, a first conformal high-k insulating layer 804, and a second conformal metal layer 806 are formed above the third etch stop layer 2002. The first conformal metal layer 802, the first conformal high-k insulating layer 804, and the second conformal metal layer 806 together fill the second opening 706 and extend above the upper surface of the third etch stop layer 2002. In some embodiments, the first conformal metal layer 802 and the second conformal metal layer 806 are or include conductive metals, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), metal alloys, combinations of the above materials, etc. In some embodiments, the first conformal high-k insulating layer 804 is or includes a high-k insulating material, such as hafnium oxide (HfO2), hafnium silicate (HfSiO4), zirconium dioxide (ZrO2), zirconium silicate (ZrSiO4), aluminum oxide (Al2O3), etc. In some embodiments, one or more of PVD, ALD, CVD, etc., are used to form the first conformal metal layer 802, the first conformal high-k insulating layer 804, and the second conformal metal layer 806.

[0066] After forming the first conformal metal layer 802, the first conformal high-k insulating layer 804, and the second conformal metal layer 806, a fourth etch stop layer 2202 is formed over the second conformal metal layer 806. In some embodiments, the fourth etch stop layer 2202 is made of the same material as the third etch stop layer 2002 and is formed using one of PVD, ALD, CVD, etc.

[0067] like FIG. 23A and FIG. 23B As shown in cross-sectional views 2300a and 2300b, in some embodiments, a third mask layer 1002 is formed over the fourth etch stop layer 2202. The third mask layer 1002 is patterned using a capacitor top metal (CTM) mask lithography process and has a pattern corresponding to the lateral dimensions of the top electrode 106. Additionally, a third etch 1004 is performed on the fourth etch stop layer 2202 to remove the second conformal metal layer (see 806 in FIG. 8) and a portion of the fourth etch stop layer 2202. After the third etch 1004, the top electrode 106 and a portion of the fourth etch stop layer 2202 remain on the first substrate 102. In embodiments including the third mask layer 1002, the third mask layer 1002 is subsequently removed.

[0068] like FIG. 24A and FIG. 24BAs shown in cross-sectional views 2400a and 2400b, a second conformal overlay oxide layer 1102 is formed above the exposed surfaces of the fourth etch stop layer 2202 and the first conformal high-k insulating layer 804. In some embodiments, the second conformal overlay oxide layer 1102 comprises the same material as the overlay oxide layer 136. In some embodiments, one or more of PVD, ALD, CVD, etc., are used to form the second conformal overlay oxide layer 1102.

[0069] like FIG. 25A and FIG. 25B As shown in cross-sectional views 2500a and 2500b, a blanket etching 1201 is performed over the first substrate 102. The blanket etching 1201 removes portions of the fourth etch stop layer 2202, the first conformal high-k insulating layer (see 804 in FIG. 8), and the first conformal metal layer (see 802 in FIG. 8). After the blanket etching 1201, the bottom electrode 108, the insulating layer 110, and the oxide spacer 1202 remain on the first substrate 102, and the third etch stop layer 2002 is exposed. The capacitor 104 remains on the first substrate 102.

[0070] like FIG. 26A and FIG. 26B As shown in cross-sectional views 2600a and 2600b, an oxide filler layer 1404 and a bonding interface layer 203 are deposited above the third etch stop layer 2002. In some embodiments, the oxide filler layer 1404 is or includes silicon dioxide (SiO2), a low-k oxide material, etc. In some embodiments, the bonding interface layer 203 is or includes an insulating material, such as silicon oxynitride (SiON). In some embodiments, one or more of PVD, ALD, CVD, etc., are used to form the oxide filler layer 1404 and the bonding interface layer 203.

[0071] like FIG. 27A and FIG. 27B As shown in cross-sectional views 2700a and 2700b, a fourth mask layer 1502 is formed above the bonding interface layer 203. In some embodiments, the fourth mask layer 1502 is or includes photoresist and is patterned using photolithography. The fourth mask layer 1502 is patterned to have a contact layer with the first upper contact layer (see...). FIG. 1C The opening corresponding to the contact element of (114).

[0072] After the fourth mask layer 1502 is formed, a fourth etching process 1504 is performed, etching through the bonding interface layer 203, the oxide filling layer 1404, the third etch stop layer 2002, and the low-k layer 134. In some embodiments, the fourth etching process 1504 is or includes dry etching, etc. The fourth etching process 1504 creates a third opening 1506. The third opening 1506 is in contact with the opening in the fourth mask layer 1502 and the first upper contact layer (see...). FIG. 1C The positions of the contacts (114) correspond to those of the contacts. Then the fourth mask layer 1502 is removed.

[0073] like FIG. 28A and FIG. 28B As shown in cross-sectional views 2800a and 2800b, a fifth mask layer 1602 is formed above the bonding interface layer 203 and in the third opening 1506. In some embodiments, the fifth mask layer 1602 is or includes photoresist and is patterned using photolithography. The fifth mask layer 1602 is patterned to have an interface with the first bonding layer (see...). FIG. 1A The opening corresponding to the bonding structure of the 116). In some embodiments, a portion of the fifth mask layer 1602 forms an insulating plug 1604, which reduces the amount of material removed in the lower part of the third opening 1506 during subsequent etching processes.

[0074] like FIG. 29A and FIG. 29B As shown in cross-sectional views 2900a and 2900b, after forming the fifth mask layer 1602, a fifth etching process 1702 is performed. The fifth etching process 1702 enlarges the third opening 1506 and creates a fourth opening 2902, removing portions of the bonding interface layer 203 and the insulating plug 1604. In some embodiments, the fifth etching process 1702 is or includes dry etching, etc. After the fifth etching process, the first bonding structure (see...) is... FIG. 1C The fourth opening 2902, corresponding to position 142, extends through the silicon nitride (Si3N4) layer 140 to the top electrode 106. This is in contrast to the first upper contact layer (see...). FIG. 1A The third opening 1506, corresponding to the position of the contact in (114), extends to the uppermost wiring layer 126 of the first interconnect structure 120. Additionally, for the first bonding layer (see...) FIG. 1C The upper part of the third opening corresponding to the bonding structure of 116) is etched. Then the fifth mask layer 1602 is removed.

[0075] like FIG. 30A and FIG. 30BAs shown in cross-sectional views 3000a and 3000b, a third conformal metal layer 1802 is formed above the bonding interface layer 203. The third conformal metal layer 1802 is or includes a conductive material, such as copper, nickel, aluminum, tungsten, titanium, titanium nitride, metal alloys, or combinations thereof. The third conformal metal layer 1802 extends into the third opening 1506 and the fourth opening 2902, and above the upper surface of the bonding interface layer 203. In some embodiments, one or more of PVD, ALD, CVD, etc., are used to form the third conformal metal layer 1802.

[0076] like FIG. 31A and FIG. 31B As shown in cross-sectional views 3100a and 3100b, a planarization process (e.g., CMP process) is performed. The planarization process removes a portion of the third conformal metal layer (see 1802 in FIG. 18) above the bonding interface layer 203. After the planarization process, the bonding structures of the first bonding layer 116 (e.g., the first bonding structure 142 and the second bonding structure 144) and the contacts of the first upper contact layer 114 remain on the first substrate 102.

[0077] FIGS. 32-43 This illustrates a structure extending from a first lower contact layer to a first upper contact layer, formed between the first bonding layer and the interconnect structure. FIG. 1E A series of cross-sectional views 3200-4300 show some embodiments of the capacitor method. Although FIGS. 32-43 The actions are described as a series of actions, but it should be understood that these actions are not limiting; the order of the actions may be changed in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted, either wholly or in part.

[0078] like FIG. 32 As shown in cross-sectional view 3200, in some embodiments, a third etch stop layer 2002 is formed on the ILD layer 132. This is because a capacitor will subsequently be formed (see...). FIG. 1E The 104th layer is formed on top of the interconnect structure 120, thus omitting the etching of the ILD layer 132 and the low-k layer (see [link]). FIG. 1A The deposition of layer 134). A third etch stop layer 2002 is formed above the substantially flat upper surface of the ILD layer 132. In some embodiments, the third etch stop layer 2002 is or includes silicon nitride, silicon oxynitride, etc. In some embodiments, the third etch stop layer 2002 is formed using a deposition process such as PVD, ALD, CVD, etc.

[0079] like FIG. 33As shown in cross-sectional view 3300, a second mask layer 702 is formed over the third etch stop layer 2002 and a plurality of ILD layers 132. In some embodiments, the second mask layer 702 is or includes photoresist and is patterned using photolithography. The second mask layer 702 is patterned to have a shape similar to that of a capacitor (see...). FIG. 1A The openings corresponding to the extensions in the multiple ILD layers 132 (104) are also present.

[0080] After the second mask layer 702 is formed, a second etching process 704 is performed, etching through the plurality of ILD layers 132 to the wiring 148. In some embodiments, the second etching process 704 is or includes dry etching, etc. The second etching process 704 creates a second opening 706 extending through the plurality of ILD layers 132 to the wiring 148. The second opening 706 corresponds to an opening in the second mask layer 702. The second mask layer 702 is then removed.

[0081] like FIG. 34 As shown in cross-sectional view 3400, a first conformal metal layer 802, a first conformal high-k insulating layer 804, and a second conformal metal layer 806 are formed above the third etch stop layer 2002. The first conformal metal layer 802, the first conformal high-k insulating layer 804, and the second conformal metal layer 806 together fill the second opening 706 and extend above the upper surface of the third etch stop layer 2002. In some embodiments, the first conformal metal layer 802 and the second conformal metal layer 806 are or include conductive metals, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), metal alloys, combinations of the above materials, etc. In some embodiments, the first conformal high-k insulating layer 804 is or includes a high-k insulating material, such as hafnium oxide (HfO2), hafnium silicate (HfSiO4), zirconium dioxide (ZrO2), zirconium silicate (ZrSiO4), aluminum oxide (Al2O3), etc. In some embodiments, one or more of PVD, ALD, CVD, etc., are used to form the first conformal metal layer 802, the first conformal high-k insulating layer 804, and the second conformal metal layer 806.

[0082] After forming the first conformal metal layer 802, the first conformal high-k insulating layer 804, and the second conformal metal layer 806, a fourth etch stop layer 2202 is formed over the second conformal metal layer 806. In some embodiments, the fourth etch stop layer 2202 is made of the same material as the third etch stop layer 2002 and is formed using one of PVD, ALD, CVD, etc.

[0083] like FIG. 35As shown in cross-sectional view 3500, in some embodiments, a third mask layer 1002 is formed over the fourth etch stop layer 2202. The third mask layer 1002 is patterned using a capacitor top metal (CTM) mask lithography process and has a pattern corresponding to the lateral dimensions of the top electrode 106. Additionally, a third etch 1004 is performed on the fourth etch stop layer 2202 to remove the second conformal metal layer (see 806 in FIG. 8) and a portion of the fourth etch stop layer 2202. After the third etch 1004, the top electrode 106 and a portion of the fourth etch stop layer 2202 remain on the first substrate 102. In embodiments including the third mask layer 1002, the third mask layer 1002 is subsequently removed.

[0084] like FIG. 36 As shown in cross-sectional view 3600, a second conformal overlay oxide layer 1102 is formed above the exposed surfaces of the fourth etch stop layer 2202 and the first conformal high-k insulating layer 804. In some embodiments, the second conformal overlay oxide layer 1102 includes an overlay oxide layer (see...) FIG. 1B The same material as 136). In some embodiments, one or more of PVD, ALD, CVD, etc., are used to form the second conformal covering oxide layer 1102.

[0085] like FIG. 37 As shown in cross-sectional view 3700, a blanket etching 1201 is performed over the first substrate 102. The blanket etching 1201 removes portions of the fourth etch stop layer 2202, the first conformal high-k insulating layer (see 804 in FIG. 8), and the first conformal metal layer (see 802 in FIG. 8). After the blanket etching 1201, the bottom electrode 108, the insulating layer 110, and the oxide spacer 1202 remain on the first substrate 102, and the third etch stop layer 2002 is exposed. The capacitor 104 remains on the first substrate 102.

[0086] like FIG. 38 As shown in cross-sectional view 3800, an oxide filler layer 1404 and a bonding interface layer 203 are deposited above the third etch stop layer 2002. In some embodiments, the oxide filler layer 1404 is or includes silicon dioxide (SiO2), a low-k oxide material, etc. In some embodiments, the bonding interface layer 203 is or includes an insulating material, such as silicon oxynitride (SiON), etc. In some embodiments, one or more of PVD, ALD, CVD, etc., are used to form the oxide filler layer 1404 and the bonding interface layer 203.

[0087] like FIG. 39As shown in cross-sectional view 3900, a fourth mask layer 1502 is formed above the bonding interface layer 203. In some embodiments, the fourth mask layer 1502 is or includes photoresist and is patterned using photolithography. The fourth mask layer 1502 is patterned to have a contact layer with the first upper contact layer (see...). FIG. 1C The opening corresponding to the contact element of (114).

[0088] After the fourth mask layer 1502 is formed, a fourth etching process 1504 is performed, etching through the bonding interface layer 203, oxide filling layer 1404, third etch stop layer 2002, and ILD layer 132 above the interconnect structure 120. In some embodiments, the fourth etching process 1504 is or includes dry etching, etc. The fourth etching process 1504 creates a third opening 1506. The third opening 1506 is connected to the opening in the fourth mask layer 1502 and the first upper contact layer (see...). FIG. 1C The positions of the contacts (114) correspond to those of the contacts. Then the fourth mask layer 1502 is removed.

[0089] like FIG. 40 As shown in the cross-sectional view 4000, a fifth mask layer 1602 is formed above the bonding interface layer 203 and in the third opening 1506. In some embodiments, the fifth mask layer 1602 is or includes photoresist and is patterned using photolithography. The fifth mask layer 1602 is patterned to have an interface with the first bonding layer (see...). FIG. 1A The opening corresponding to the bonding structure of the 116). In some embodiments, a portion of the fifth mask layer 1602 forms an insulating plug 1604, which reduces the amount of material removed in the lower part of the third opening 1506 during subsequent etching processes.

[0090] like FIG. 41 As shown in cross-sectional view 4100, after the formation of the fifth mask layer 1602, a fifth etching process 1702 is performed. The fifth etching process 1702 enlarges the third opening 1506 and creates a fourth opening 2902, removing the bonding interface layer 203 and the insulating plug (see...). FIG. 40 The portion of 1604). In some embodiments, the fifth etching process 1702 is or includes dry etching, etc. After the fifth etching process, the first bonding structure (see 1604) is joined. FIG. 1C The fourth opening 2902, corresponding to position 142, extends through the silicon nitride (Si3N4) layer 140 to the top electrode 106. This is in contrast to the first upper contact layer (see...). FIG. 1A The third opening 1506, corresponding to the position of the contact in (114), extends to the uppermost wiring layer 126 of the first interconnect structure 120. Additionally, for the first bonding layer (see...) FIG. 1CThe upper part of the third opening corresponding to the bonding structure of 116) is etched. Then the fifth mask layer 1602 is removed.

[0091] like FIG. 42 As shown in cross-sectional view 4200, a third conformal metal layer 1802 is formed above the bonding interface layer 203. The third conformal metal layer 1802 is or includes a conductive material, such as copper, nickel, aluminum, tungsten, titanium, titanium nitride, metal alloys, or combinations thereof. The third conformal metal layer 1802 extends into the third opening 1506 and the fourth opening 2902, and above the upper surface of the bonding interface layer 203. In some embodiments, one or more of PVD, ALD, CVD, etc., are used to form the third conformal metal layer 1802.

[0092] like FIG. 43 As shown in cross-sectional view 4300, a planarization process (e.g., CMP process) is performed. The planarization process removes a portion of the third conformal metal layer (see 1802 in FIG. 18) above the bonding interface layer 203. After the planarization process, the bonding structures of the first bonding layer 116 (e.g., the first bonding structure 142 and the second bonding structure 144) and the contacts of the first upper contact layer 114 remain on the first substrate 102.

[0093] FIG. 44 A flowchart 4400 illustrates some embodiments of a method for forming a capacitor extending between a first lower contact layer at a substrate and a first upper contact layer at a first bonding layer. Although the methods and other methods shown and / or described herein are illustrated as a series of actions or events, it should be understood that the invention is not limited to the shown order or actions. Therefore, in some embodiments, these actions may be performed in a different order than shown, and / or may be performed simultaneously. Additionally, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed either at individual times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.

[0094] At position 4402, a doped region is formed on the substrate. For example, at... FIGS. 4A-4B Examples illustrating this step can be found in the drawing.

[0095] At position 4404, a first lower contact layer is formed above the substrate. For example, in FIGS. 4A-4B Examples illustrating this step can be found in the drawing.

[0096] At position 4406, an interconnect structure surrounded by a plurality of first interlayer dielectric (ILD) layers is formed on the substrate. For example, in FIGS. 4A-4BExamples illustrating this step can be found in the drawing.

[0097] At 4408, an opening is formed that extends through the first plurality of ILD layers to the first lower contact layer. For example, in FIGS. 5A-5B Examples illustrating this step can be found in the drawing.

[0098] At 4410, fill the opening with a low-k layer. For example, at... FIGS. 6A-6B Examples illustrating this step can be found in the drawing.

[0099] At 4412, a capacitor is formed within the low-k layer, extending above the topmost wiring layer of the interconnect structure. For example, in FIGS. 7A-12B Examples illustrating this step can be found in the drawing.

[0100] At position 4414, a first upper contact layer is formed on the interconnect structure and flush with the capacitor. For example, in FIGS. 15A-19B Examples illustrating this step can be found in the drawing.

[0101] At 4416, a first bonding layer is formed, the first bonding layer including a first bonding structure electrically connected to the capacitor. For example, in FIGS. 15A-19B Examples illustrating this step can be found in the drawing.

[0102] Some embodiments relate to an integrated device comprising: a substrate including a first doped region; an interconnect structure on the substrate including a plurality of wiring layers and via layers; a first lower contact layer extending between the substrate and the interconnect structure; a first bonding layer above the interconnect structure; a first upper contact layer extending between the interconnect structure and the first bonding layer; and a capacitor located in the interconnect structure, wherein the capacitor extends above the uppermost wiring layer of the plurality of wiring layers and via layers. In some embodiments, the capacitor includes a bottom electrode with a bottom surface extending through the first lower contact layer to the first doped region. In some embodiments, the integrated device further includes: a bottom electrode of the capacitor; and a first lower contact of the first lower contact layer electrically connecting the bottom electrode to the first doped region. In some embodiments, the capacitor further includes a top electrode with a top surface flush with or above the bottom surface of the first bonding structure of the first bonding layer. In some embodiments, the integrated device further includes: a top electrode of the capacitor; and a first upper contact of the first upper contact layer electrically connecting the top electrode to the first bonding structure of the first bonding layer. In some embodiments, the integrated device further includes a low-k layer extending from a first lower contact layer to a first upper contact layer and having an outer wall that contacts a plurality of interlayer dielectric (ILD) layers. In some embodiments, the plurality of ILD layers surround the first lower contact layer and the outer wall of the interconnect structure, and the low-k layer extends to the first lower contact layer through openings in the plurality of ILD layers.

[0103] Some embodiments relate to an integrated device comprising: a substrate including a first doped region; an interconnect structure located on the substrate and including a plurality of wiring layers and a plurality of via layers; a first lower contact layer extending between the substrate and the interconnect structure; a first bonding layer located above the interconnect structure; a first upper contact layer extending between the interconnect structure and the first bonding layer; and a capacitor located in the interconnect structure, wherein the capacitor includes: a bottom electrode having a bottom surface connected to the bottom surface of the first doped region, a top electrode extending above the uppermost wiring layer of the plurality of wiring layers, and an insulating layer separating the bottom electrode from the top electrode. In some embodiments, the bottom electrode includes: a base portion having a base portion contacting the bottom surface of the first doped region, and a sleeve portion extending upward from the base portion; and wherein the top electrode includes a protrusion disposed within the sleeve portion of the bottom electrode, the protrusion having: an uppermost portion located above the upper surface of the uppermost wiring layer, and a lowermost portion located directly below the bottom surface of the via layer below the uppermost wiring layer. In some embodiments, the integrated device further includes: a first lower contact of the first lower contact layer, the first lower contact electrically connecting the bottom electrode to the first doped region. In some embodiments, the top electrode has an uppermost surface flush with the bottom surface of the first bonding structure of the first bonding layer, or located above the bottom surface of the first bonding structure of the first bonding layer. In some embodiments, the integrated device further includes: a first upper contact of the first upper contact layer, the first upper contact electrically connecting the top electrode to the first bonding structure of the first bonding layer. In some embodiments, the integrated device further includes: a low-k layer extending from the first lower contact layer to the first upper contact layer, the low-k layer having an outer wall contacting a plurality of interlayer dielectric layers. In some embodiments, the plurality of interlayer dielectric layers surround the interconnect structure and the outer wall of the first lower contact layer, and the low-k layer extends to the first lower contact layer through openings in the plurality of interlayer dielectric layers.

[0104] Other embodiments relate to an integrated device including: a first substrate; a capacitor located above the first substrate, the capacitor including a bottom electrode and a top electrode; a first bonding layer located above the capacitor; a second bonding layer bonded to the first bonding layer; a first lower contact layer connected to the first substrate and flush with the bottom electrode; a first upper contact layer connected to the first bonding layer and flush with the top electrode; and a low-k layer surrounding the capacitor and extending from the first lower contact layer to the first upper contact layer. In some embodiments, the uppermost surface of the first lower contact layer is flush with the lowermost surface of the bottom electrode of the capacitor. In some embodiments, the lowermost surface of the first upper contact layer is flush with the lowermost surface of the bottom electrode of the capacitor. In some embodiments, the uppermost surface of a first lower contact of the first lower contact layer is flush with or above the lowermost surface of the bottom electrode of the capacitor. In some embodiments, the lowermost surface of the first upper contact layer is flush with or below the uppermost surface of the top electrode of the capacitor. In some embodiments, the integrated device further includes: a second substrate located above the first substrate, wherein a second bonding layer is located on the second substrate; a first interconnect structure extending between the first substrate and the first bonding layer and including a first plurality of wiring layers and a first plurality of via layers; and a second interconnect structure extending between the second substrate and the second bonding layer and including a second plurality of wiring layers and a second plurality of via layers; wherein a capacitor extends above the uppermost wiring layer of the first plurality of wiring layers. In some embodiments, the capacitor extends above the uppermost wiring layer of the first plurality of wiring layers, and the capacitor is connected to the second interconnect structure via the first bonding layer and the second bonding layer. In some embodiments, the integrated device further includes: a plurality of interlayer dielectric (ILD) layers surrounding the first interconnect structure, wherein a low-k layer spaces the plurality of ILD layers from the capacitor.

[0105] Other embodiments relate to a method of forming an integrated device, including: forming a doped region on a substrate; forming an interconnect structure on the substrate surrounded by a first plurality of interlayer dielectric (ILD) layers; forming an opening extending through the first plurality of ILD layers; filling the opening with a low-k layer; forming a capacitor within the low-k layer, the capacitor extending above the uppermost wiring layer of the interconnect structure; and forming a first bonding layer, the first bonding layer including a first bonding structure electrically connected to the capacitor. In some embodiments, bonding electrodes and shielding electrodes form a capacitor electrically connected from an output node to a floating diffusion node. In some embodiments, the method further includes: forming a first lower contact layer on the substrate prior to forming the interconnect structure, wherein the capacitor extends to the first lower contact layer. In some embodiments, forming the first lower contact layer includes forming a first lower contact electrically connected to the doped region, wherein the opening is directly above the first lower contact, and the capacitor contacts the first lower contact. In some embodiments, the low-k layer extends to the bottom surface of the bottommost ILD layer of the plurality of ILD layers, and the capacitor extends to the substrate. In some embodiments, the method further includes forming an upper contact layer while forming a first bonding layer, wherein the uppermost surface of the top electrode of the capacitor is flush with or above the upper contact layer. In some embodiments, a first upper contact of the upper contact layer electrically connects the top electrode to the first bonding structure. In some embodiments, the uppermost surface of the top electrode is flush with the first bonding structure. In some embodiments, the method further includes bonding a second bonding layer on a second substrate to the first bonding structure using metal-to-metal bonding.

[0106] It should be understood that in this written specification and the following claims, the terms "first," "second," "third," etc., are merely general identifiers used to facilitate the description of differences between different elements in the drawings or a series of drawings. In themselves, these terms do not imply any temporal order or structural proximity of these elements, nor are they intended to describe corresponding elements in different illustrated and / or unshown embodiments. For example, a "first dielectric layer" described in conjunction with the first drawing may not necessarily correspond to a "first dielectric layer" described in conjunction with another drawing, and may not necessarily correspond to a "first dielectric layer" in embodiments not shown.

[0107] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. An integrated device, comprising: Substrate, including a first doped region; An interconnect structure is located on the substrate and includes multiple wiring layers and multiple via layers; A first lower contact layer extends between the substrate and the interconnect structure; A first bonding layer is located above the interconnect structure; A first upper contact layer extends between the interconnect structure and the first bonding layer; as well as A capacitor is located in the interconnect structure, wherein the capacitor includes: a bottom electrode having a bottom surface connected to the bottom surface of the first doped region, a top electrode extending above the top wiring layer of the plurality of wiring layers, and an insulating layer separating the bottom electrode from the top electrode.

2. The integrated device according to claim 1, wherein, The bottom electrode includes: a base portion having a bottom surface in contact with the first doped region, and a sleeve portion extending upward from the base portion; and The top electrode includes a protrusion disposed within the sleeve portion of the bottom electrode, the protrusion having: an uppermost portion located above the upper surface of the uppermost wiring layer, and a lowermost portion located directly below the bottom surface of the via layer below the highest wiring layer.

3. The integrated device according to claim 1, further comprising: The first lower contact of the first lower contact layer electrically connects the bottom electrode to the first doped region.

4. The integrated device according to claim 1, wherein, The top electrode has a surface that is flush with the bottom surface of the first bonding structure of the first bonding layer, or is located above the bottom surface of the first bonding structure of the first bonding layer.

5. The integrated device according to claim 1, further comprising: The first upper contact of the first upper contact layer electrically connects the top electrode to the first bonding structure of the first bonding layer.

6. The integrated device according to claim 1, further comprising: A low-k layer extends from the first lower contact layer to the first upper contact layer, and the low-k layer has an outer wall that contacts a plurality of interlayer dielectric layers.

7. The integrated device according to claim 6, wherein, The plurality of interlayer dielectric layers surround the outer wall of the interconnect structure and the first lower contact layer, and the low-k layer extends to the first lower contact layer through openings in the plurality of interlayer dielectric layers.

8. An integrated device, comprising: First substrate; A capacitor is located above the first substrate and includes a bottom electrode and a top electrode; A first bonding layer is located above the capacitor; A second bonding layer is bonded to the first bonding layer; A first lower contact layer is connected to the first substrate and is flush with the bottom electrode; A first upper contact layer is connected to the first bonding layer and is flush with the top electrode; as well as A low-k layer surrounds the capacitor and extends from the first lower contact layer to the first upper contact layer.

9. The integrated device according to claim 8, wherein, The uppermost surface of the first lower contact of the first lower contact layer is flush with or above the lowermost surface of the bottom electrode of the capacitor.

10. A method of forming an integrated device, comprising: Doped regions are formed on the substrate; An interconnect structure surrounded by a first plurality of interlayer dielectric layers is formed on the substrate; Forming an opening that extends through the first plurality of interlayer dielectric layers; The opening is filled with a low-k layer; A capacitor is formed within the low k layer, and the capacitor extends above the uppermost wiring layer of the interconnect structure. as well as A first bonding layer is formed, the first bonding layer including a first bonding structure electrically connected to the capacitor.

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