Low energy underlayer for room temperature physical vapor deposition of conductive features

Abstract

Embodiments of the present disclosure generally relate to methods of forming conductive features on a substrate. In one embodiment, the method includes forming a first conductive layer through physical vapor deposition (PVD) at an opening of a substrate. The thickness of the first conductive layer is less than 20 angstroms. The method further includes forming a second conductive layer on the first conductive layer through PVD. The first conductive layer and the second conductive layer are formed at a temperature of less than 50 DEG C. The method further includes annealing at least a portion of the first conductive layer and the second conductive layer.

Description

Technical Field

[0001] The embodiments disclosed herein generally relate to the formation of physical vapor deposition (PVD) films on a substrate in an electronic device manufacturing process, and particularly to apparatus and methods for depositing one or more film layers in features formed on a substrate. Background Technology

[0002] Conductive features grown using physical vapor deposition (PVD) techniques, such as tungsten-backed and padded processes, are fundamental to reducing contact resistance in midline (MOL) process steps. Existing tungsten-backed and padded processes include PVD tungsten deposition, wet etch removal of tungsten, and chemical vapor deposition (CVD) of tungsten to selectively deposit tungsten bottom-up or to completely fill MOL structures associated with gates, contact pads, conductive wiring, vias, etc. Achieving high bottom coverage with minimal overhang is a prerequisite for good gap filling. However, existing methods have several drawbacks.

[0003] For example, sputtering of high aspect ratio features (such as trenches) often results in disproportionate material buildup at the edges of the deposited feature. This excess material buildup creates overhangs, leading to reduced or pinched-off underbody coverage. Furthermore, PVD deposition of conductive materials (such as tungsten) often results in material penetration into the substrate. Therefore, after recycling (or a similar etching process), some of the conductive material mixes with the substrate, reducing the electrical properties of the conductive features formed on / within the substrate.

[0004] Therefore, there is an urgent need for improved technologies to form conductive features through PVD processes. Summary of the Invention

[0005] The embodiments disclosed herein generally relate to a method of forming a conductive feature on a substrate. In one embodiment, the method includes forming a first conductive layer at an opening in the substrate via physical vapor deposition (PVD). The thickness of the first conductive layer is less than 20 angstroms. The method further includes forming a second conductive layer on the first conductive layer via PVD. The first and second conductive layers are formed at a temperature below 50°C. The method further includes annealing at least a portion of the first and second conductive layers.

[0006] In another embodiment, the method includes forming a first conductive layer at an opening in the substrate via physical vapor deposition (PVD). The thickness of the first conductive layer is less than 20 angstroms. The method further includes forming a second conductive layer on the first conductive layer via PVD. The thickness of the second conductive layer is greater than 20 angstroms, and the first and second conductive layers are formed at a temperature below 50°C.

[0007] In another embodiment, the method includes forming a first conductive layer at an opening in the substrate using physical vapor deposition (PVD). The thickness of the first conductive layer is less than 20 angstroms. The method further includes forming a second conductive layer on the first conductive layer using PVD. The first and second conductive layers are formed at a temperature below 50°C. The method further includes depositing a third conductive layer on the second conductive layer using chemical vapor deposition (CVD). Attached Figure Description

[0008] To enable a detailed understanding of the features of this disclosure, a more specific description of the disclosure is provided below with reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of this disclosure and should not be considered as limiting its scope, as the disclosure may also include other equally effective embodiments.

[0009] Figure 1 A schematic plan view of a multi-chamber processing system according to an embodiment described herein is shown.

[0010] Figure 2 This is a cross-sectional view of the chamber according to the embodiment described herein.

[0011] Figure 3 A flowchart of a method for filling features with conductive material according to an embodiment described herein is shown.

[0012] Figures 4A-4F According to the embodiment described herein, a substrate is shown having an opening on which a conductive layer is deposited.

[0013] Figure 5 According to the embodiments described herein, the interface between the conductive material and the substrate is shown under different bias voltages.

[0014] Figure 6 According to the embodiments described herein, the bottom coverage of the trench structure is shown to vary with the bias voltage applied to the substrate.

[0015] Figure 7 According to the embodiments described herein, the remaining amount of tungsten in the tetraethoxysilane (TEOS) layer is shown as a function of processing temperature and substrate bias, the amount of which is measured by total reflected X-ray fluorescence (TXRF).

[0016] Figure 8 According to the embodiments described herein, the remaining amount of tungsten in the TEOS layer is shown as a function of substrate bias and the presence of the underlying layer, the amount of which is measured by TXRF.

[0017] Figure 9According to the embodiments described herein, the resistivity of a PVD tungsten layer deposited at 25°C and 325 mTorr is shown as a function of substrate bias.

[0018] Figure 10 According to the embodiments described herein, the resistivity of 40 to 50 angstroms PVD tungsten films after annealing at different temperatures for 10 seconds is shown.

[0019] For ease of understanding, the same element symbols have been used to identify the same elements in the figures where possible. Elements and features of certain embodiments may be advantageously incorporated into other embodiments without further explanation. Detailed Implementation

[0020] The embodiments disclosed herein generally relate to the process of performing physical vapor deposition (PVD) films on substrates in which features generated through electronic device manufacturing processes are formed. More specifically, the embodiments described herein provide methods and apparatus for improving the electrical properties of conductive features by reducing the mixing between the conductive features and the underlying layer (e.g., a dielectric layer) in which they are formed.

[0021] Example substrate processing system

[0022] Figure 1 This is a schematic top view of an example substrate processing system 100 (also referred to as a “processing platform”). According to the embodiments described herein, the substrate processing system 100 typically includes a device front-end module (EFEM) 102 for loading substrates into the processing system 100, a first load-locking chamber 104 connected to the EFEM 102, a transfer chamber 108 connected to the first load-locking chamber 104, and a plurality of other chambers connected to the transfer chamber 108 as described below. The EFEM 102 typically includes one or more robots 105 configured to transfer substrates from a front-opening unification chamber (FOUP) 103 to at least one first load-locking chamber 104 or a second load-locking chamber 106. Starting from the buffer portion 108A of the first load-locking chamber 104, and moving counterclockwise, the processing system 100 includes a first dedicated degassing chamber 109, a first pre-cleaning chamber 110, a first passage chamber 112, a second passage chamber 113, a second pre-cleaning chamber 114, a second degassing chamber 116, and a second load-locking chamber 106. The buffer portion 108A of the transfer chamber 108 includes a first robot 115 configured to transfer the substrate to each of the load-locking chambers 104, 106, the degassing chambers 109, 116, the pre-cleaning chambers 110, 114, and the passage chambers 112, 113.

[0023] The rear end portion 108B of the transfer chamber 108 includes a second robot 135 configured to transfer substrates to each of the processing chambers connected to the rear end portion 108B of the processing system 100 via chambers 112, 113. The processing chambers may include a first processing chamber 132, a second processing chamber 134, a third processing chamber 136, and a fourth processing chamber 138. Generally, processing chambers 132, 134, 136, and 138 may include at least one atomic layer deposition (ALD) chamber, a chemical vapor deposition (CVD) chamber, a physical vapor deposition (PVD) chamber, an etching chamber, a degassing chamber, an annealing chamber, and other types of semiconductor substrate processing chambers. In some embodiments, one or more of processing chambers 132, 134, 136, and 138 are PVD chambers configured similarly to the processing chamber 200 described below.

[0024] The buffer portion 108A and the rear portion 108B of the transfer chamber 108, as well as each chamber connected to the transfer chamber 108, can be maintained under vacuum. The term "vacuum" as used herein may refer to a pressure below 760 Torr, and will typically be maintained at a pressure close to 10⁻⁵ Torr (i.e., approximately 10⁻³ Pa). However, some high-vacuum systems may operate at pressures close to 10⁻⁷ Torr (i.e., approximately 10⁻⁵ Pa). In some embodiments, this vacuum is created using a roughing pump and / or turbomolecular pump connected to the transfer chamber 108 and one or more processing chambers (e.g., processing chambers 109-138). However, other types of vacuum pumps are also considered.

[0025] System controller 126, such as a programmable computer, is connected to processing system 100 to control one or more of its components. For example, system controller 126 may control the operation of processing chamber 200, which will be further described below. In operation, system controller 126 coordinates data acquisition and feedback from the various components to process within processing system 100.

[0026] The system controller 126 includes a programmable central processing unit (CPU) 126A, which can operate in conjunction with a memory 126B (e.g., non-volatile memory) and support circuitry 126C. The support circuitry 126C (e.g., cache, clock circuitry, input / output subsystem, power supply, and combinations thereof) is typically connected to the CPU 126A and to various components within the processing system 100.

[0027] In some embodiments, CPU 126A is a general-purpose computer processor for use in industrial environments, such as a programmable logic controller (PLC), for controlling various monitoring system components and subprocessors. The memory 126B connected to CPU 126A is non-transitory and is typically one of the readily available types of memory, such as random access memory (RAM), read-only memory (ROM), floppy disk drive, hard disk, or any other form of digital storage, local or remote.

[0028] Here, memory 126B exists in the form of a computer-readable storage medium containing instructions (e.g., non-volatile memory) that, when executed by CPU 126A, contribute to the operation of processing system 100. The instructions in memory 126A exist in the form of a program product, such as a program implementing the methods disclosed herein (e.g., an intermediate application, device software application, etc.). The program code may conform to one of many different programming languages. In one embodiment, this disclosure may be implemented as a program product stored on a computer-readable storage medium for use by a computer system. The program of the program product defines the functionality of the embodiments (including the methods described herein). For example, computer-readable storage media include, but are not limited to: (i) non-writable storage media (e.g., read-only memory devices within a computer, such as CD-ROM disks readable by a CD-ROM drive, flash memory, ROM chips, or any type of solid-state non-volatile semiconductor memory) on which information is permanently stored; and (ii) writable storage media (e.g., floppy disks within a disk drive or hard disk drive, or any type of solid-state random access semiconductor memory) on which modifiable information is stored. Such computer-readable storage media, when carrying instructions and directing the function of the methods described herein, constitute embodiments of this disclosure.

[0029] Processing chamber examples

[0030] Figure 2The illustrated processing chamber 200 includes an upper process assembly 208, a processing sleeve 250, and a substrate support base 220, all configured to process a substrate 205 placed in a central processing area 210. The processing sleeve 250 includes a processing sleeve shroud 260, a lower processing sleeve 265, and an isolation ring assembly 280. In the illustrated version, the processing chamber 200 is a sputtering chamber, also known as a PVD chamber, capable of depositing single or multiple composition materials from a target 235 onto the substrate 205. The processing chamber 200 can also be used to deposit aluminum, copper, nickel, platinum, hafnium, silver, chromium, gold, molybdenum, silicon, ruthenium, tantalum, tantalum nitride, tantalum carbide, titanium nitride, tungsten, tungsten nitride, lanthanum, alumina, lanthanum oxide, nickel-platinum alloys, and titanium, or combinations thereof. Such processing chambers are available from Applied Materials, Inc., located in Santa Clara, California. Other processing chambers, including those from other manufacturers, are also expected to be adapted to benefit from one or more embodiments described in this disclosure.

[0031] Processing chamber 200 includes a chamber body 201 having sidewalls 204, a bottom wall 206, and an upper process assembly 208 surrounding a central processing region 210 or plasma region. The chamber body 201 is typically made of a welded stainless steel sheet or a single block of aluminum. In one embodiment, the sidewalls are made of aluminum, and the bottom wall is made of stainless steel. The sidewalls 204 typically include a slit valve (not shown) to allow the substrate 205 to enter and exit the processing chamber 200. Elements in the upper process assembly 208 of the processing chamber 200, in conjunction with a processing sleeve shroud 260, a substrate support base 220, and a cover ring 270, confine the plasma formed in the processing region 210 to the area above the substrate 205.

[0032] A substrate support base 220 is supported from the bottom wall 206 of the chamber 200. During processing, the substrate support base 220 supports the deposition ring 270 and the substrate 205. The substrate support base 220 is connected to the bottom wall 206 of the chamber 200 via a lifting mechanism 222, which is designed to move the substrate support base 220 between an upper processing position and a lower transfer position. Furthermore, in the lower transfer position, a lifting pin 223 passes through the substrate support base 220 to maintain a distance between the substrate and the substrate support base 220, facilitating substrate exchange with a substrate transfer mechanism located outside the processing chamber 200, such as a single-blade robot (not shown). A bellows 224 is typically disposed between the substrate support base 220 and the bottom wall 206 of the chamber to isolate the processing area 210 from the interior of the substrate support base 220 and the exterior of the chamber.

[0033] The substrate support base 220 typically includes a support member 226 that is hermetically bonded to the platform housing 228. The platform housing 228 is typically made of a metal material such as stainless steel or aluminum. A cooling plate (not shown) is typically disposed within the platform housing 228 to thermally regulate the support member 226.

[0034] The support 226 may be made of aluminum or ceramic. The substrate support 226 has a substrate receiving surface 227 that receives and supports the substrate 205 during processing, the substrate receiving surface 227 being substantially parallel to the sputtering surface 233 of the target 235. A gap 239 exists between the target 235 and the sputtering surface 233. The support 226 also has a peripheral edge 229 that terminates before the overhanging edge of the substrate 205. The support 226 may be an electrostatic adsorption fixture, a ceramic body, a heater, or a combination thereof. In some embodiments, the support 226 is an electrostatic adsorption fixture containing a dielectric material with an embedded conductive layer or electrode 226A. This dielectric material is typically made of a dielectric material with high thermal conductivity, such as pyrolytic boron nitride, aluminum nitride, silicon nitride, alumina, or equivalent materials. Other aspects of the substrate support base 220 and the support 226 are further described below. In one embodiment, the conductive layer 226A is designed such that when a DC voltage is applied to the conductive layer 226A, the substrate 205 placed on the substrate receiving surface 227 will be electrostatically attracted via the electrostatic chuck power supply 243, thereby improving heat transfer between the substrate 205 and the support 226. In another embodiment, an RF bias power supply 241 is also connected to the conductive layer 226A to maintain a voltage applied to the substrate during processing to influence plasmon interactions on the surface of the substrate 205.

[0035] A program (or computer instructions) readable by the system controller 126 determines which tasks can be performed on the substrate. This program is software readable by the system controller 126 and contains code related to performing and monitoring, executing, and controlling movement and various process recipe tasks and process steps performed within the processing system 100 and the processing chamber 200. For example, the controller 126 may contain program code including a substrate positioning instruction set to operate the substrate support base 220; program code including a gas flow control instruction set to operate a gas flow control valve to adjust the sputtering gas flow to the chamber 200; program code including a pressure control instruction set to operate a throttle valve or gate valve to maintain pressure within the chamber 200; program code including a temperature control instruction set to control a temperature control system (not shown) in the substrate support base 220 or sidewall 204 to adjust the temperature of the substrate or sidewall 204 respectively; and program code including a process monitoring instruction set to monitor the process within the chamber 200.

[0036] The chamber 200 also includes a processing sleeve 250, which includes various components that can be easily removed from the chamber 200, such as cleaning sputtered deposits from component surfaces, replacing or repairing worn components, or adapting the chamber 200 to other processes. In one embodiment, the processing sleeve 250 includes an isolation ring assembly 280, a processing sleeve shroud 260, and an annular assembly 268 for placement on the peripheral edge 229 of the support 226 and terminating before the overhanging edge of the substrate 205.

[0037] The upper process assembly 208 may also include an RF source 281, a direct current (DC) source 282, an adapter 202, a motor 293, and a cover assembly 230. The cover assembly 230 typically includes a target 235, a magnetron system 289, and a cover sealing device 291. When in the closed position, the upper process assembly 208 is supported by sidewalls 204, such as... Figure 2 As shown. Adapter 202 is sealed to sidewall 204 and configured to assist in the removal of upper process assembly 208 and isolation ring assembly 280.

[0038] When in the processing position, the target 235 is located next to the adapter 202 and exposed to the processing area 210 of the processing chamber 200. The target 235 contains material deposited on the substrate 205 in a PVD or sputtering process. An isolation ring assembly 280 is located between the target 235 and the processing sleeve shroud 260 and the chamber body 201 to electrically isolate the target 235 from the processing sleeve shroud 260 and the chamber body 201.

[0039] During processing, the target 235 is biased relative to a processing chamber (e.g., chamber body 201 and adapter 202) located in a grounded region. This bias is provided by a power source located in the RF source 281 and / or the direct current (DC) power supply 282. It is believed that in high-voltage PVD processes, by delivering both RF energy and DC power to the target 235, significant process advantages can be achieved when used in conjunction with sputtering materials such as tungsten, cobalt, titanium, copper, nickel, ruthenium, aluminum, tantalum, molybdenum, and others, compared to conventional low-voltage DC plasma processing techniques. Furthermore, in one embodiment, the combination of RF and DC power allows for the use of lower total RF power during processing, which helps reduce plasma-related damage to the substrate and improve device yield compared to using only an RF power supply. In one embodiment, the RF source 281 includes an RF power supply 281A and an RF matching device 281B, configured to efficiently deliver RF energy to the target 235. In one embodiment, RF power supply 281A is capable of generating RF current with a frequency between about 13.56 MHz and about 228 MHz and a power between about 0 and about 8 kW. In one embodiment, DC power supply 282A in DC power supply 282 is capable of providing DC power between about 0 and about 10 kW.

[0040] The central portion of the processing chamber 200 includes an induction coil assembly 255 located within the central region of the processing unit 250 and configured to form an inductively coupled plasma 211 during processing. This plasma is used to ionize atoms ejected from the target 235 and / or to ionize the processing gas during processing. The induction coil assembly 255 includes an RF power supply 256 and an impedance matching device 257, which are connected to a coil 258 located within the processing region 210 of the processing chamber 200. In some embodiments, the coil 258 comprises a single-turn coil made of metal. In one configuration, the coil 258 is formed of a conductive material made of the same material as the target 235. In some configurations, the RF power supply 256 is capable of generating an RF current at an RF frequency of about 13.56 MHz to about 228 MHz, with a power range between about 0 and about 10 kilowatts.

[0041] During processing, a gas (e.g., argon) is supplied from a gas source 242 to the processing zone 210 via a mass flow controller 244 connected to a conduit 245. The gas source 242 may contain non-reactive gases, such as argon, krypton, helium, or xenon, which can impact and sputter material onto the target 235 at high energy. The gas source 242 may also contain reactive gases, such as one or more oxygen-containing or nitrogen-containing gases, which can react with the sputtered material to form a layer on the substrate. Used process gases and byproducts are discharged from the chamber 200 through an exhaust port 246, which receives the used process gases and directs them to the exhaust conduit 246, which has an adjustable gate valve 247 to control the pressure in the processing zone 210 within the chamber 200. The exhaust conduit 246 is connected to one or more exhaust pumps 249, such as cryogenic pumps. Typically, during processing, the pressure of the sputtering gas in chamber 200 is set below atmospheric pressure, such as in a vacuum environment, for example, from approximately 0.6 mTorr to approximately 400 mTorr. In one embodiment, the processing pressure is set from approximately 250 mTorr to approximately 400 mTorr, for example, approximately 325 mTorr. A plasma is formed between the substrate 205 and the target 235. Ions in the plasma are accelerated toward the target 235, causing material to detach from the target 235. The detached target material is deposited on the substrate.

[0042] The sealing device 291 typically includes a conductive wall 285, a central feed 284, and a shield 286. In this configuration, a portion of the source distribution plate 285, the central feed 284, the target 235, and the motor 293 encloses and forms a rear region 234. The rear region 234 is a sealed area on the back side of the target 235 and is typically filled with a flowing liquid during processing to remove heat generated by the target 235 during processing. In one embodiment, the conductive wall 285 and the central feed 284 are designed to support the motor 293 and the magnetron system 289 so that the motor 293 can rotate the magnetron system 289 during processing. In one embodiment, the motor 293 is electrically isolated from RF or DC power supplied from a power supply through a dielectric layer 293B (e.g., Delrin, G10, or Ardel).

[0043] Shield 286 may include one or more dielectric materials positioned to enclose and prevent interference from RF energy delivered to target 235 and affecting cluster tool 100. Figure 1 Other processing chambers disposed of in the process. In the configuration, shield 286 may contain Delrin, G10, Ardel or other similar materials and / or a thin ground plane metal RF shield.

[0044] To provide efficient sputtering, a magnetron system 289 is positioned behind the target 235, establishing a magnetic field in the upper process assembly 208 located in the processing region 210, near the sputtering surface 233 of the target 235, thereby generating magnetron-induced plasma 213. The magnetic field generated by the magnetron system 289 is used to capture electrons and ions, thereby increasing the plasma density in the magnetron-induced plasma 213 region and thus increasing the sputtering rate. According to some embodiments, the magnetron system 289 includes a source magnetron sputtering assembly 221, which includes an outer pole (not shown) and an inner pole (not shown). The magnetron system 289 is rotated by a motor 293 about the central axis 294 of the chamber 200. In some embodiments, a “closed-loop” magnetron sputtering configuration is formed such that the outer pole of the magnetron sputtering surrounds the inner pole, forming a gap of a continuous loop between the two poles. In a closed-loop configuration, the magnetic field emanating from and re-entering the target surface forms a "closed-loop" pattern, which can be used to confine electrons in a closed mode near the target surface; this is often referred to as a "racetrack" pattern. The closed-loop magnetron sputtering configuration can confine electrons and generate high-density plasma near the sputtering surface 233 of the target 235 to improve sputtering yield. In some other embodiments, an "open-loop" magnetron sputtering configuration is formed within the magnetron system 289, such that the outer pole of the magnetron sputtering surrounds the inner pole, forming a continuous loop gap between the two poles. In the open-loop magnetron sputtering configuration, electrons trapped between the inner and outer poles migrate, escape, and flee from the B-field formed at the opening of the magnetron sputtering. Therefore, during sputtering, electrons are only confined for a short time due to reduced confinement. Studies have found that using an open-loop magnetron sputtering configuration, when combined with RF and DC sputtering of multi-component targets as described herein, can significantly improve step coverage and increase the uniformity of the substrate surface material composition.

[0045] In some embodiments of the processing chamber 200, an RF bias power supply 241 is connected between the electrodes and RF ground to adjust the bias voltage of the substrate (also referred to as "wafer bias") during processing to control the degree of bombardment received on the substrate surface. In some embodiments, the electrodes are positioned near the substrate receiving surface 227 of the support 226 and include electrode 226A. In a PVD reactor, adjusting the impedance of the electrodes to ground to adjust the bombardment of the substrate surface will affect the stepped coverage, cantilever geometry, and properties of the deposited film, such as grain size, film stress, crystal orientation, film density, roughness, and film composition. Therefore, the RF bias power supply 241 can be used to change the deposition rate, etching rate, and even the composition of multi-component films on the substrate surface. In some embodiments, the RF bias power supply 241 enables deposition or etching by appropriately adjusting the impedance of the electrodes / substrate to ground. In some embodiments of the RF bias power supply 241, the RF bias power supply 241 has a variable capacitor tuning circuit and a feedback circuit to control the characteristics of the metallic or non-metallic layers deposited on the substrate.

[0046] In some embodiments, the RF bias power supply 241 is replaced by an RF source (not shown) and an impedance match (not shown), which are connected to electrode 226A. In some embodiments, the RF power supply is capable of generating RF current in the RF range of about 13.56 MHz to about 228 MHz, with a power range of about 0 to about 10 kilowatts.

[0047] processing method

[0048] Conductive features developed through physical vapor deposition (PVD) techniques, such as tungsten encapsulation and padding processes, are crucial for reducing contact resistance in medium-level loop (MOL) process steps. Existing tungsten encapsulation and padding processes include PVD tungsten deposition, wet etch removal of tungsten, and chemical vapor deposition (CVD) of tungsten, selectively depositing tungsten from the bottom up or conforming to fill MOL structures, such as trenches associated with gates, contact pads, conductive lines, and vias. Achieving high bottom coverage and minimal overhang is a prerequisite for good gap filling in bottom-up deposition methods.

[0049] Existing methods have several drawbacks. For example, applying a bias voltage to the substrate during sputtering effectively increases the sheath voltage, leading to re-sputtering of material. Since the substrate is typically close to the target during sputtering, the material ejected from the target travels towards the substrate at a large incident angle, resulting in disproportionate material accumulation at the edges of openings (e.g., trenches). This accumulation of excess material causes overhangs, potentially leading to reduced or pinched-off bottom coverage. Furthermore, the high temperatures and / or high substrate bias applied during PVD deposition of metals (such as tungsten, molybdenum, cobalt, titanium, tantalum, ruthenium, or other similar metals) can cause metal penetration into the exposed substrate surface. Typical substrate surfaces include a dielectric layer that may contain silicon dioxide (SiO2), silicon nitride (SiN), low-dielectric, ultra-low-dielectric, or other similar materials. Therefore, after a pullback (or similar etching process), the metal (e.g., tungsten) will mix with a portion of the substrate surface, causing interfacial scattering at these mixed portions when drive current passes through the metal layer formed on the substrate during device operation. Interface scattering generated within the metal layer increases the resistivity of conductive features formed on the substrate during device operation.

[0050] In various embodiments, the processing techniques disclosed herein can be implemented to reduce overhang and improve bottom coverage of the deposited metal layer on the substrate by increasing the spacing between the target and the substrate. For example, at low processing pressures, increasing the spacing between the target and the substrate reduces the angle of incidence of material ejected from the target toward the substrate, allowing more material to reach the bottom surface of openings (e.g., trenches) formed in the substrate and reducing the percentage of material deposited at the opening edges. At high processing pressures, increasing the spacing between the target and the substrate may increase the Penny ionization rate (e.g., due to an increased number of collisions between atoms or molecules in the gas), resulting in a higher fraction of quasi-stable ions affected by the substrate bias, which may reduce the percentage of material deposited at the opening edges. Furthermore, by reducing the deposition temperature of the PVD-deposited metal layer (e.g., to room temperature) and / or reducing the bias applied to the substrate (e.g., to 0V), the kinetic energy of the material deposited on the substrate is lower, thereby reducing the degree of mixing between the deposited material and the substrate surface. In various embodiments, a low-energy conductive underlayer can be deposited via PVD at low temperatures and low substrate bias, followed by the deposition of a thicker conductive layer at a higher substrate bias. By first depositing a low-energy conductive underlayer, mixing between the conductive layer and the substrate can be reduced, resulting in smoother boundaries and reduced interface scattering and resistivity of related conductive features. These techniques will be discussed below. Figure 3 , 4A -4F and 5-10 detailed descriptions.

[0051] Figure 3 A flowchart of method 300 is shown for filling features with a conductive material, according to the embodiments described herein. Method 300 will be targeted at... Figures 4A-4F The opening 402 formed in the substrate 400 shown is described. This method 300 can be performed in any suitable processing chamber configured with one or more chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) functions. Example processing systems suitable for performing the inventive methods disclosed herein may include, but are not limited to, any processing systems from the ENDURA®, CENTURA®, or PRODUCER® family, as well as ALPS® Plus or SIP ENCORE® PVD processing chambers, all commercially available from Applied Materials, Inc., Santa Clara, California. Other processing chambers, including those from other manufacturers, may also be suitably used in the teachings provided in this disclosure. In some embodiments, one or more conductive material layers can be deposited via a physical vapor deposition (PVD) process, such as... Figure 2 The deposition (PVD) processing system in the processing chamber 200 shown is used.

[0052] In some embodiments, method 300 may begin by placing substrate 400 (e.g., Figures 4A-4F(As shown) is provided to the PVD processing chamber, for example Figure 2 The processing chamber 200 is shown. The processing chamber 200 includes a substrate support base 220 for receiving the substrate 400 and has a sputtering source, such as a target 235. In some embodiments, the target 235 is configured as is known in the art and may include one or more metals (e.g., tungsten or tungsten source materials), as described herein. Although method 300 is described in the context of tungsten, in various embodiments, the target and source materials may include, for example but not limited to, tungsten, cobalt, titanium, copper, nickel, ruthenium, aluminum, tantalum, molybdenum, etc.

[0053] Figure 4A Display substrate 400 has an opening 402 formed on a first surface 404 (also referred to as the substrate extent) of substrate 400 and extends along a sidewall 410 to a bottom surface 408 of substrate 400. Substrate 400 may contain one or more dielectric materials, silicon (Si), metals, or similar materials. Furthermore, substrate 400 may contain additional material layers or have one or more completed or partially completed structures formed in or on substrate 400. For example, substrate 400 may include a dielectric layer such as silicon oxide, a low dielectric constant material (e.g., a material having a dielectric constant lower than that of silicon oxide, or a material lower than about 3.9), etc. The opening 402 may be formed in the dielectric layer. A conductive feature 420 (indicated by dashed lines) may be located on the bottom surface 408 of the opening 402 and is at least partially aligned with the opening 402. In some embodiments, when the opening 402 is filled with a conductive material, such as tungsten, it provides an electrical path to the conductive feature 420, for example, as part of a device (e.g., a logic device), an electrical path to the device (e.g., a gate, a contact pad, a conductive line, a via), or the like.

[0054] Opening 402 can be any opening, such as a trench, via, dual damascene structure, or similar structure. In some embodiments, the aspect ratio of the height to the width of opening 402 is approximately 4:1 or higher, for example, 4:1 to 9:1, or 4:1 to 20:1 (e.g., high aspect ratio). In some embodiments, opening 402 is a trench or via with a diameter of 25 nm or less, for example, about 1 nm to about 25 nm, such as 20 nm, 14 nm, 7 nm, 5 nm, 3 nm, or 1 nm. Opening 402 can be formed on substrate 400 using any suitable etching process.

[0055] Back Figure 3 In block 310, a first conductive layer 430 (also referred to herein as the bottom layer 430) is formed in the opening 402 of the substrate 400, as shown below. Figure 4BAs shown. The underlayer 430 can be formed by depositing a conductive material (e.g., tungsten, cobalt, titanium, copper, nickel, ruthenium, aluminum, tantalum, molybdenum) through a PVD process performed in a PVD chamber (e.g., processing chamber 200). In various embodiments, the underlayer 430 is a low-energy layer that can be deposited at room temperature (e.g., about 25°C) or near room temperature with a thickness of about 8 angstroms (Å) (e.g., two layers of tungsten) and a low or zero bias applied to the substrate 400. For example, in some embodiments, the thickness of the underlayer 430 is about 4 angstroms to about 50 angstroms, such as about 4 angstroms to about 20 angstroms, such as about 4 angstroms to about 12 angstroms, such as about 8 angstroms, and can be deposited in the opening 402 with a bias of about 0 watts (W) to about 50 W, such as about 0 W to about 25 W, such as about 1 W to about 50 W, such as about 1 W to about 25 W, applied to the substrate 400, and processed at a temperature of about 10°C to about 100°C, such as about 15°C to 40°C, such as about 25°C. In some embodiments, the processing pressure is set to about 250 mTorr to about 400 mTorr, for example, about 325 mTorr, and the spacing 239 between the target 235 and the substrate 400 can be about 50 mm to about 250 mm, for example, about 80 mm to about 200 mm, for example, about 130 mm to about 160 mm. Increasing the spacing 239 between the target 235 and the substrate 400 may result in a more uniform distribution of sputtering gas (e.g., argon) within the processing chamber. Furthermore, increasing the spacing 239 between the target 235 and the substrate 400 may reduce the angle of incidence of material ejected from the target as it moves toward the opening 402, reduce overhangs formed at the edge of the opening 402, and improve bottom coverage of the deposited material within the opening 402.

[0056] Depositing a low-energy underlayer 430 at low temperatures and / or with low or zero bias applied to the substrate 400 can reduce mixing between the deposited layer and the substrate surface material, and create a smooth boundary between the conductive material and the substrate 400, such as... Figure 5 As shown. This smooth boundary can reduce electron scattering at one or more interfaces formed between the substrate 400 and the bottom layer 430, reduce the resistivity of the formed metal layer, and improve the performance of any device and / or circuit electrically connected to the conductive feature 420. For example, low-energy deposition of the bottom layer 430 is thought to promote the growth of the α phase of tungsten, which has a lower resistivity than the β phase of tungsten. In contrast, when tungsten (or a similar material) is deposited at a higher substrate bias, the additional kinetic energy may be sufficient to overcome the energy barrier associated with the formation of the β phase, resulting in the deposition of a more brittle, higher resistivity β phase onto the substrate. Furthermore, since tungsten is a heavy element, relatively thin layers (e.g., 4 to 12 angstroms, such as about 8 angstroms or about two monolayers) are thought to provide sufficient protection against mixing during subsequent high-energy deposition processes.

[0057] Next, in block 320, a second conductive layer 440 is formed on the first conductive layer 430 (also called the bottom layer 430), as follows: Figure 4C As shown. The second conductive layer 440 can be formed by depositing a conductive material (e.g., tungsten, cobalt, titanium, copper, nickel, ruthenium, aluminum, tantalum, molybdenum) through a PVD process performed inside a PVD chamber (e.g., processing chamber 200). In various embodiments, the second conductive layer 440 can be deposited at room temperature (e.g., about 25°C) with a thickness of about 40 angstroms and a bias voltage of about 150 W applied to the substrate 400. For example, in some embodiments, the thickness of the second conductive layer 440 is about 20 to 100 angstroms, such as about 30 to 60 angstroms, such as about 35 to 45 angstroms, such as about 40 angstroms, and this layer can be deposited on the underlayer 430 with a bias voltage of about 0 W to 350 W, such as about 125 W to 175 W, such as about 150 W, and a processing temperature of about 10°C to 100°C, such as about 15°C to 40°C, such as about 25°C. In some embodiments, the processing pressure is set to approximately 250 mTorr to 400 mTorr, for example, approximately 325 mTorr, and the spacing 239 between the target 235 and the substrate 400 can be approximately 50 mm to 250 mm, for example, approximately 80 mm to 200 mm, for example, approximately 130 mm to 160 mm, for example, approximately 145 mm. Generally, depositing the second conductive layer 440 (e.g., relative to the first conductive layer 430) under a higher substrate bias will result in the formation of a β phase in the conductive material. As further described below, this β phase can be converted into an α phase by annealing the first and second conductive layers 430, 440.

[0058] In block 330, at least a portion of the first conductive layer 430 and the second conductive layer 440 are selectively removed from opening 402. For example, as Figure 4D As shown, a “retraction” process (e.g., including one or more wet etching steps) can be performed to remove at least a portion of the first conductive layer 430 and the second conductive layer 440 from the first surface 404 and sidewall 410 and opening 402 of the substrate 400.

[0059] In block 340, substrate 400 can be annealed. As described above, annealing can be performed to transform the β phase of the conductive material (e.g., tungsten, cobalt, titanium, copper, nickel, ruthenium, aluminum, tantalum, molybdenum) contained in the second conductive layer 440 into an α phase, the resistivity of which is lower than that of the β phase. Annealing can be performed at a temperature of approximately 150°C to approximately 350°C, for example, in the range of approximately 200°C to approximately 250°C, for approximately 5 seconds to approximately 30 seconds, for example, approximately 10 seconds.

[0060] In some embodiments, annealing may be performed in block 340 while a selective chemical vapor deposition (CVD) process is performed, which deposits a bulk layer 450 of conductive material (e.g., tungsten, cobalt, titanium, copper, nickel, ruthenium, aluminum, tantalum, molybdenum) in opening 402 in a “closed” process, such as Figure 4E As shown. For example, tungsten hexafluoride (WF6) (or any other suitable precursor gas for deposition of, for example, tungsten, cobalt, titanium, copper, nickel, ruthenium, aluminum, tantalum, or molybdenum) can be introduced into the processing chamber to deposit tungsten in opening 402. Since the CVD closed process is carried out at a temperature of about 250°C to about 350°C, for example about 300°C, the first conductive layer 430 and the second conductive layer 440 are annealed in the CVD process without the need for a separate dedicated annealing step.

[0061] In some embodiments, after block 320, method 300 does not remove the first conductive layer 430 and the second conductive layer 440, but may continue to block 340, in which the first conductive layer 430 and the second conductive layer 440 undergo a CVD "pad" process while being annealed to deposit additional conductive material to fill the opening 402, such as... Figure 4F As shown. For example, additional conductive material can be deposited by a CVD process at a temperature of about 250°C to about 350°C, for example about 300°C, to bulk fill a high aspect ratio feature (e.g., opening 402). Such a CVD process can utilize the first conductive layer 430 and / or the second conductive layer 440 as nucleation layers for depositing additional conductive material in the bulk filling step.

[0062] It is worth noting that the aforementioned CVD technology (or any other high-temperature process that may be performed after PVD deposition of the first conductive layer 430 and / or the second conductive layer 440) eliminates the need for an additional annealing step because the CVD process is performed at a sufficiently high temperature and for a sufficient time to convert the β-phase conductive material into the α-phase with lower resistivity. Therefore, the substrate processing time and overall energy consumption may be reduced.

[0063] Figure 6 The bias applied to substrate 400 as a function of bottom coverage of the trench structure, according to the embodiments described herein, is illustrated. As shown, increasing the spacing 239 between the target 235 and substrate 400 from 95 mm to 145 mm significantly improves bottom coverage, increasing it from less than 80% to over 90% under a non-zero substrate bias. The underlying mechanism for this improved bottom coverage is that the additional distance between the target 235 and substrate 400 reduces the angle at which sputtered material travels toward opening 402. This reduction in incident angle reduces the overhang at the edge of opening 402, allowing more sputtered material to reach the bottom surface 408 of opening 402, thereby improving bottom coverage.

[0064] Figure 7 This diagram illustrates the relationship between the amount of tungsten remaining on the tetraethoxysilane (TEOS) layer and processing temperature and substrate bias, as shown in the embodiments disclosed herein, measured by total internal reflection X-ray fluorescence (TXRF). As illustrated, a 100 Å PVD tungsten layer was deposited at three different temperatures (e.g., 400°C, 70°C, and 25°C) and at different intervals 239 and substrate biases (e.g., 0W, 50W, 100W, 250W, and 350W), resulting in varying amounts of mixing between the tungsten layer and the TEOS layer. Therefore, the amount of tungsten remaining on the TEOS substrate after wet etching of the tungsten layer varies, as shown in the figure. Figure 7 As shown, the increase in TXRF intensity indicates an increase in the amount of residual tungsten.

[0065] Generally, the TXRF signal is very high at a processing temperature of 400°C. Furthermore, as the substrate bias increases, the energy applied to the tungsten increases, leading to more mixing and increasing the amount of tungsten remaining on the TEOS layer. Lowering the processing temperature and using a longer spacing of 239 (e.g., approximately 145 mm) causes almost no mixing between the tungsten and the dielectric layer (e.g., TEOS).

[0066] Figure 8 The following diagram illustrates the amount of tungsten remaining in the TEOS layer with and without a substrate bias and underlayer 430, as measured by TXRF, according to the embodiment described herein. 100 Å of PVD tungsten was deposited at different substrate biases (e.g., 0W, 50W, 100W, 250W, 350W) to induce varying amounts of mixing between the tungsten and the TEOS layer, with (right) and without (left) an 8 Å underlayer 430. When the 100 Å PVD tungsten layer is deposited on the 8 Å underlayer 430, less tungsten remains in the TEOS substrate compared to a TEOS substrate without the underlayer 430. The advantage is that using a low-energy underlayer 430 effectively offsets the negative effects of mixing that occurs during annealing (e.g., resistivity increase), resulting in a TXRF signal comparable to that of an undeposited tungsten layer. Notably, all room-temperature deposition processes—with or without the underlayer 430—significantly outperformed deposition of a 100 Å tungsten layer at a short 239 nm spacing with a 95 mm diameter at high temperatures (250°C). Figure 8 (Top line).

[0067] Figure 9The resistivity of PVD tungsten layers deposited at 25°C and 325 mTorr under the influence of substrate bias is shown, according to the embodiments described herein. As shown, tungsten deposited at a substrate bias of 0 W produces more α phase, significantly reducing resistivity at lower thicknesses. In contrast, tungsten deposited at substrate biases of 100 W or 150 W produces more β phase and corresponds to higher resistivity at lower thicknesses. As mentioned above, a potential explanation for these phase and resistivity differences may be related to the energy applied to the tungsten during deposition; at lower energies, the α phase grows, while applying a bias to the substrate increases the kinetic energy of the ions, enabling the deposited tungsten to overcome the energy barrier, resulting in more β phase and higher resistivity.

[0068] In addition, such as Figure 9 As shown, the curves associated with substrate biases of 100W and 150W exhibit a dome shape. This behavior can be explained by changes in the deposited material as the layer thickness increases. For example, as the thickness of the tungsten layer increases (e.g., from about 20 to about 40 angstroms), the number of α-phase waterholes (e.g., from β-phase grain merging) increases, leading to more grain boundary scattering (also known as interface scattering). However, once the tungsten layer becomes thicker (e.g., beyond about 40 angstroms), stress accumulation within the layer causes a metastable β-phase to transform into the α-phase, reducing the layer's resistivity. As mentioned above, this β-phase to α-phase transformation can also be caused by thermal annealing. For example, as... Figure 10 As shown in the figure, the resistivity of 40 to 50 angstroms PVD tungsten films after 10 seconds of annealing at different temperatures can be significantly reduced by performing a short annealing step (e.g., during the CVD process or during a separate dedicated thermal annealing step) compared to the as-deposited layer.

[0069] While the foregoing describes embodiments disclosed herein, other further embodiments may be conceived without departing from its essential scope, the scope of which is defined by the following claims.

Claims

1. A method comprising: forming a first conductive layer at an opening of a substrate by physical vapor deposition (PVD), wherein the first conductive layer has a thickness of less than 20 Angstroms; forming a second conductive layer on the first conductive layer by PVD, wherein the first conductive layer and the second conductive layer are formed at a temperature of less than 50 degrees Celsius; and annealing at least a portion of the first conductive layer and the second conductive layer.

2. The method of claim 1, wherein the first conductive layer has a thickness of 4 to 12 Angstroms.

3. The method of claim 1, wherein the first conductive layer has a thickness of approximately 8 Angstroms.

4. The method of claim 1, wherein the first conductive layer has a thickness of approximately two monolayers.

5. The method of claim 1, wherein the first conductive layer and the second conductive layer comprise at least one of tungsten, cobalt, titanium, copper, nickel, ruthenium, aluminum, tantalum, molybdenum.

6. The method of claim 1, wherein the first conductive layer and the second conductive layer comprise tungsten.

7. The method of claim 1, wherein the first conductive layer and the second conductive layer are formed at a temperature of 15 degrees Celsius to 40 degrees Celsius.

8. The method of claim 1, wherein the first conductive layer and the second conductive layer are formed at approximately 25 degrees Celsius.

9. The method of claim 1, wherein the first conductive layer is formed at a bias of 1 W to 50 W applied to the substrate, and the second conductive layer is formed at a bias of more than 50 W applied to the substrate.

10. The method of claim 1, wherein the first conductive layer is formed at a bias of approximately 0 W applied to the substrate, and the second conductive layer is formed at a bias of 125 W to 175 W applied to the substrate.

11. The method of claim 1, wherein a spacing between a sputter target and the substrate is 130 mm to 160 mm when forming the first conductive layer and the second conductive layer.

12. The method of claim 1, wherein, annealing concurrently with forming a third conductive layer on the second conductive layer by chemical vapor deposition (CVD).

13. The method of claim 1, further comprising: etching at least a portion of the first conductive layer and the second conductive layer from sidewalls of one or more openings; and selectively forming a bulk conductive material layer on the second conductive layer after etching.

14. A method comprising: forming a first conductive layer at an opening of a substrate by physical vapor deposition (PVD), wherein the first conductive layer has a thickness of less than 20 Angstroms; forming a second conductive layer on the first conductive layer by PVD, wherein the second conductive layer has a thickness of more than 20 Angstroms, and the first conductive layer and the second conductive layer are formed at a temperature of less than 50 degrees Celsius.

15. The method of claim 14, wherein the first conductive layer is formed at a bias of 1 W to 50 W applied to the substrate, and the second conductive layer is formed at a bias of more than 50 W applied to the substrate.

16. The method of claim 14, wherein the first conductive layer has a thickness of 4 to 12 Angstroms.

17. The method of claim 14, wherein the first and second conductive layers comprise at least one of tungsten, cobalt, titanium, copper, nickel, ruthenium, aluminum, tantalum, molybdenum.

18. A method comprising: forming a first conductive layer at an opening of a substrate by physical vapor deposition (PVD), wherein a thickness of the first conductive layer is less than 20 Angstroms; forming a second conductive layer on the first conductive layer by PVD, wherein the first and second conductive layers are formed at a temperature less than 50 °C; and depositing a third conductive layer on the second conductive layer by chemical vapor deposition (CVD).

19. The method of claim 18, wherein the first conductive layer is formed with a bias of less than 50 W applied to the substrate, and the second conductive layer is formed with a bias of greater than 50 W applied to the substrate.

20. The method of claim 18, wherein the thickness of the first conductive layer is 4 to 12 Angstroms.

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