Duty ratio detection circuit and switching power supply converter using same
By introducing a duty cycle detection circuit into the switching power supply converter, and utilizing a ramp generation and sample-and-hold circuit to quickly detect changes in the duty cycle of the PWM pulse signal, the problem of the inability to quickly detect duty cycle changes in existing technologies is solved, thereby improving the dynamic response capability of the system.
Patent Information
- Application Number
- CN202411853458.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-11-21
AI Technical Summary
In existing technologies, changes in the duty cycle of PWM pulse signals cannot be detected quickly, resulting in the output voltage not matching in time and affecting the normal operation of subsequent circuits.
The system employs a first ramp generation circuit, a first sample-and-hold circuit, and a second sample-and-hold circuit. It detects the duty cycle change of the PWM pulse signal through a comparison circuit, uses the same capacitor for sampling and holding to avoid errors, and quickly outputs an indication signal.
This technology enables rapid detection of duty cycle changes in PWM pulse signals, improves the system's dynamic response, ensures that the output voltage matches the duty cycle changes, and enhances the circuit's rapid adjustment capability.
Smart Images
Figure CN120993053A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of switching converter, more particularly, to a duty cycle detection circuit and a switching power converter applying the same. BACKGROUND
[0002] In the working of the switching power converter, the PWM pulse signal is a signal needed by various working modules such as the control module, the logic module, the clock module, etc., and the duty cycle of the PWM pulse signal refers to the ratio of the high level time of the PWM pulse signal to a cycle time. In some cases, the duty cycle of the PWM pulse signal will change, but due to the feedback time of the circuit, the change information of the duty cycle of the PWM pulse signal cannot be quickly perceived, which will have a great impact on the later stage circuit, such as possibly leading to the output voltage not being able to match the change information of the duty cycle in time.
[0003] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems in the prior art. SUMMARY
[0004] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems in the prior art.
[0005] According to the duty cycle detection circuit of the present application, the duty cycle of the pulse signal is detected, which comprises: a first slope generation circuit receiving a first current and a pulse signal to be detected, and determining whether the first current charges a first capacitor according to the high and low level states of the pulse signal to be detected, so as to obtain a first slope signal; a first sample and hold circuit and a second sample and hold circuit receiving the first slope signal and the pulse signal to be detected, and sampling and holding the first slope signal in adjacent cycles of the pulse signal to be detected, so as to obtain a first sample and hold signal and a second sample and hold signal respectively; and a comparison circuit comparing the first sample and hold signal and the second sample and hold signal to obtain a comparison signal, wherein the high and low level states of the comparison signal indicate whether the duty cycle of the PWM pulse signal to be detected has changed.
[0006] Preferably, when the difference between the first sample and hold signal and the second sample and hold signal is greater than a bias voltage, it indicates that the duty cycle of the PWM pulse signal to be detected has changed.
[0007] Preferably, the pulse signal to be detected is inverted to obtain an intermediate pulse signal, and the duration of the low level of the intermediate pulse signal is greater than the duration of the high level of the pulse signal to be detected, and in the time when the intermediate pulse signal is at low level, the first current charges the first capacitor to obtain the first slope signal.
[0008] Preferably, the first short pulse signal and the second short pulse signal are obtained according to the falling edge information of the adjacent period of the pulse signal to be detected, the first sample-and-hold circuit samples and holds the first ramp signal to obtain a first sample-and-hold signal when the first short pulse signal is high, and the second sample-and-hold circuit samples and holds the first ramp signal to obtain a second sample-and-hold signal when the second short pulse signal is high.
[0009] Preferably, the first short pulse signal and the second short pulse signal are high when the pulse signal to be detected and the intermediate pulse signal are both low.
[0010] Preferably, the first short pulse signal is obtained by using a short pulse circuit at the falling edge time of the current period of the pulse signal to be detected, the second short pulse signal is obtained by using a short pulse circuit at the falling edge time of the next period of the current period of the pulse signal to be detected, and the pulse width of the first short pulse signal and the second short pulse is set to the difference between the time length during which the intermediate pulse signal is low and the time length during which the pulse signal to be detected is high.
[0011] Preferably, the first ramp generation circuit includes a first current source, a first switch, and a first capacitor, the first switch and the first capacitor are connected in parallel, the first current source and the first capacitor are connected in series, the other end of the first capacitor is grounded, the intermediate pulse signal controls the switching state of the first switch, and the signal at the common connection node of the first capacitor and the first current source is taken as the first ramp signal.
[0012] Preferably, the first sample-and-hold circuit includes a second switch and a second capacitor, one end of the second switch is connected to the common connection node of the first capacitor and the first current source, the second end is connected to the second capacitor, the other end of the second capacitor is grounded, and the voltage of the second capacitor is taken as the first sample-and-hold signal; the second sample-and-hold circuit includes a third switch and a third capacitor, one end of the third switch is connected to the common connection node of the first capacitor and the first current source, the second end is connected to the third capacitor, the other end of the third capacitor is grounded, and the voltage of the third capacitor is taken as the second sample-and-hold signal.
[0013] Preferably, the comparison circuit comprises a first comparator, a second comparator and an OR gate, the first comparator receives the first sample-and-hold signal at a positive input terminal, receives a second sample-and-hold signal and a bias voltage at a negative input terminal, and outputs a first comparison signal; the second comparator receives the second sample-and-hold signal at a positive input terminal, receives the first sample-and-hold signal and the bias voltage at a negative input terminal, and outputs a second comparison signal; the OR gate receives the first comparison signal and the second comparison signal, and outputs the comparison signal.
[0014] Preferably, the pulse signal to be detected comprises a first pulse signal and a second pulse signal, the first pulse signal and the second pulse signal are superimposed to form the pulse signal to be detected, and the first pulse signal and the second pulse signal are superimposed in a cycle-by-cycle sequence.
[0015] Preferably, a high / low state of the comparison signal indicates whether a duty cycle of the first pulse signal and the second pulse signal is consistent.
[0016] Preferably, the comparison circuit comprises a first comparator, the first comparator receives the first sample-and-hold signal and a second sample-and-hold signal to output the comparison signal.
[0017] In a second aspect, a switching power converter according to the present application comprises a reference voltage circuit, a switching controller, a power stage circuit and the above-mentioned duty cycle detection circuit, the reference voltage circuit receives an external pulse signal to generate a reference voltage signal according to the external pulse signal, the duty cycle detection circuit receives the external pulse signal to generate an output signal, the external pulse signal is taken as the pulse signal to be detected, the switching controller receives the reference voltage signal and the output signal of the duty cycle detection circuit to generate a switching control signal to control a power switch in the power stage circuit to operate, the power stage circuit receives an input voltage to output a desired output voltage according to the switching operation of the power switch, and the desired output voltage is consistent with the reference voltage signal.
[0018] In a third aspect, a switching power converter according to the present application comprises a clock phase-locked loop circuit, a slave converter main circuit and the above-mentioned duty cycle detection circuit, the clock phase-locked loop circuit receives an external pulse signal to generate a clock signal according to the external pulse signal, the external pulse signal is provided by a master converter; the duty cycle detection circuit receives the external pulse signal to generate an output signal, the external pulse signal is taken as the pulse signal to be detected, and the slave converter main circuit receives the clock signal and the output signal of the duty cycle detection circuit to adjust a working state of the slave converter main circuit, wherein the working state comprises at least one of the following: controlling a current working clock signal to be consistent with the external pulse signal, turning on / off or adjusting an output current.
[0019] The duty cycle detection circuit and the switching power converter using the same can quickly detect whether the duty cycle of the pulse signal changes, and when the change occurs, an indication signal can be immediately output to instruct the subsequent circuit to adjust, thereby increasing the fast dynamic response of the system. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figure 1 The first circuit block diagram of the switching power converter according to the present application is shown in FIG. 1.
[0021] Figure 2 The second circuit block diagram of the switching power converter according to the present application is shown in FIG. 2.
[0022] Figure 3 The circuit block diagram of the duty cycle detection circuit according to the present application is shown in FIG. 3.
[0023] Figure 4 The specific circuit diagram of the duty cycle detection circuit according to the present application is shown in FIG. 4.
[0024] Figure 5 The circuit diagram of the comparison circuit according to the present application is shown in FIG. 5. DETAILED DESCRIPTION
[0025] The preferred embodiments of the present application are described in detail below with reference to the accompanying drawings, but the present application is not limited to only these embodiments. The present application encompasses any alternative, modification, equivalent method and scheme made within the spirit and scope of the present application.
[0026] In order to make the public have a thorough understanding of the present application, the specific details are described in the following preferred embodiments of the present application, and the present application can also be completely understood without the description of these details for those skilled in the art.
[0027] The present application is described in more detail in the following paragraphs with reference to the accompanying drawings. It should be noted that the drawings are in a simplified form and use non-precise proportions, only to facilitate and clarify the purpose of assisting in the description of the embodiments of the present application.
[0028] Reference Figure 1 The first circuit block diagram of the switching power converter according to the present application is shown in FIG. 1. Figure 3This is a circuit block diagram of a duty cycle detection circuit according to the present invention. Figure 1 As shown, the switching power converter in this example includes a reference voltage circuit, a switching controller, a power stage circuit, and a duty cycle detection circuit. The switching power converter receives an input electrical signal to output a desired output voltage. A host computer outputs a pulse signal, such as a PWM signal, to the switching power converter. The reference voltage circuit receives the PWM signal and generates a corresponding reference voltage signal, Vout_ref. The duty cycle detection circuit synchronously receives the PWM signal, using the external pulse signal as the pulse signal to be detected, and detects whether the duty cycle of the PWM signal has changed, generating an output signal Vz indicating whether it has changed. The switching controller receives the reference voltage signal Vout_ref and the output signal Vz from the duty cycle detection circuit to generate a switching control signal to control the operation of the power switch in the power stage circuit. The power stage circuit receives an input electrical signal, such as an input voltage, and outputs a desired output voltage based on the switching action of the power switch. The desired output voltage is consistent with the reference voltage signal Vout_ref. Here, the duty cycle of the PWM signal corresponds to the reference voltage signal Vout_ref. The reference voltage circuit can be a filter circuit, etc., which converts the PWM signal into a corresponding voltage value. The power stage circuit can be a DC-DC switching circuit in the prior art, such as a buck switching circuit, a boost switching circuit, or a buck-boost switching circuit. The switch controller can be an existing controller structure, which receives the reference voltage signal Vout_ref and the feedback signal at the output terminal, generates a switch control signal, and adjusts the output signal by controlling the switching action of the power switch to make it consistent with the reference voltage signal Vout_ref. Here, the switch controller receives the output signal Vz of the duty cycle detection circuit. When the output signal Vz indicates a change in the reference voltage signal Vout_ref, such as an increase or decrease, the switch controller can quickly control the operating state of the power switch after receiving the information, so that the output voltage can be quickly adjusted accordingly. In some cases, when the power stage circuit has multiple phases, the switch controller can also adjust the number of operating phases of the power stage circuit according to the indication of the output signal Vz, so that the system can quickly match the load requirements.
[0029] refer to Figure 3 A circuit block diagram of the duty cycle detection circuit according to the present invention and Figure 4 This is a specific circuit diagram of a duty cycle detection circuit according to the present invention. The duty cycle detection circuit of this embodiment includes: a first ramp generating circuit, a first sample-and-hold circuit, a second sample-and-hold circuit, and a comparison circuit. (Reference) Figure 3 and Figure 4, the first slope generating circuit receives a first current I1 and a pulse signal PWM to be detected, and determines whether the first current I1 charges the first capacitor C RAMP to obtain a first slope signal V CAP , specifically, the first slope generating circuit comprises a first current source I1, a first switch S1 and a first capacitor C RAMP , the first switch S1 and the first capacitor C RAMP are connected in parallel, the first current source I1 and the first capacitor C RAMP are connected in series, the other end of the first capacitor is grounded, the first switch controls its switch state through an intermediate pulse signal RST, and a signal at a common connection node of the first capacitor and the first current source is the first slope signal V CAP . The intermediate pulse signal RST is obtained by taking the NOT of the pulse signal PWM to be detected, and the rising edge of the intermediate pulse signal is delayed from the falling edge of the pulse signal PWM to be detected, that is, the time length during which the intermediate pulse signal is at a low level is greater than the time length during which the pulse signal PWM to be detected is at a high level, preferably, the time length during which the intermediate pulse signal is at a low level is slightly greater than the time length during which the pulse signal PWM to be detected is at a high level, and during the time when the intermediate pulse signal is at a low level, the first current I1 charges the first capacitor C RAMP to obtain the first slope signal V CAP .
[0030] With reference to Figure 3 and Figure 4 , the first sample-and-hold circuit and the second sample-and-hold circuit receive the first slope signal V CAP and the pulse signal PWM to be detected, sample and hold the first slope signal V CAP in adjacent periods of the pulse signal PWM to be detected, and obtain a first sample-and-hold signal in1 and a second sample-and-hold signal in2, respectively. Specifically, a first short pulse signal SMP1 is obtained at the falling edge of the current period of the pulse signal PWM to be detected by using a short pulse circuit, a second short pulse signal SMP2 is obtained at the falling edge of the next period of the current period of the pulse signal PWM to be detected by using a short pulse circuit, and the short pulse circuit is not shown in Figure 3 . Preferably, the first sample-and-hold circuit samples and holds the first slope signal V CAP to obtain the first sample-and-hold signal in1 when the first short pulse signal SMP1 is at a high level, and the second sample-and-hold circuit samples and holds the first slope signal V CAP, obtain a second sample-and-hold signal in2, wherein, in order to better obtain the sample-and-hold signal, the sample-and-hold needs to be performed when the first ramp signal has not been reset, and therefore, in the case that the to-be-detected pulse signal and the intermediate pulse signal are both low, the first short pulse signal and the second short pulse signal are in a high level state. Preferably, the pulse width of the first short pulse signal and the second short pulse signal is set as the difference between the time length during which the intermediate pulse signal is in a low level and the time length during which the to-be-detected pulse signal is in a high level, so that the sampling can be performed at the time close to the peak value, and the sampling accuracy is good. CAP For sampling at the time close to the peak value, the sampling accuracy is good. Specifically, referring to Figure 4 , the first sample-and-hold circuit comprises a second switch S2 and a second capacitor C SMP1 , one end of the second switch is connected to the common connection node of the first capacitor and the first current source, the second end of the second switch is connected to the second capacitor, the other end of the second capacitor is connected to the ground, and the voltage of the second capacitor is taken as the first sample-and-hold signal in1; the second sample-and-hold circuit comprises a third switch S3 and a third capacitor C SMP2 , one end of the third switch is connected to the common connection node of the first capacitor and the first current source, the second end of the third switch is connected to the third capacitor, the other end of the third capacitor is connected to the ground, and the voltage of the third capacitor is taken as the second sample-and-hold signal in2. Here, the capacitance of the second capacitor C SMP1 (third capacitor C SMP2 ) is smaller than the capacitance of the first capacitor C RAMP . According to the above-mentioned slope generation circuit and the sampling circuit, it can be seen that the sampling and holding scheme of the present application uses the same capacitor (the first capacitor C RAMP ) to obtain two sample signals in the working process, thereby avoiding the error of the two sample signals caused by the difference between different capacitors, and the accuracy is high.
[0031] Referring to Figure 4 and Figure 5 , a circuit diagram of a comparison circuit according to the present application; the comparison circuit of the present embodiment compares the first sample-and-hold signal in1 and the second sample-and-hold signal in2 to obtain a comparison signal Vz, the high and low level states of the comparison signal indicate whether the duty cycle of the to-be-detected PWM pulse signal has changed, and the comparison signal Vz is taken as the output signal of the duty cycle detection circuit. In the present example, when the difference between the first sample-and-hold signal in1 and the second sample-and-hold signal in2 is greater than a bias voltage ΔV, it indicates that the duty cycle of the to-be-detected PWM pulse signal has changed. Specifically, as shown in Figure 5As shown, the comparison circuit includes a first comparator, a second comparator and an OR gate, the positive input end of the first comparator receives the first sample and hold signal in1, the negative input end receives the second sample and hold signal in2 and a bias voltage AV, and outputs a first comparison signal; the positive input end of the second comparator receives the second sample and hold signal in2, the negative input end receives the first sample and hold signal in2 and the bias voltage in2, and outputs a second comparison signal; the OR gate receives the first comparison signal and the second comparison signal, and outputs the comparison signal Vz. According to the above comparison circuit structure, when in1-in2>AV or in2-in1>AV, the comparison circuit outputs a high-level comparison signal, indicating that the duty cycle of the PWM signal to be detected has changed, and by detecting whether the output of the first comparator or the second comparator is high, it can be determined whether the duty cycle of the PWM signal is getting larger or smaller.
[0032] In another embodiment, Figure 2 For the second circuit diagram of the switching power converter according to the present application, the switching power converter of the present embodiment includes a clock phase-locked loop, a slave converter main circuit and a duty cycle detection circuit, which has basically the same circuit structure as the previous embodiment. The clock phase-locked loop receives an external pulse signal such as a PWM signal to generate a clock signal CLK therefrom, which can be provided by the main converter; the duty cycle detection circuit receives the PWM signal as the pulse signal to be detected, and generates an output signal Vz, in the present example, the pulse signal to be detected includes a first pulse signal PWM1 and a second pulse signal PWM2, which are superimposed to form the pulse signal to be detected, wherein the first pulse signal and the second pulse signal are superimposed in a cycle-by-cycle sequence, that is, the first cycle of the pulse signal to be detected is a cycle of the first pulse signal PWM1, the second cycle is a cycle of the second pulse signal PWM2, the third cycle of the pulse signal to be detected is a next cycle of the first pulse signal PWM1, the fourth cycle is a next cycle of the second pulse signal PWM2, and so on. The slave converter main circuit receives the clock signal CLK and the output signal Vz of the duty cycle detection circuit to adjust the working state in the slave converter main circuit, wherein the working state includes at least one of controlling the current working clock signal to be consistent with the external pulse signal, power on / off or output current adjustment.
[0033] In the embodiment, the comparison circuit includes a first comparator receiving the first sample-and-hold signal in1 and the second sample-and-hold signal in2 to output the comparison signal. The high or low state of the comparison signal indicates whether the duty cycles of the first pulse signal and the second pulse signal are consistent. According to the scheme of the embodiment, the first sample-and-hold signal in1 represents the duty cycle information of the first pulse signal, the second sample-and-hold signal in2 represents the duty cycle information of the second pulse signal, and the first comparator compares the two to represent whether the duty cycle of the second pulse signal is greater than or less than the duty cycle of the first pulse signal. For example, in some cases, the slave switching power converter needs to be consistent with the master converter. When the working duty cycle of the master converter changes, it is transmitted to the duty cycle detection circuit through the PWM signal. The duty cycle detection circuit detects that the PWM signal of the master converter has changed, and can immediately instruct the slave switching power converter to adjust the frequency.
[0034] The above embodiment of the application discloses a duty cycle detection circuit and a switching power converter applying the same. However, the duty cycle detection circuit of the application is not limited to the above-mentioned converter, but can also be applied to other occasions requiring duty cycle detection. The duty cycle detection scheme of the application can quickly detect whether the duty cycle of the related pulse signal changes. When the change occurs, a signal can be immediately output to instruct the rear-stage circuit to make relevant switching or frequency adjustment, thereby increasing the fast dynamic response of the system. Moreover, the input voltage of the comparator of the scheme of the application is basically stable, the accuracy and responsiveness requirements of the device are low, the response speed requirement of the comparator is low, and the cost is saved. The same capacitor is used for sample-and-hold in the scheme, avoiding the sampling error caused by the difference between different capacitors, and the control accuracy is high.
[0035] It should be further explained that the specific implementation and corresponding legends given are only a way to describe the implementation method of the application, and do not limit the specific structure of the implementation scheme of the application. Without departing from the principles and essence of the application, various changes or modifications can be made to these implementation methods, but these changes and modifications all fall within the protection scope of the application.
[0036] Although the above embodiments are described and explained separately, some of the technologies involved are common between the embodiments, and can be replaced and integrated between the embodiments according to the ordinary skill in the art. The content not explicitly recorded in one embodiment can be referred to another embodiment recorded.
[0037] The above-described implementation does not constitute a limitation on the protection scope of the technical scheme. Any modification, equivalent replacement and improvement made within the spirit and principles of the above-described implementation shall be included in the protection scope of the technical scheme.
Claims
1. A duty cycle detection circuit for detecting the duty cycle of a pulse signal, characterized in that, include: The first ramp generating circuit receives a first current and a pulse signal to be detected, and determines whether the first current charges the first capacitor based on the high or low level state of the pulse signal to be detected, so as to obtain the first ramp signal. The first sample-and-hold circuit and the second sample-and-hold circuit receive the first ramp signal and the pulse signal to be detected, and sample and hold the first ramp signal in adjacent periods of the pulse signal to be detected to obtain the first sample-and-hold signal and the second sample-and-hold signal, respectively. The comparison circuit compares the first sample-and-hold signal and the second sample-and-hold signal to obtain a comparison signal. The high or low level state of the comparison signal indicates whether the duty cycle of the PWM pulse signal to be detected has changed.
2. The duty cycle detection circuit according to claim 1, characterized in that, When the difference between the first sample-and-hold signal and the second sample-and-hold signal is greater than the bias voltage, it indicates that the duty cycle of the PWM pulse signal to be detected has changed.
3. The duty cycle detection circuit according to claim 1, characterized in that, The intermediate pulse signal is obtained by negating the pulse signal to be detected, and the rising edge of the intermediate pulse signal is delayed compared to the falling edge of the pulse signal to be detected. During the period when the intermediate pulse signal is at a low level, the first current charges the first capacitor to obtain the first ramp signal.
4. The duty cycle detection circuit according to claim 3, characterized in that, Based on the falling edge information of adjacent periods of the pulse signal to be detected, a first short pulse signal and a second short pulse signal are obtained. When the first short pulse signal is high, the first sample-and-hold circuit samples and holds the first ramp signal to obtain the first sample-and-hold signal. When the second short pulse signal is high, the second sample-and-hold circuit samples and holds the first ramp signal to obtain the second sample-and-hold signal.
5. The duty cycle detection circuit according to claim 4, characterized in that, When both the pulse signal to be detected and the intermediate pulse signal are low, the first short pulse signal and the second short pulse signal are in a high-level state.
6. The duty cycle detection circuit according to claim 5, characterized in that, The pulse widths of the first short pulse signal and the second short pulse are set to the duration during which both the intermediate pulse signal and the pulse signal to be detected are low.
7. The duty cycle detection circuit according to claim 4, characterized in that, A first short pulse signal is obtained using a short pulse circuit at the falling edge of the current period of the pulse signal to be detected. A second short pulse signal is obtained by using a short pulse circuit at the falling edge of the next cycle of the current cycle of the pulse signal to be detected.
8. The duty cycle detection circuit according to claim 3, characterized in that, The first ramp generating circuit includes a first current source, a first switch, and a first capacitor. The first switch and the first capacitor are connected in parallel, the first current source and the first capacitor are connected in series, and the other end of the first capacitor is grounded. The intermediate pulse signal controls the switching state of the first switch, and the signal at the common connection node of the first capacitor and the first current source serves as the first ramp signal.
9. The duty cycle detection circuit according to claim 8, characterized in that, The first sample-and-hold circuit includes a second switch and a second capacitor. One end of the second switch is connected to the common connection node of the first capacitor and the first current source, and the second end is connected to the second capacitor. The other end of the second capacitor is grounded, and the voltage of the second capacitor serves as the first sample-and-hold signal. The second sample-and-hold circuit includes a third switch and a third capacitor. One end of the third switch is connected to the common connection node of the first capacitor and the first current source, and the second end is connected to the third capacitor. The other end of the third capacitor is grounded, and the voltage of the third capacitor serves as the second sample-and-hold signal.
10. The duty cycle detection circuit according to claim 8, characterized in that, The capacitance of the second / third capacitor is less than the capacitance of the first capacitor.
11. The duty cycle detection circuit according to claim 2, characterized in that, The comparison circuit includes a first comparator, a second comparator, and an OR gate. The positive input of the first comparator receives the first sample-and-hold signal, the negative input receives the second sample-and-hold signal and the bias voltage, and outputs the first comparison signal; The positive input of the second comparator receives the second sample-and-hold signal, the negative input receives the first sample-and-hold signal and the bias voltage, and outputs the second comparison signal; The OR gate receives the first comparison signal and the second comparison signal, and outputs the comparison signal.
12. The duty cycle detection circuit according to claim 1, characterized in that, The pulse signal to be detected includes a first pulse signal and a second pulse signal. The first pulse signal and the second pulse signal are superimposed to form the pulse signal to be detected, wherein the first pulse signal and the second pulse signal are superimposed in a cycle-by-cycle order.
13. The duty cycle detection circuit according to claim 12, characterized in that, The high and low level states of the comparison signal indicate whether the duty cycles of the first pulse signal and the second pulse signal are consistent.
14. The duty cycle detection circuit according to claim 13, characterized in that, The comparison circuit includes a first comparator. The first comparator receives the first sample-and-hold signal and the second sample-and-hold signal to output the comparison signal.
15. A switching power supply converter, characterized in that, It includes a reference voltage circuit, a switch controller, a power stage circuit, and a duty cycle detection circuit as described in any one of claims 1-11. The reference voltage circuit receives external pulse signals to generate a reference voltage signal. The duty cycle detection circuit receives the external pulse signal to generate an output signal, and the external pulse signal serves as the pulse signal to be detected. The switch controller receives the reference voltage signal and the output signal of the duty cycle detection circuit to generate a switch control signal to control the operation of the power switch in the power stage circuit. The power stage circuit receives the input voltage and outputs a desired output voltage based on the switching action of the power switch, the desired output voltage being consistent with the reference voltage signal.
16. A switching power supply converter, characterized in that, It includes a clock phase-locked loop circuit, a slave converter main circuit, and a duty cycle detection circuit as described in any one of claims 1, 12-14. The clock-locked loop circuit receives an external pulse signal to generate a clock signal, which is provided by the main converter. The duty cycle detection circuit receives the external pulse signal to generate an output signal, and the external pulse signal serves as the pulse signal to be detected. The slave converter main circuit receives the clock signal and the output signal of the duty cycle detection circuit to adjust the operating state of the slave converter main circuit. The operating state includes at least one of controlling the current operating clock signal to be consistent with the external pulse signal, powering on / off, or adjusting the output current.