Small-area current mode CMOS voltage reference circuit

Abstract

The invention discloses a small-area current mode CMOS (Complementary Metal Oxide Semiconductor) voltage reference circuit which comprises a bias circuit generator, a negative temperature coefficient current generator, a beta multiplier and a mirror image reference voltage generator, the bias circuit generator forms a current mirror through a multi-stage MOS (Metal Oxide Semiconductor) tube to generate stable bias voltages VB1 and VB2, and the mirror image reference voltage generator generates a mirror image reference voltage; grid bias is provided for the negative temperature coefficient current generator and the beta multiplier, so that the corresponding MOS tubes are in a sub-threshold region, the negative temperature coefficient current generator outputs negative temperature coefficient current, the beta multiplier multiplies the received current, generates positive temperature coefficient current and outputs the positive temperature coefficient current to the mirror image reference voltage generator, and the mirror image reference voltage generator outputs the positive temperature coefficient current. The mirror reference voltage generator outputs a reference voltage with a low temperature coefficient at the VREF. The full CMOS structural design is adopted, a BJT transistor is removed, the function of the reference circuit is achieved only through the MOS transistor and the resistor, the chip area of the circuit is remarkably reduced, and the reference circuit is particularly suitable for the design scene of low-power-consumption and small-size chips sensitive to the area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a small-area current-mode CMOS voltage reference circuit. BACKGROUND

[0002] In integrated circuit design, a voltage reference circuit is a key component of analog circuits and mixed-signal circuits, providing a stable reference voltage for various circuits, and its performance directly affects the accuracy, stability and reliability of the entire circuit system.

[0003] At present, most existing reference circuits are bandgap reference circuits with BJT transistors. This bandgap reference circuit uses the negative temperature coefficient of the base-emitter voltage of the BJT and the positive temperature coefficient of the thermal voltage to compensate, so as to realize a reference voltage with zero temperature coefficient. However, this method has obvious defects:

[0004] 1. Large circuit area: the structural characteristics of BJT transistors result in a large chip area, which is not conducive to application in low-power, small-area chip design.

[0005] 2. High requirement for power voltage: the working characteristics of BJT make the bandgap reference circuit need a large power voltage to work normally, which is greatly limited in the design of low-voltage circuits and cannot meet the current increasing demand for low-voltage chip design.

[0006] 3. Limited temperature coefficient compensation: the existing reference circuit is difficult to realize in a low-voltage situation when performing secondary compensation, resulting in poor temperature coefficient performance and affecting the stability of the circuit in a wide temperature range.

[0007] Therefore, it is an urgent problem in the field to develop a reference circuit with small area, low voltage, good temperature coefficient and suitable for low-power chip design. SUMMARY

[0008] The purpose of the present application is to provide a small-area current-mode CMOS voltage reference circuit.

[0009] To achieve the above purpose, the present application adopts the following technical solutions:

[0010] The small-area current-mode CMOS voltage reference circuit comprises a bias circuit generator, a negative temperature coefficient current generator, a beta multiplier and a mirror reference voltage generator, the bias circuit generator generates stable bias voltages VB1 and VB2 by a multi-stage MOS tube current mirror, and provides gate bias for the negative temperature coefficient current generator and the beta multiplier, so that the corresponding MOS tubes are in the sub-threshold region, the negative temperature coefficient current generator outputs a negative temperature coefficient current, which is transmitted to the beta multiplier and the mirror reference voltage generator as a temperature-compensated negative temperature coefficient, the beta multiplier multiplies the received current to generate a positive temperature coefficient current and output it to the mirror reference voltage generator, and the mirror reference voltage generator integrates the negative temperature coefficient current and the positive temperature coefficient current, and finally outputs a reference voltage with low temperature coefficient at VREF through voltage / current superposition.

[0011] Further, the bias circuit generator comprises MOS tubes M12, M13, M14, M15, M16, M17 and a resistor R10, wherein the sources of the MOS tubes M12 and M13 are connected to the power supply VDD, the gates of the MOS tubes M12 and M13 are connected to the bias voltage VB1, the gate of the MOS tube M12 is short-circuited to the drain thereof, the drain of the MOS tube M14 is connected to the drain of the MOS tube M12, the gate of the MOS tube M14 is connected to the gate of the MOS tube M15, the gate of the MOS tube M15 is short-circuited to the drain thereof, the drain of the MOS tube M15 is connected to the drain of the MOS tube M13, the drain of the MOS tube M16 is connected to the source of the MOS tube M14, the gates of the MOS tubes M16 and M17 are connected to the bias voltage VB2, the gate of the MOS tube M17 is short-circuited to the drain thereof, the source of the MOS tube M17 is connected to the ground, and one end of the resistor R10 is connected to the source of the MOS tube M16 and the other end thereof is connected to the ground.

[0012] Further, the negative temperature coefficient current generator comprises MOS tubes M1, M2, M9, M10, M11, a resistor R1 and a first operational amplifier, wherein the sources of the MOS tubes M1 and M2 are connected to the power supply VDD, the gates of the MOS tubes M1 and M2 are connected to the positive output terminal of the first operational amplifier, the drain of the MOS tube M1 is connected to the drain of the MOS tube M9, the gate of the MOS tube M9 is connected to the drain thereof and the gate of the MOS tube M10, the drain of the MOS tube M10 and the source of the MOS tube M9 are connected to the negative input terminal of the first operational amplifier, the source of the MOS tube M10 is connected to the ground, the drain of the MOS tube M2 is connected to the drain of the MOS tube M11, the gate of the MOS tube M11 is short-circuited to the drain thereof, the source of the MOS tube M11 and one end of the resistor R1 are connected to the positive input terminal VP of the first operational amplifier, a comparator is connected between the MOS tube M11 and the resistor R1, and the other end of the resistor R1 is connected to the ground.

[0013] Further, the β multiplier comprises MOS transistor M3, MOS transistor M4, MOS transistor M18, MOS transistor M19, resistor R2 and a second operational amplifier, wherein the sources of MOS transistor M3 and MOS transistor M4 are connected to power supply VDD, the gates of MOS transistor M3 and MOS transistor M4 are connected to the inverting output terminal VN of the second operational amplifier, the drain of MOS transistor M3 is connected to the drain and gate of MOS transistor M18 and the inverting input terminal of the second operational amplifier, the drain of MOS transistor M18 is connected to its gate, the source of MOS transistor M18 is connected to ground, the drain of MOS transistor M4 is connected to the drain of MOS transistor M19 and the non-inverting input terminal of the first operational amplifier, the gate of MOS transistor M19 is connected to the gate of MOS transistor M18, one end of resistor R2 is connected to the source of MOS transistor M19, and the other end of resistor R2 is connected to ground.

[0014] Further, the mirror reference voltage generator comprises MOS transistor M5, MOS transistor M7, resistors R3, R4, R5 and R6, wherein the sources of MOS transistor M5 and MOS transistor M6 are connected to power supply VDD, the gate of MOS transistor M5 is connected to the gate of MOS transistor M2, the gate of MOS transistor M1 and the non-inverting output terminal VP of the first operational amplifier, the drain of MOS transistor M5 is connected to resistor R3 and the drain of MOS transistor M7, the gate of MOS transistor M7 is connected to the gate of MOS transistor M3, the gate of MOS transistor M4 and the inverting output terminal VN of the second operational amplifier, resistor R3, resistor R4, resistor R5 and resistor R6 are connected in series, the other end of resistor R6 is connected to ground, and comparators are connected between resistor R4 and resistor R5 and between resistor R5 and resistor R6, respectively.

[0015] Further, it further comprises MOS transistor M6, MOS transistor M8, resistors R7, R8 and R9, wherein the sources of MOS transistor M6 and MOS transistor M8 are connected to power supply VDD, the gate of MOS transistor M6 is connected to the gate of MOS transistor M5, the gate of MOS transistor M2, the gate of MOS transistor M1 and the non-inverting output terminal VP of the first operational amplifier, the drain of MOS transistor M6 is connected to the drain of MOS transistor M8 and one end of resistor R7, the gate of MOS transistor M8 is connected to the gate of MOS transistor M7, the gate of MOS transistor M3, the gate of MOS transistor M4 and the inverting output terminal VN of the second operational amplifier, resistor R7, resistor R8 and resistor R9 are connected in series, and the other end of resistor R9 is connected to ground.

[0016] Further, the output terminal VREF is connected between MOS transistor M6, MOS transistor M8 and resistor R7.

[0017] Further, an input terminal for inputting negative temperature coefficient compensation current is connected between resistor R7 and resistor R8, and an input terminal for inputting positive temperature coefficient compensation current is connected between resistor R8 and resistor R9.

[0018] Compared with the background art, the present application has the following advantages:

[0019] 1. The present application adopts a full CMOS structure design, removes the BJT transistor, and only realizes the reference circuit function through MOS tubes and resistors. Since the CMOS tube can realize a more compact layout in the integrated circuit process, and no additional process area is reserved for the BJT, compared with the existing bandgap reference circuit which relies on the BJT transistor, the structure characteristics result in a larger chip area occupation. The present design significantly reduces the chip area of the circuit, and is especially suitable for low-power, small-size chip design scenarios which are sensitive to area.

[0020] 2. The present application generates stable bias voltages VB1 and VB2 through a bias circuit generator, so that the core MOS tube works in the sub-threshold region. The MOS tube in the sub-threshold region has low-voltage working characteristics, which, in combination with the current mode design architecture, reduces the demand of the circuit on the power supply voltage, and can work stably in a low-voltage environment, meeting the mainstream demand of current low-voltage chip design.

[0021] 3. The present application is a current mode CMOS reference circuit. The reference current can be converted into a reference voltage through the resistance network in the mirror reference voltage generator. By adjusting the resistance ratio of the resistance network, the size of the output reference voltage VREF can be freely set, meeting the diversified demand of reference voltage of different circuit systems, and improving the universality of the circuit.

[0022] 4. The circuit core MOS tube of the present application works in the sub-threshold region. The drain current of the MOS tube in the sub-threshold region changes exponentially with the gate-source voltage, and can maintain stable work at a lower current, significantly reducing the static power consumption of the circuit, and being suitable for low-power chip design scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The figure is a circuit structure diagram of the present application;

[0024] Figure 2 The figure is a first-order curve diagram of the present application;

[0025] Figure 3 The figure is a twice jump diagram of the present application;

[0026] Figure 4 The figure is a twice compensation diagram of the present application. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application, and are not used to limit the present application.

[0028] It should be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like, as used herein, are intended to be based on the orientation or positional relationship shown in the drawings, and are merely for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements of the present application must have a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0029] Embodiment

[0030] Cooperation Figures 1 to 4 As shown, the present application discloses a small-area current-mode CMOS voltage reference circuit, which comprises a bias circuit generator, a negative temperature coefficient current generator, a beta multiplier and a mirror reference voltage generator. The bias circuit generator generates stable bias voltages VB1 and VB2 by a multi-stage MOS tube current mirror, and provides gate bias for the negative temperature coefficient current generator and the beta multiplier, so that the corresponding MOS tubes are in the sub-threshold region. The negative temperature coefficient current generator outputs a negative temperature coefficient current, which is transmitted to the beta multiplier and the mirror reference voltage generator as a temperature compensation negative temperature coefficient. The beta multiplier multiplies the received current to generate a positive temperature coefficient current and output it to the mirror reference voltage generator. The mirror reference voltage generator integrates the negative temperature coefficient current and the positive temperature coefficient current, and finally outputs a reference voltage with low temperature coefficient at VREF through voltage / current superposition.

[0031] The present embodiment adopts a full CMOS structure design, removes the BJT transistor, and realizes the reference circuit function only by MOS tubes and resistors. Since the CMOS tube can realize a more compact layout in the integrated circuit process, and no additional process area is reserved for the BJT, compared with the existing bandgap reference circuit which relies on the BJT transistor, the structure characteristics result in a larger chip area occupation. The present design significantly reduces the chip area of the circuit, and is especially suitable for low-power, small-size chip design scenarios which are sensitive to area.

[0032] The bias circuit generator generates stable bias voltages VB1 and VB2 to make the core MOS tube work in the sub-threshold region. The MOS tube in the sub-threshold region has low-voltage working characteristics, which, in combination with the current-mode design architecture, reduces the demand of the circuit on the power supply voltage, and can work stably in a low-voltage environment, meeting the mainstream demand of current low-voltage chip design.

[0033] The core function of the bias circuit generator is to generate stable bias voltages VB1 and VB2 to provide gate bias for the MOS tubes of the negative temperature coefficient current generator, the beta multiplier and the mirror reference voltage generator, and ensure that they work in the sub-threshold region.

[0034] The bias circuit generator comprises MOS tubes M12, M13, M14, M15, M16, M17 and a resistor R10, wherein the sources of the MOS tubes M12 and M13 are connected to a power supply VDD, the gates of the MOS tubes M12 and M13 are connected to a bias voltage VB1, the gate of the MOS tube M12 is short-circuited to the drain of the MOS tube M12, the drain of the MOS tube M14 is connected to the drain of the MOS tube M12, the gate of the MOS tube M14 is connected to the gate of the MOS tube M15, the gate of the MOS tube M15 is short-circuited to the drain of the MOS tube M15, the drain of the MOS tube M15 is connected to the drain of the MOS tube M13, the drain of the MOS tube M16 is connected to the source of the MOS tube M14, the gates of the MOS tubes M16 and M17 are connected to a bias voltage VB2, the gate of the MOS tube M17 is short-circuited to the drain of the MOS tube M17, the source of the MOS tube M17 is connected to ground, one end of the resistor R10 is connected to the source of the MOS tube M16, and the other end of the resistor R10 is connected to ground.

[0035] The MOS tube M12 and the MOS tube M13 constitute a first-stage current mirror, the gate of the MOS tube M12 is short-circuited to the drain of the MOS tube M12 as a reference tube, and the MOS tube M13 mirrors the current of the MOS tube M12.

[0036] The MOS tube M14 and the MOS tube M15 constitute a second-stage current mirror, and the current of the MOS tube M12 and the MOS tube M13 is transmitted to the next stage.

[0037] The MOS tube M16 and the MOS tube M17 constitute a third-stage current mirror, the gate of the MOS tube M17 is short-circuited to the drain of the MOS tube M17, and the resistor R10 is used to form current negative feedback to stabilize the output bias voltages VB1 and VB2.

[0038] Through the accurate mirroring of the multi-stage current mirror, the voltage values of the bias voltages VB1 and VB2 are stable, and the MOS tubes in the negative temperature coefficient current generator and the beta multiplier are ensured to work in the sub-threshold region, thereby laying a foundation for the generation of the subsequent temperature coefficient current.

[0039] The negative temperature coefficient current generator utilizes the characteristic that the threshold voltage of the sub-threshold region MOS transistor has a negative temperature coefficient, generates a negative temperature coefficient current through an operational amplifier clamping and resistance adjustment, and comprises MOS transistors M1, M2, M9, M10, M11, a resistor R1 and a first operational amplifier, wherein the sources of the MOS transistors M1 and M2 are connected to a power supply VDD, the gates of the MOS transistors M1 and M2 are connected to a positive output terminal of the first operational amplifier, the drain of the MOS transistor M1 is connected to the drain of the MOS transistor M9, the gate of the MOS transistor M9 is connected to the drain of the MOS transistor M9 and the gate of the MOS transistor M10, the drain of the MOS transistor M10 and the source of the MOS transistor M9 are connected to a negative input terminal of the first operational amplifier, the source of the MOS transistor M10 is connected to ground, the drain of the MOS transistor M2 is connected to the drain of the MOS transistor M11, the gate of the MOS transistor M11 is connected to the drain of the MOS transistor M11, the source of the MOS transistor M11 and one end of the resistor R1 are connected to a positive input terminal VP of the first operational amplifier, and a comparator is connected between the MOS transistor M11 and the resistor R1, and the other end of the resistor R1 is connected to ground.

[0040] The MOS transistors M1 and M2 constitute a current mirror, the gates of which are connected to the positive output terminal of the first operational amplifier, so as to ensure that the currents of the two transistors are consistent.

[0041] The MOS transistors M9 and M10 are a pair of transistors with a width-length ratio equal to K, the gate of the MOS transistor M9 is connected to the drain of the MOS transistor M9, and the MOS transistor M9 forms a current mirror with the MOS transistor M10, and the source voltage of the MOS transistor M9 and the drain voltage of the MOS transistor M10 are clamped through the negative input terminal of the first operational amplifier.

[0042] The gate of the MOS transistor M11 is connected to the drain of the MOS transistor M11, and the source voltage of the MOS transistor M11 and the voltage at one end of the resistor R1 are connected to the positive input terminal VP of the first operational amplifier, the operational amplifier makes the positive and negative input terminal voltages equal through negative feedback, and the current relationship between the MOS transistor M11 and the MOS transistors M9 / M10 is stable.

[0043] Based on the current-voltage characteristic of the sub-threshold region MOS transistor, the difference (K) in the width-length ratio of the MOS transistors M9 and M10 will generate a voltage containing an lnK coefficient, which is converted by the resistor R1 to form a negative temperature coefficient current, and the current is copied and output through the current mirror composed of the MOS transistors M1 and M2.

[0044] The beta multiplier utilizes the current difference of asymmetric sub-threshold MOS tubes and the positive temperature coefficient characteristic of thermal voltage to generate a positive temperature coefficient current by current multiplication. The beta multiplier comprises MOS tubes M3, M4, M18, M19, a resistor R2 and a second operational amplifier. The sources of the MOS tubes M3 and M4 are connected to a power supply VDD. The gates of the MOS tubes M3 and M4 are connected to a reverse output terminal VN of the second operational amplifier. The drain of the MOS tube M3 is connected to the drain and gate of the MOS tube M18 and a reverse input terminal of the second operational amplifier. The drain of the MOS tube M18 is connected to the gate of the MOS tube M18. The source of the MOS tube M18 is connected to ground. The drain of the MOS tube M4 is connected to the drain of the MOS tube M19 and a forward input terminal of the first operational amplifier. The gate of the MOS tube M19 is connected to the gate of the MOS tube M18. One end of the resistor R2 is connected to the source of the MOS tube M19, and the other end of the resistor R2 is connected to ground.

[0045] The MOS tubes M3 and M4 form a current mirror, and the gates thereof are connected to the reverse output terminal VN of the second operational amplifier to ensure current consistency. The MOS tubes M18 and M19 are a pair of tubes with a width-length ratio equal to K. The gate of the MOS tube M18 is connected to the drain of the MOS tube M18. The MOS tube M18 forms a current mirror with the MOS tube M19. The source of the MOS tube M18 is connected to ground. The source of the MOS tube M19 is connected to ground in series with the resistor R2. The second operational amplifier makes the drain voltage of the MOS tube M3 equal to the drain voltage of the MOS tube M4 through negative feedback. In combination with the current of the sub-threshold MOS tube, the width-length ratio difference of the MOS tubes M18 and M19 and the resistor R2 generate a voltage related to thermal voltage. After conversion, a positive temperature coefficient current is formed, which is copied and output by the current mirror formed by the MOS tubes M3 and M4.

[0046] The mirror reference voltage generator comprises MOS tubes M5, M7, resistors R3, R4, R5 and R6. The sources of the MOS tubes M5 and M6 are connected to a power supply VDD. The gate of the MOS tube M5 is connected to the gate of the MOS tube M2, the gate of the MOS tube M1 and a forward output terminal VP of the first operational amplifier. The drain of the MOS tube M5 is connected to the resistor R3 and the drain of the MOS tube M7. The gate of the MOS tube M7 is connected to the gate of the MOS tube M3, the gate of the MOS tube M4 and a reverse output terminal VN of the second operational amplifier. The resistors R3, R4, R5 and R6 are connected in series. The other end of the resistor R6 is connected to ground. Comparators are connected between the resistor R4 and the resistor R5 and between the resistor R5 and the resistor R6, respectively.

[0047] The embodiment also includes MOS transistor M6, MOS transistor M8, resistors R7, R8 and R9, wherein the source of MOS transistor M6 and the source of MOS transistor M8 are both connected to power supply VDD, the gate of MOS transistor M6 is connected to the gate of MOS transistor M5, the gate of MOS transistor M2, the gate of MOS transistor M1 and the positive output terminal VP of the first operational amplifier, the drain of MOS transistor M6 is connected to the drain of MOS transistor M8 and one end of resistor R7, the gate of MOS transistor M8 is connected to the gate of MOS transistor M7, the gate of MOS transistor M3, the gate of MOS transistor M4 and the negative output terminal VN of the second operational amplifier, resistors R7, R8 and R9 are connected in series, and the other end of resistor R9 is connected to ground.

[0048] The output terminal VREF is connected between MOS transistor M6, MOS transistor M8 and resistor R7. The compensation circuit includes multiple comparators for integrating positive and negative temperature coefficient currents and implementing secondary temperature compensation.

[0049] One input terminal for inputting negative temperature coefficient compensation current is connected between resistor R7 and resistor R8; and one input terminal for inputting positive temperature coefficient compensation current is connected between resistor R8 and resistor R9.

[0050] The compensation circuit includes multiple comparators for integrating positive and negative temperature coefficient currents and implementing secondary temperature compensation.

[0051] Current superposition and first-order compensation: MOS transistor M5, MOS transistor M2 and MOS transistor M1 form a current mirror to copy negative temperature coefficient current; MOS transistor M7, MOS transistor M3 and MOS transistor M4 form a current mirror to copy positive temperature coefficient current. The two currents are superposed at resistor R3 to form a reference current with approximately zero temperature coefficient, like first-order compensation, the temperature coefficient is about 20ppm / ℃.

[0052] Voltage conversion: the superposed reference current is converted into a reference voltage through resistor network R3-R6, R7-R9, wherein MOS transistor M6, MOS transistor M8, MOS transistor M5 and MOS transistor M7 form a mirror relationship to ensure current stability, and finally output VREF at the connection point of MOS transistor M6, MOS transistor M8 and resistor R7.

[0053] Secondary compensation: the comparators monitor "voltage 1" between resistor R4 and resistor R5, "voltage 2" between resistor R5 and resistor R6 and the proportionally reduced value of the reference voltage, respectively. When the temperature is lower than the set threshold, the comparators detect that the negative temperature coefficient component is dominant, and inject negative temperature coefficient compensation current through the input terminal between resistor R7 and resistor R8; when the temperature is higher than the set threshold, the comparators detect that the positive temperature coefficient component is dominant, and inject positive temperature coefficient compensation current through the input terminal between resistor R8 and resistor R9. After two times of jump compensation, the temperature coefficient of VREF is reduced to below 5ppm / ℃.

[0054] As Figures 2-4 shown, the first-order curve is approximately a parabola opening upward with a temperature coefficient of about 20ppm / ℃, and after comparison, the temperature of the jump point is compensated, as Figure 3 shown, two jumps occur, that is, one compensation is performed on the left and right of the original parabola, and the second compensation can make the temperature coefficient reach below 5ppm / ℃, and the fourth compensation can approach 1ppm / ℃.

[0055] The embodiment is a current mode CMOS reference circuit, and the reference current can be converted into a reference voltage through a resistance network in the mirror reference voltage generator. By adjusting the resistance ratio of the resistance network, the size of the output reference voltage VREF can be freely set to meet the diversified needs of reference voltages of different circuit systems and improve the versatility of the circuit.

[0056] The MOS transistor in the circuit core of the embodiment works in the sub-threshold region, and the drain current of the MOS transistor in the sub-threshold region changes exponentially with the gate-source voltage, which can maintain stable operation at a lower current, significantly reducing the static power consumption of the circuit, and is suitable for low-power chip design scenarios.

[0057] The principle of the embodiment is as follows: the MOS transistor with a thin gate generates a negative temperature coefficient voltage in the sub-threshold region, and through the clamping action of the operational amplifier, the positive and negative input voltages of the operational amplifier are equal, and then the temperature coefficient of the negative temperature coefficient current is controlled through the resistance, and finally the negative temperature coefficient current is copied by the current mirror. At the same time, the beta multiplier generates a positive temperature coefficient voltage through two asymmetric MOS transistors in the sub-threshold region, through the principle that the currents at both ends of the current mirror are equal, and in combination with the characteristics of the MOS transistor in the sub-threshold region, and then the temperature coefficient and the current size of the positive temperature coefficient voltage are controlled through the resistance, which is also copied by the current mirror. Finally, the positive and negative temperature coefficient currents are added, the positive and negative are offset to achieve a reference current close to zero temperature coefficient, which can generate a low-temperature coefficient reference voltage source through the resistance, or directly generate a low-temperature coefficient current reference source, and then compare the negative voltage and the scaled reference voltage source, and the positive voltage and the scaled reference voltage source through the comparator, respectively. Through the result of the size comparison, the temperature coefficient of the reference source is made to be lower by increasing the compensation current.

[0058] Reference is made to the accompanying Figure 1The circuit of the negative temperature coefficient current generator and the beta multiplier, the main difference of the thin-thick gate MOS tube in the embodiment is that the MOS tube M9 and the MOS tube M10 are a pair of MOS tubes, and the MOS tube M12 and the MOS tube M13 are another pair of MOS tubes, the width-length ratio of the MOS tube M9 and the MOS tube M10 is K, and the width-length ratio of the MOS tube M12 and the MOS tube M13 is also K, so that the voltage at the input end of the error amplifier is the value of the coefficient containing lnk and-link, that is, the positive and negative voltages, and the proportion of the two pairs of tubes is ensured to be the same to ensure a lower first-order TC.

[0059] The embodiment has the two characteristics of low voltage and small area, and the comparator is used for compensation, so that further compensation of the temperature coefficient can be realized under low voltage, good temperature coefficient functions can be realized under low power consumption and small area, and the current mode CMOS reference circuit can freely set the output voltage size.

[0060] The above merely describes a preferred specific embodiment of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A small area current mode (CMOS) voltage reference circuit, characterized by: The bias circuit generator generates stable bias voltages VB1 and VB2 by a multi-stage MOS tube current mirror, provides gate bias for the negative temperature coefficient current generator and the beta multiplier, and makes the corresponding MOS tube in the sub-threshold region. The negative temperature coefficient current generator outputs a negative temperature coefficient current, which is transmitted to the beta multiplier and the mirror reference voltage generator as a temperature-compensated negative temperature coefficient. The beta multiplier multiplies the received current to generate a positive temperature coefficient current and output it to the mirror reference voltage generator. The mirror reference voltage generator integrates the negative temperature coefficient current and the positive temperature coefficient current, and finally outputs a reference voltage with low temperature coefficient at VREF through voltage / current superposition.

2. A small-area current-mode CMOS voltage reference circuit as claimed in claim 1, characterized in that: The bias circuit generator includes MOS tubes M12, M13, M14, M15, M16, M17 and a resistor R10, wherein the sources of MOS tubes M12 and M13 are connected to a power supply VDD, the gates of MOS tubes M12 and M13 are connected to a bias voltage VB1, the gate of MOS tube M12 is shorted to the drain of itself, the drain of MOS tube M14 is connected to the drain of MOS tube M12, the gate of MOS tube M14 is connected to the gate of MOS tube M15, the gate of MOS tube M15 is shorted to the drain of itself, the drain of MOS tube M15 is connected to the drain of MOS tube M13, the drain of MOS tube M16 is connected to the source of MOS tube M14, the gates of MOS tubes M16 and M17 are connected to a bias voltage VB2, the gate of MOS tube M17 is shorted to the drain of itself, the source of MOS tube M17 is connected to ground, and one end of the resistor R10 is connected to the source of MOS tube M16 and the other end is connected to ground.

3. A small-area current-mode CMOS voltage reference circuit as claimed in claim 2, characterized in that: The negative temperature coefficient current generator includes MOS tubes M1, M2, M9, M10, M11, a resistor R1 and a first operational amplifier, wherein the sources of MOS tubes M1 and M2 are connected to a power supply VDD, the gates of MOS tubes M1 and M2 are connected to the positive output terminal of the first operational amplifier, the drain of MOS tube M1 is connected to the drain of MOS tube M9, the gate of MOS tube M9 is connected to the drain of itself and the gate of MOS tube M10, the drain of MOS tube M10 and the source of MOS tube M9 are connected to the negative input terminal of the first operational amplifier, the source of MOS tube M10 is connected to ground, the drain of MOS tube M2 is connected to the drain of MOS tube M11, the gate of MOS tube M11 is shorted to the drain of itself, the source of MOS tube M11 and one end of the resistor R1 are connected to the positive input terminal VP of the first operational amplifier, a comparator is connected between MOS tube M11 and the resistor R1, and the other end of the resistor R1 is connected to ground.

4. A small-area current-mode CMOS voltage reference circuit as claimed in claim 3, characterized in that: The beta multiplier comprises MOS tubes M3, M4, M18, M19, a resistor R2 and a second operational amplifier, wherein the sources of the MOS tubes M3 and M4 are connected to a power supply VDD, the gates of the MOS tubes M3 and M4 are connected to a negative output terminal VN of the second operational amplifier, the drain of the MOS tube M3 is connected to the drain and the gate of the MOS tube M18 and a negative input terminal of the second operational amplifier, the drain of the MOS tube M18 is connected to the gate of the MOS tube M18, the source of the MOS tube M18 is connected to ground, the drain of the MOS tube M4 is connected to the drain of the MOS tube M19 and a positive input terminal of the first operational amplifier, the gate of the MOS tube M19 is connected to the gate of the MOS tube M18, one end of the resistor R2 is connected to the source of the MOS tube M19, and the other end of the resistor R2 is connected to ground.

5. A small-area current-mode CMOS voltage reference circuit as claimed in claim 4, characterized in that: The mirror reference voltage generator comprises MOS tubes M5, M7, resistors R3, R4, R5 and R6, wherein the sources of the MOS tubes M5 and M6 are connected to the power supply VDD, the gate of the MOS tube M5 is connected to the gate of the MOS tube M2, the gate of the MOS tube M1 and a positive output terminal VP of the first operational amplifier, the drain of the MOS tube M5 is connected to the resistor R3 and the drain of the MOS tube M7, the gate of the MOS tube M7 is connected to the gate of the MOS tube M3, the gate of the MOS tube M4 and a negative output terminal VN of the second operational amplifier, the resistors R3, R4, R5 and R6 are connected in series, the other end of the resistor R6 is connected to ground, and comparators are connected between the resistor R4 and the resistor R5 and between the resistor R5 and the resistor R6.

6. A small-area current-mode CMOS voltage reference circuit as claimed in claim 5, characterized in that, The mirror reference voltage generator further comprises MOS tubes M6, M8, resistors R7, R8 and R9, wherein the sources of the MOS tubes M6 and M8 are connected to the power supply VDD, the gate of the MOS tube M6 is connected to the gate of the MOS tube M5, the gate of the MOS tube M2, the gate of the MOS tube M1 and the positive output terminal VP of the first operational amplifier, the drain of the MOS tube M6 is connected to the drain of the MOS tube M8 and one end of the resistor R7, the gate of the MOS tube M8 is connected to the gate of the MOS tube M7, the gate of the MOS tube M3, the gate of the MOS tube M4 and the negative output terminal VN of the second operational amplifier, the resistors R7, R8 and R9 are connected in series, and the other end of the resistor R9 is connected to ground.

7. A small-area current-mode CMOS voltage reference circuit as claimed in claim 6, characterized in that: The MOS tube M6, the MOS tube M8 and the resistor R7 are connected to an output terminal VREF.

8. A small-area current-mode CMOS voltage reference circuit as claimed in claim 6, characterized in that: The resistor R7 and the resistor R8 are connected to an input terminal for inputting a negative temperature coefficient compensation current, and the resistor R8 and the resistor R9 are connected to an input terminal for inputting a positive temperature coefficient compensation current.

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