Data alignment circuit and alignment method for multichannel data transmission
By using a combination of first-in-first-out (FIFO) storage circuits and readout control circuits in multi-channel data transmission, the misalignment problem caused by inconsistent data arrival times is solved, achieving high-precision data alignment, which is suitable for FPGA or ASIC chips.
Patent Information
- Application Number
- CN202511091676.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-05
- Publication Date
- 2025-11-21
AI Technical Summary
Existing multi-channel data transmission methods still suffer from data misalignment when there is a significant time difference in data arrival, leading to image misalignment or errors.
By employing n first-in-first-out (FIFO) memory circuits and one read control circuit, the alignment of multi-channel data is achieved through the buffering characteristics of the FIFO memory circuits and the write/read flag bits.
It effectively avoids data misalignment problems caused by data misalignment, and has high data alignment accuracy and is easy to modularly apply to FPGA or ASIC chips.
Smart Images
Figure CN120994160A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to data alignment circuits and methods, specifically to a data alignment circuit and method for multi-channel data transmission. Background Technology
[0002] Multichannel data transmission is widely used in data transmission systems for remote real-time imaging, such as image sensor data output and high-speed fiber optic data transmission. Due to factors such as serial-to-parallel conversion and latency, data from different channels does not arrive at the receiving end simultaneously. If the multichannel data is not aligned, the received data will be misaligned, leading to image misalignment or errors. Existing multichannel data alignment methods often use registers for buffering. This method works well when data arrival times are similar, but misalignment still occurs when arrival times differ significantly. Therefore, a more reliable data alignment circuit and method are needed for multichannel data transmission. Summary of the Invention
[0003] The purpose of this invention is to solve the technical problem that existing multi-channel data alignment methods using registers for caching still result in data misalignment when the data arrival times differ significantly, and to provide a data alignment circuit and alignment method for multi-channel data transmission.
[0004] To achieve the above objectives, the technical solution provided by the present invention is as follows:
[0005] A data alignment circuit for multi-channel data transmission is characterized in that it includes n first-in-first-out storage circuits and a readout control circuit, where n≥2;
[0006] The first-in-first-out (FIFO) storage circuit has a data write-first-read-first function. The n FIFO storage circuits respectively include a data write port, a write enable port, a data read port, a read enable port, a storage empty signal port, a write clock port, a read clock port, and a reset port; the read control circuit includes n storage empty receive ports, one read enable generation port, n data receive ports, one aligned data output port, and one valid flag port;
[0007] Each of the n data write ports is used to receive input data DATA_IN corresponding to the n channels;
[0008] The n write enable ports are used to receive the write enable signals WR_EN corresponding to the n channels, and to write the input data DATA_IN of the corresponding channel when the write enable signal WR_EN is high.
[0009] The n empty storage signal ports are used to output the corresponding empty storage flag signal EMPRTY according to the storage state of the corresponding first-in-first-out storage circuit; the n empty storage receiving ports are connected to the n empty storage signal ports respectively, and are used to receive the empty storage flag signals output by the n empty storage signal ports; the read enable generation port is used to generate and output the read enable signal RD_EN according to the empty storage flag signal.
[0010] Each of the n read enable ports is connected to a read enable generation port, which is used to receive the read enable signal RD_EN respectively, and to determine whether to read the data stored in the n first-in-first-out storage circuits based on the read enable signal RD_EN.
[0011] The n data readout ports are used to read out the data stored in the n first-in-first-out storage circuits, and are denoted as n output data DATA_OUT;
[0012] The n write clock ports are used to receive external write clock signals WR_CLK; the n read clock ports are used to receive external read clock signals RD_CLK; and the n reset ports are used to receive external reset enable signals RESET and reset the stored data according to the reset enable signals RESET.
[0013] n data receiving ports are connected to n data reading ports respectively, and are used to receive the output data DATA_OUT read from the corresponding first-in-first-out storage circuit;
[0014] The aligned data output port is used to output the data received from the n data receiving ports as M×n-bit aligned data DATA, where M is the number of bits of the input data DATA_IN;
[0015] The valid flag port is used to output the alignment data valid flag signal DATA_VALID.
[0016] Furthermore, the output logic of the n empty storage signal ports is as follows: the empty storage signal port output by the empty storage signal port of the first-in-first-out storage circuit that stores data is at a low level, and the empty storage signal port output by the empty storage signal port of the first-in-first-out storage circuit that stores no data is at a high level.
[0017] Furthermore, when the read enable signal RD_EN received by the read enable port is high, the stored n M-bit data are read out.
[0018] Furthermore, the data is reset when the reset enable signal RESET received by the reset port is high.
[0019] Furthermore, when the alignment data validity flag signal DATA_VALID output by the validity flag port is high, it indicates that the data is valid.
[0020] In addition, the present invention also provides a data alignment method for multi-channel data transmission, which is characterized by including the following steps:
[0021] Step 1: Construct the data alignment circuit described above for multi-channel data transmission;
[0022] Step 2: Set the reset enable signal RESET of each of the n first-in-first-out storage circuits to high level, clear the data, and then set the reset enable signal RESET to low level.
[0023] Step 3: Write the M-bit input data DATA_IN corresponding to the first-in-first-out (FIFO) memory circuits in the n FIFO memory circuits where the write enable signal WR_EN is high through the corresponding data write ports. Do not write to the FIFO memory circuits where the write enable signal WR_EN is low.
[0024] Step 4: When the storage empty flag signal EMPTY of the n first-in-first-out storage circuits is low, the read enable signal RD_EN output by the read enable generation port of the read control circuit is high; otherwise, the read enable signal RD_EN output by the read enable generation port is low.
[0025] Step 5: When the read enable signal RD_EN received by the n first-in-first-out storage circuits is high, the n data readout ports read out the n M-bit data stored; otherwise, they do not read out the data. The alignment data output port of the readout control circuit integrates the data read out by the n data readout ports into M×n-bit alignment data DATA, and sets the alignment data valid flag signal DATA_VALID to high.
[0026] Step 6: n FIFO memory circuits repeat step 3 in each write clock cycle, and n FIFO memory circuits and read control circuits repeat steps 4-5 in each read clock cycle until all channel data is aligned and read out.
[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0028] 1. The present invention provides a data alignment circuit for multi-channel data transmission. A first-in-first-out (FIFO) storage circuit is set in each channel for initial data reception, and a readout control circuit is set to control the reading of the FIFO storage circuit. By utilizing the buffering characteristics of the FIFO storage circuit and the write and readout flag bits, multi-channel data alignment can be accurately achieved, effectively avoiding data misalignment and other problems caused by data misalignment.
[0029] 2. The present invention provides a data alignment circuit for multi-channel data transmission, which can be modularly called and is easy to implement in FPGA or ASIC chips, making it convenient for large-scale promotion and application.
[0030] 3. The present invention provides a data alignment method for multi-channel data transmission. The readout control circuit determines whether to read out by judging whether all first-in-first-out storage circuits are empty, and at the same time indicates whether the readout data is valid. The data alignment accuracy is high and the implementation is simple and convenient. Attached Figure Description
[0031] Figure 1 This is a schematic diagram of a data alignment circuit for multi-channel data transmission according to the present invention;
[0032] Figure 2 This is a schematic diagram illustrating step 6 of an embodiment of a data alignment method for multi-channel data transmission according to the present invention, where all channel data is read out in alignment. Detailed Implementation
[0033] To make the advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0034] The inventive concept of this invention is to use the valid flag bit of each channel data to determine whether the data is stored in the cache circuit, and then use the non-empty flag of all cache circuits to determine whether the data is read out, thereby realizing the alignment of multi-channel data.
[0035] like Figure 1 As shown, a data alignment circuit for multi-channel data transmission includes n first-in-first-out (FIFO) memory circuits and a readout control circuit (CONTROLLER), where n = 4 in this embodiment.
[0036] The first-in-first-out (FIFO) memory circuit features a data write-first-read-first-out (FIFO) function. Each FIFO memory circuit includes a data write port, a write enable port, a data read port, a read enable port, a memory empty signal port, a write clock port, a read clock port, and a reset port. The read control circuit includes four memory empty receive ports, one read enable generation port, four data receive ports, one aligned data output port, and one valid flag port.
[0037] The four data write ports are used to receive the input data DATA_IN corresponding to the four channels, each with the same number of bits, denoted as M bits. The four write enable ports are used to receive the write enable signal WR_EN corresponding to the four channels. When the write enable signal WR_EN is high, it indicates that the input data DATA_IN of that channel is valid, and the input data DATA_IN of that channel is written and stored.
[0038] The four empty signal ports are used to output the corresponding empty flag signal EMPRTY according to the storage state of the corresponding FIFO storage circuit. Specifically, the output logic of the four empty signal ports is as follows: the empty signal port of the FIFO storage circuit that stores data outputs the empty flag signal EMPRTY at a low level, and the empty signal port of the FIFO storage circuit that is empty outputs the empty flag signal EMPRTY at a high level.
[0039] The four empty memory receiving ports of the read control circuit are respectively connected to the empty memory signal ports of the four FIFO memory circuits to receive the empty memory flag signals output by the four empty memory signal ports. The read enable generation port of the read control circuit generates and outputs a read enable signal RD_EN based on the empty memory flag signal, which is then provided to the four FIFO memory circuits. The read enable ports of the four FIFO memory circuits are all connected to the read enable generation port of the read control circuit to receive the read enable signal RD_EN and determine whether to read the four M bits of stored data in the four FIFO memory circuits based on the read enable signal RD_EN; specifically, the four M bits of stored data are read when the read enable signal RD_EN received by the read enable port is high, and not read when the read enable signal RD_EN is low.
[0040] Four FIFO (First-In, First-Out) memory circuit data read ports are used to read the corresponding stored data, and the four read data are recorded as output data DATA_OUT; four write clock ports are used to receive external write clock signals WR_CLK; four read clock ports are used to receive external read clock signals RD_CLK. Four reset ports are used to receive external reset enable signals RESET, and reset the stored data according to the reset enable signal RESET, clearing the stored data after the reset; specifically, the data is reset when the reset enable signal RESET is high, and is usually low when no data reset is needed.
[0041] The four data receiving ports of the readout control circuit are connected to the four data reading ports respectively, and are used to receive the four output data DATA_OUT read from the corresponding FIFO memory circuits. The aligned data output port is used to output the data received by the four data receiving ports as M×n bit aligned data DATA. The valid flag port is used to output the aligned data valid flag signal DATA_VALID. When the aligned data valid flag signal DATA_VALID is high, it indicates that the data is valid.
[0042] Based on the data alignment circuit described above for multi-channel data transmission, the present invention also provides a data alignment method for multi-channel data transmission, specifically including the following steps:
[0043] Step 1: Construct the data alignment circuit described above for multi-channel data transmission;
[0044] Step 2: Set the reset enable signal RESET of the four FIFO storage circuits to high level, clear the data, and then set the reset enable signal RESET to low level.
[0045] Step 3: Write the M-bit input data DATA_IN corresponding to the first-in-first-out (FIFO) memory circuits in the four FIFO memory circuits where the write enable signal WR_EN is high through the corresponding data write ports. Do not write to the FIFO memory circuits where the write enable signal WR_EN is low.
[0046] Step 4: When the storage empty flag signal EMPTY of the four first-in-first-out storage circuits is low, the read enable signal RD_EN output by the read enable generation port of the read control circuit is high; otherwise, the read enable signal RD_EN output by the read enable generation port is low.
[0047] Step 5: When the read enable signal RD_EN received by the four FIFO storage circuits is high, the four data readout ports read out the four M-bit data stored. When the read enable signal RD_EN received by the four FIFO storage circuits is low, the data readout ports do not read out.
[0048] The aligned data output port of the readout control circuit integrates the data output from the four data readout ports into M×4-bit aligned data DATA, and sets the aligned data valid flag signal DATA_VALID to a high level.
[0049] Step 6: The four FIFO memory circuits repeat step 3 in each write clock cycle, and the four FIFO memory circuits and the read control circuit repeat steps 4-5 in each read clock cycle until all channel data is aligned and read out.
[0050] like Figure 2 The diagram shows the process of processing data from four-channel data transmission using the alignment method of this invention. BR_DATA_OUT, TR_DATA_OUT, BL_DATA_OUT, and TL_DATA_OUT are the four unaligned input channels, FRM_BUF_DATA is the aligned data after processing by this invention, and FRM_BUF_VALID is the valid alignment flag signal. It can be seen that all channel data processed by the alignment method of this invention can be read out in alignment.
[0051] This invention relates to a data alignment circuit and method for multi-channel data transmission. Each channel includes a first-in-first-out (FIFO) storage circuit for initial data reception, and a readout control circuit to control the reading out of the FIFO storage circuit. The readout control circuit determines whether to read out data by checking if all FIFO storage circuits are empty, and also indicates whether the read data is valid. This effectively solves the problems of image misalignment caused by data misalignment when using multi-channel data transmission with image sensors and other devices.
[0052] The above description is only used to illustrate the technical solutions of the present invention, and is not intended to limit them. For those skilled in the art, modifications can be made to the specific technical solutions described in the above embodiments, or equivalent substitutions can be made to some of the technical features. However, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions protected by the present invention.
Claims
1. A data alignment circuit for multi-channel data transmission, characterized in that: It includes n first-in-first-out storage circuits and one readout control circuit, where n≥2; The first-in-first-out (FIFO) storage circuit has the function of writing and reading data first. The n FIFO storage circuits include a data write port, a write enable port, a data read port, a read enable port, a storage empty signal port, a write clock port, a read clock port, and a reset port. The readout control circuit includes n memory empty receive ports, one read enable generation port, n data receive ports, one aligned data output port, and one valid flag port. Each of the n data write ports is used to receive input data DATA_IN corresponding to the n channels; The n write enable ports are used to receive the write enable signals WR_EN corresponding to the n channels, and to write the input data DATA_IN of the corresponding channel when the write enable signal WR_EN is high. The n empty storage signal ports are respectively used to output the corresponding empty storage flag signal EMPRTY according to the storage state of the corresponding first-in-first-out storage circuit. The n memory empty receiving ports are respectively connected to the n memory empty signal ports and are used to receive the memory empty flag signals output by the n memory empty signal ports; the read enable generating port is used to generate and output the read enable signal RD_EN according to the memory empty flag signal. Each of the n read enable ports is connected to a read enable generation port, which is used to receive the read enable signal RD_EN respectively, and to determine whether to read the data stored in the n first-in-first-out storage circuits based on the read enable signal RD_EN. The n data readout ports are used to read out the data stored in the n first-in-first-out storage circuits, and the readout data is recorded as output data DATA_OUT; The n write clock ports are used to receive external write clock signals WR_CLK; the n read clock ports are used to receive external read clock signals RD_CLK; and the n reset ports are used to receive external reset enable signals RESET and reset the stored data according to the reset enable signals RESET. n data receiving ports are connected to n data reading ports respectively, and are used to receive the output data DATA_OUT read from the corresponding first-in-first-out storage circuit; The aligned data output port is used to output the data received from the n data receiving ports as M×n-bit aligned data DATA, where M is the number of bits of the input data DATA_IN; The valid flag port is used to output the alignment data valid flag signal DATA_VALID.
2. The data alignment circuit for multi-channel data transmission according to claim 1, characterized in that: The output logic of the n empty storage signal ports is as follows: the empty storage signal port of the first-in-first-out (FIFO) storage circuit that stores data outputs the empty storage flag signal EMPRTY at a low level, and the empty storage signal port of the first-in-first-out (FIFO) storage circuit that stores no data outputs the empty storage flag signal EMPRTY at a high level.
3. The data alignment circuit for multi-channel data transmission according to claim 2, characterized in that: When the read enable signal RD_EN received by the read enable port is high, the stored n M-bit data are read out.
4. The data alignment circuit for multi-channel data transmission according to claim 3, characterized in that: The data is reset when the reset enable signal RESET received by the reset port is high.
5. The data alignment circuit for multi-channel data transmission according to claim 4, characterized in that: When the alignment data validity flag signal DATA_VALID output by the validity flag port is high, it indicates that the data is valid.
6. A data alignment method for multi-channel data transmission, characterized in that, Includes the following steps: Step 1: Construct a data alignment circuit for multi-channel data transmission as described in any one of claims 1-5; Step 2: Set the reset enable signal RESET of each of the n first-in-first-out storage circuits to high level, clear the data, and then set the reset enable signal RESET to low level. Step 3: Write the M-bit input data DATA_IN corresponding to the first-in-first-out (FIFO) memory circuits in the n FIFO memory circuits where the write enable signal WR_EN is high through the corresponding data write ports. Do not write to the FIFO memory circuits where the write enable signal WR_EN is low. Step 4: When the storage empty flag signal EMPTY of the n first-in-first-out storage circuits is low, the read enable signal RD_EN output by the read enable generation port of the read control circuit is high; otherwise, the read enable signal RD_EN output by the read enable generation port is low. Step 5: When the read enable signal RD_EN received by the n first-in-first-out storage circuits is high, the n data readout ports read out the n M-bit data stored; otherwise, they do not read out the data. The alignment data output port of the readout control circuit integrates the data read out by the n data readout ports into M×n-bit alignment data DATA, and sets the alignment data valid flag signal DATA_VALID to high. Step 6: n FIFO memory circuits repeat step 3 in each write clock cycle, and n FIFO memory circuits and read control circuits repeat steps 4-5 in each read clock cycle until all channel data is aligned and read out.