Level conversion circuit, memory, memory system and electronic equipment

Abstract

The embodiment of the invention provides a level conversion circuit, a memory, a memory system and electronic equipment. The level conversion circuit comprises an input circuit, a conversion circuit and an output circuit which are coupled in sequence, wherein the input circuit is configured to generate a first input signal in response to a first level signal; the adjusting circuit is respectively coupled with the input circuit and the conversion circuit; wherein the adjusting circuit is configured to respond to a first input signal and adjust a first control signal output by the conversion circuit; wherein the voltage domain of the conversion circuit is different from the voltage domain of the input circuit; the output circuit is configured to output a second level signal in response to the adjusted first control signal; wherein the level value of the second level signal is greater than the level value of the first level signal.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a level conversion circuit, a memory, a memory system, and an electronic device. Background Technology

[0002] In recent years, the integrated circuit industry has experienced rapid development. With the continuous advancement of semiconductor manufacturing processes, the feature size of semiconductor components has been shrinking, and their integration density has been increasing. Due to the growing demand from the consumer market for high-performance, high-speed, and multifunctional semiconductor equipment, various components in semiconductor equipment may operate in multiple different voltage domains.

[0003] A level shifter is an essential circuit in a multi-voltage system. It provides interaction between circuits in different voltage domains and ensures the normal transmission of signals in different voltage domains. Summary of the Invention

[0004] This disclosure provides a level conversion circuit, a memory, a memory system, and an electronic device.

[0005] In a first aspect, this disclosure provides a level conversion circuit, comprising:

[0006] An input circuit, a conversion circuit, and an output circuit are coupled in sequence; wherein the input circuit is configured to generate a first input signal in response to a first level signal;

[0007] An adjustment circuit is coupled to the input circuit and the conversion circuit respectively; wherein the adjustment circuit is configured to: adjust the first control signal output by the conversion circuit in response to the first input signal; wherein the voltage domain of the conversion circuit is different from the voltage domain of the input circuit.

[0008] The output circuit is configured to output a second level signal in response to the adjusted first control signal; wherein the level value of the second level signal is greater than the level value of the first level signal.

[0009] In some embodiments, the input circuit is specifically configured to: generate a first input signal that is inversely phase to the first level signal in response to the first level signal; wherein, the first output terminal of the input circuit is used to output the first input signal;

[0010] The conversion circuit includes a feedback circuit, which is coupled to a first power supply terminal and a first node of the conversion circuit; wherein the feedback circuit is configured to provide the power level of the first power supply terminal to the first node.

[0011] The regulating circuit includes: a first branch coupled to the first node and a first output terminal of the input circuit; wherein the first branch is configured to: discharge the first node in response to the first input signal, thereby regulating the first control signal output by the conversion circuit.

[0012] In some embodiments, the input circuit is further configured to: generate a second input signal that is inversely phase to the first input signal in response to the first input signal; wherein the second output terminal of the input circuit is used to output the second input signal;

[0013] The adjustment circuit further includes a second branch, which is coupled to a second node of the conversion circuit and a second output terminal of the input circuit; wherein the second branch is configured to: adjust the level of the second node in response to the second input signal, so that the feedback circuit stops providing the power level to the first node; the feedback circuit is coupled to the first power terminal and the second node respectively.

[0014] In some embodiments, the second branch is specifically configured to charge the second node in response to the second input signal until the first node and the first power supply are disconnected.

[0015] In some embodiments, the feedback circuit includes:

[0016] A first transistor, wherein a first terminal of the first transistor is coupled to the first power supply terminal, a second terminal of the first transistor is coupled to the first node, and a control terminal of the first transistor is coupled to the second node;

[0017] The second transistor has a first terminal coupled to the first power supply terminal, a second terminal coupled to the second node, and a control terminal coupled to the first node.

[0018] In some embodiments, the first branch includes a first capacitor; the second branch includes a second capacitor.

[0019] In some embodiments, the conversion circuit further includes a pull-down circuit; the pull-down circuit includes:

[0020] The third transistor has a first terminal coupled to the first node, a second terminal coupled to ground, and a control terminal coupled to the second output terminal of the input circuit.

[0021] A fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second node, a second terminal of the fourth transistor is coupled to the ground terminal, and a control terminal of the fourth transistor is coupled to the first output terminal of the input circuit.

[0022] In some embodiments, the threshold voltage of the third transistor is greater than the level value of the second input signal.

[0023] In some embodiments, the third transistor and the fourth transistor are NMOS transistors; the input circuit includes at least one NMOS transistor; wherein the threshold voltage of the third transistor and the threshold voltage of the fourth transistor are the same as the threshold voltage of the NMOS transistor in the input circuit.

[0024] In some embodiments, the input circuit includes at least one inverter.

[0025] In a second aspect, this disclosure provides a memory, the memory including a page buffer circuit, a control logic circuit, and a level shifting circuit, the level shifting circuit being coupled between the control logic circuit and the page buffer circuit; the level shifting circuit includes:

[0026] A first inverter and a second inverter connected in series; the first inverter is configured to generate a first input signal in response to a first level signal output by the control logic circuit.

[0027] A first transistor, wherein a first terminal of the first transistor is coupled to a first power supply terminal, a second terminal of the first transistor is coupled to a first node, and a control terminal of the first transistor is coupled to a second node; the voltage of the second power supply terminal to which the first inverter is coupled is different from the voltage of the first power supply terminal.

[0028] The second transistor has a first terminal coupled to the first power supply terminal, a second terminal coupled to the second node, and a control terminal coupled to the first node.

[0029] A first capacitor is coupled to the first node and the output of the first inverter; the first capacitor is configured to: adjust a first control signal output through the first node in response to the first input signal.

[0030] The second capacitor is coupled to the second node and the output of the second inverter;

[0031] A third inverter, coupled to the first node, is configured to output a second level signal in response to the adjusted first control signal, wherein the level value of the second level signal is greater than the level value of the first level signal.

[0032] In some embodiments, the second inverter is configured to generate a second input signal in response to the first input signal;

[0033] The second capacitor is configured to: adjust the level of the second node in response to the second input signal, thereby turning off the first transistor.

[0034] In some embodiments, the first capacitor is specifically configured to: discharge the first node in response to the first input signal, thereby adjusting the first control signal output by the first node;

[0035] The second capacitor is configured to charge the second node in response to the second input signal until the first transistor is turned off.

[0036] In some embodiments, the level conversion circuit further includes:

[0037] The third transistor has a first terminal coupled to the first node, a second terminal coupled to ground, and a control terminal coupled to the output terminal of the second inverter.

[0038] A fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second node, a second terminal of the fourth transistor is coupled to the ground terminal, and a control terminal of the fourth transistor is coupled to the output terminal of the first inverter.

[0039] In some embodiments, the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.

[0040] In some embodiments, the threshold voltage of the third transistor is greater than the level value of the second input signal.

[0041] In some embodiments, the third transistor and the fourth transistor are NMOS transistors; the threshold voltage of the third transistor, the threshold voltage of the fourth transistor, the threshold voltage of the NMOS transistor in the first inverter, and the threshold voltage of the NMOS transistor in the second inverter are all the same.

[0042] In some embodiments, the page buffer circuit includes a bias circuit; the level shifting circuit is coupled between the bias circuit and the control logic circuit;

[0043] The bias circuit is configured to apply a bias voltage to the bit line in response to the second level signal.

[0044] Thirdly, this disclosure provides a memory system, comprising:

[0045] The memory described in any of the above embodiments;

[0046] A memory controller, coupled to the memory.

[0047] Fourthly, this disclosure provides an electronic device, including: the memory system described in the above embodiments.

[0048] In this embodiment, the voltage domain of the conversion circuit differs from that of the input circuit. The adjustment circuit is configured to adjust the first control signal output by the conversion circuit in response to the first input signal; the output circuit is configured to output a second-level signal in response to the adjusted first control signal. Thus, when there is a significant voltage difference between the power supply voltage coupled to the conversion circuit and the power supply voltage coupled to the input circuit, the adjustment circuit can adjust the level of the first control signal, allowing the level of the first control signal to flip normally. This ensures that the output circuit can output a second-level signal with a higher level, thereby improving the reliability of the level conversion circuit. Attached Figure Description

[0049] Figure 1 A schematic diagram of a system with a memory provided for an embodiment of this disclosure;

[0050] Figure 2a A schematic diagram of a memory card provided in an embodiment of this disclosure;

[0051] Figure 2b A schematic diagram of a solid state drive (SSD) provided in an embodiment of this disclosure;

[0052] Figure 3 A schematic diagram of a memory provided for an embodiment of this disclosure;

[0053] Figure 4 A schematic diagram of a level conversion circuit provided in an embodiment of this disclosure;

[0054] Figure 5 A timing diagram of the level levels of each node in a level conversion circuit provided in an embodiment of this disclosure;

[0055] Figure 6 A schematic diagram of another level conversion circuit provided in an embodiment of this disclosure;

[0056] Figure 7 A schematic diagram of the adjustment circuit in another level conversion circuit provided in this embodiment of the present disclosure;

[0057] Figure 8 A circuit diagram of another level conversion circuit provided in an embodiment of this disclosure;

[0058] Figure 9 A timing diagram of the node levels of another level conversion circuit provided in an embodiment of this disclosure;

[0059] Figure 10 A circuit diagram of yet another level conversion circuit provided in an embodiment of this disclosure;

[0060] Figure 11 This is a schematic diagram of a bias circuit in a page buffer circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0061] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0062] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described herein.

[0063] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0064] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0065] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0066] Figure 1 A schematic diagram of an electronic device 100 having memory according to some aspects of this disclosure is shown. The electronic device 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0067] like Figure 1 As shown, electronic device 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.

[0068] According to some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital Memory Card (SD Card), Compact Flash Card (CFCard), Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as solid-state drives (SSDs) or embedded multi-media cards (eMMCs), used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0069] Memory controller 106 can be configured to control operations of memory 104, such as read, erase, and write (also known as programming) operations. Memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, memory controller 106 is also configured to process error correction codes (ECCs) relating to data read from or written to memory 104. Memory controller 106 can also perform any other suitable functions, such as formatting memory 104. Memory controller 106 can communicate with a host (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the host 108 through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Express (PCIE), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced System Device Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0070] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a general-purpose flash memory package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Reduced-Size MMC (RS-MMC), a Multimedia Card Micro (MMCmicro), an SD card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0071] In the embodiments of this disclosure, the memory can be NAND flash memory. However, it should be understood that the level conversion circuit provided in this disclosure is not limited to applications in NAND flash memory, but can be applied to other types of memory devices, such as electrically erasable programmable read-only memory (EEPROM), NOR flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. In other embodiments, the level conversion circuit provided in this disclosure can be applied not only to memory, but also to any other type of electronic device containing digital circuitry, such as processors, controllers, programmable logic devices, etc.

[0072] Figure 3 A schematic diagram of a memory provided in an embodiment of this disclosure, such as... Figure 3As shown, the memory 300 includes a memory cell array 310 and peripheral circuitry 320. The memory 300 includes, but is not limited to, NAND flash memory. Exemplarily, the memory cell array 310 may include different types of memory cells, such as Single-Level Cell (SLC), Multi-Level Cell (MLC), Trinary-Level Cell (TLC), Quad-Level Cell (QLC), and Penta-Level Cell (PLC). The peripheral circuitry 320 can be coupled to each memory cell in the memory cell array 310 via multiple word lines (WL) and multiple bit lines (BL). The peripheral circuitry 320 may include a page buffer (PB) circuit 321, a column decoder / bit line driver 322, a row decoder / word line driver 323, a voltage generator 324, control logic circuitry 325, a register 326, an interface 327, and a data bus 328. In other embodiments, the peripheral circuit 320 may also include Figure 3 Additional peripheral circuitry not shown.

[0073] Voltage generator 324 can generate operating voltages of various levels. For example, in a read operation, voltage generator 324 can generate operating voltages of various levels, such as read voltage and pass voltage. Row decoder / word line driver 323 can be coupled to control logic circuit 325, voltage generator 324, and memory cell array 310. Row decoder 323 can select one of multiple word lines in response to a row address generated by control logic circuit 325 and provide the operating voltage generated from voltage generator 324 to the selected word line. Page buffer circuit 321 can be coupled to memory cells in memory cell array 310 via bit lines. Page buffer circuit 321 can precharge bit lines with a corresponding voltage in response to a page buffer control signal generated by control logic circuit 325, send data to and receive data from selected memory cells during programming and read operations, or temporarily store sent data. Column decoder / bit line driver 322 can send data to and receive data from page buffer circuit 321 or exchange data with data bus 328. Interface 327 can send commands and addresses received from external devices (e.g., memory controllers) to control logic circuitry 325. Interface 327 can also send data from external devices to column decoder 322 or output data from column decoder 322 to external devices via data bus 328. Control logic circuitry 325 can control peripheral circuitry in response to commands and addresses. Register 326 can be coupled to control logic circuitry 325 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0074] The peripheral circuit 320 may further include a level shifting circuit 400, which can be coupled between the control logic circuit 325 and the page buffer circuit 321, whose voltage domains are different. For example, the maximum signal level in the control logic circuit 325 can be lower than the maximum signal level in the page buffer circuit 321; that is, the power supply voltage provided by the memory to the control logic circuit 325 can be lower than the power supply voltage provided to the page buffer circuit 321. This results in lower power consumption for the control logic circuit 325, while allowing the page buffer circuit 321 to apply a sufficiently large bias voltage to the corresponding bit line to perform operations such as disabling programming of the bit line. Thus, the level shifting circuit 400 can convert the first level signal S1 output by the control logic circuit 325 into a second level signal S2 with a higher level value. The level of the second level signal S2 matches the voltage domain of the page buffer circuit 321, so the page buffer circuit 321 can apply a bias voltage to the corresponding bit line in response to the second level signal S2. In other embodiments, the level shifting circuit can also be coupled between any two circuits / modules in different voltage domains.

[0075] like Figure 4 The diagram illustrates an exemplary level-shifting circuit 400. The level-shifting circuit 400 may include an input circuit 410, a conversion circuit 420, and an output circuit 430. The input circuit 410 may be coupled to a second power supply terminal, and the conversion circuit 420 and the output circuit 430 may be coupled to a first power supply terminal. The power supply voltage VDDHV of the first power supply terminal is greater than the power supply voltage VDDLV of the second power supply terminal. It is understood that the power supply voltage of the control logic circuit and the input circuit 410 is VDDLV, meaning that the control logic circuit and the input circuit 410 are in the same voltage domain.

[0076] Specifically, the input circuit 410 may include a first inverter INV1 and a second inverter INV2 connected in series. The conversion circuit 420 may include a feedback circuit 421 and a pull-down circuit 422. The feedback circuit 421 includes a first transistor MP1 coupled between a first power supply terminal and a first node N1, and a second transistor MP2 coupled between the first power supply terminal and the second node N2. The control terminal of the first transistor MP1 is coupled to the second node N2, and the control terminal of the second transistor MP2 is coupled to the first node N1. The pull-down circuit 422 includes a third transistor MN1 coupled between the first node N1 and a ground terminal, and a fourth transistor MN2 coupled between the second node N2 and a ground terminal. The control terminal of the third transistor MN1 is coupled to the second output terminal N4 of the second inverter INV2, and the control terminal of the fourth transistor MN2 is coupled to the first output terminal N3 of the first inverter INV1. The output circuit 430 may include a third inverter INV3, the input terminal of which is coupled to the first node N1. In one example, the first transistor MP1 and the second transistor MP2 are PMOS transistors, and the third transistor MN1 and the fourth transistor MN2 are NMOS transistors. It should be noted that the type of each transistor in the level conversion circuit provided in this disclosure can be set according to actual needs and is not limited to the example given in the accompanying drawings. For example, the first and second transistors can be NMOS transistors, while the third and fourth transistors can be PMOS transistors.

[0077] When the signal received by the first inverter INV1 is low level VSS, the level of the first output terminal N3 of the first inverter INV1 is VDDLV, the fourth transistor MN2 is turned on, which pulls the level of the second node N2 low to VSS, the first transistor MP1 is turned on, and the level of the first node N1 is pulled high to VDDHV; the level of the second output terminal N4 of the second inverter INV2 is VSS, the third transistor MN1 is turned off, which disconnects the first node N1 from the ground terminal.

[0078] When the first inverter INV1 receives the first level signal S1 (level value VDDLV), the level of the first output terminal N3 of the first inverter INV1 is VSS, the fourth transistor MN2 is turned off, and the second node N2 is disconnected from the ground terminal; the level of the second output terminal N4 of the second inverter INV2 is VDDLV, the third transistor MN1 is turned on, the level of the first node N1 discharges from the previous VDDHV until it becomes VSS, the second transistor MP2 is turned on, and the level of the second node N2 is pulled high to VDDHV, thereby causing the first transistor MP1 to turn off, the first node N1 is disconnected from the first power supply terminal, and the level of the first node N1 remains at VSS. In this way, the third inverter INV3 of the output circuit 430 can output a second level signal S2 (level value VDDHV) with a higher level value, so that the page buffer can apply a bias voltage to the corresponding bit line in response to the second level signal S2 to perform operations such as disabling programming of the bit line.

[0079] It should be noted that since the input circuit 410 is coupled to the second power supply terminal and the conversion circuit 420 is coupled to the first power supply terminal, and the power supply voltage VDDHV of the first power supply terminal is greater than the power supply voltage VDDLV of the second power supply terminal, the transistors in the input circuit 410 and the conversion circuit 420 are manufactured using different processes, and their threshold voltages are also different. For example, the NMOS transistor in the conversion circuit 420 uses a slow corner process, and the threshold voltage of the NMOS transistor in the conversion circuit 420 will be higher than the threshold voltage of the NMOS transistor in the input circuit 410. In some embodiments, if the level conversion circuit 400 operates under more extreme conditions (such as a low-temperature environment), the threshold voltage of the NMOS transistor in the conversion circuit 420 will further increase; for example, the threshold voltage of the third transistor MN1 may increase to be greater than the power supply voltage VDDLV of the second power supply terminal. Thus, refer to... Figure 5The timing diagram of the level shifting circuit under extreme conditions is shown. At time t1, the first inverter INV1 receives the first level signal S1 (level value VDDLV). The level of the second output terminal N4 of the second inverter INV2 is flipped from VSS to VDDLV. However, the level VDDLV of node N4 cannot turn on the third transistor MN1. The first node N1 cannot discharge normally or discharges incompletely. The level of the first node N1 remains at VDDHV or slightly lower than VDDHV. The second transistor MP2 cannot be turned on. The level of the second node N2 remains at VSS. Therefore, the first transistor MP1 remains on, which further keeps the level of the first node N1 at VDDHV or slightly lower than VDDHV. In other words, even though the input circuit 410 receives the first level signal S1 (level value VDDLV), the level of the first node N1 cannot be flipped from VDDHV to VSS. As a result, the third inverter INV3 of the output circuit 430 cannot output the second level signal S2 with a level of VDDHV normally. The control logic circuit in the peripheral circuit cannot control the page buffer to operate on the corresponding bit line, resulting in a decrease in the performance and reliability of the memory.

[0080] In some embodiments, the third transistor MN1 (and the fourth transistor MN2) in the conversion circuit 420 can be replaced with a transistor with a smaller threshold voltage. This allows the third transistor MN1 to conduct even under extreme conditions, with the voltage level VDDLV at node N4. This means that node N1 can discharge normally from VDDHV to VSS, ensuring that the third inverter INV3 in the output circuit 430 can output the second-level signal S2 at VDDHV. However, using a transistor with a smaller threshold voltage (such as the third transistor MN1) in a circuit with a higher voltage range (such as the conversion circuit 420) increases the complexity and cost of the manufacturing process.

[0081] like Figure 6 As shown, this disclosure provides a level conversion circuit 500, including: an input circuit 510, a conversion circuit 520, and an output circuit 530 coupled in sequence; wherein, the input circuit 510 is configured to generate a first input signal INB in ​​response to a first level signal S1; an adjustment circuit 540 is coupled to the input circuit 510 and the conversion circuit 520 respectively; wherein, the adjustment circuit 540 is configured to adjust a first control signal Ctrl output by the conversion circuit 520 in response to the first input signal INB; wherein, the voltage domain of the conversion circuit 520 is different from the voltage domain of the input circuit 510; the output circuit 530 is configured to output a second level signal S2 in response to the adjusted first control signal Ctrl; wherein, the level value of the second level signal S2 is greater than the level value of the first level signal S1.

[0082] In this embodiment of the disclosure, the level conversion circuit 500 can be applied to any electronic device containing digital circuits, such as a memory, processor, controller, or programmable logic device. The level conversion circuit 500 includes an input circuit 510, a conversion circuit 520, and an output circuit 530 coupled in sequence, and an adjustment circuit 540 coupled between the input circuit 510 and the conversion circuit 520.

[0083] Input circuit 510 can receive a first level signal S1 and generate a first input signal INB in ​​response to the first level signal S1. The first level signal S1 can be a signal generated by a circuit in a lower voltage domain; that is, the circuit generating the first level signal S1 can have lower power consumption and be used to control other circuits in a higher voltage domain. For example, input circuit 510 may include one or more inverters to generate one or more input signals. The first input signal INB can be the inverse of the first level signal S1. Input circuit 510 and the circuit generating the first level signal S1 can be in the same voltage domain.

[0084] The conversion circuit 520 can respond to the input signal (including but not limited to the first input signal INB) generated by the input circuit 510 and output a first control signal Ctrl. Exemplarily, the conversion circuit 520 may include a cross-pair circuit, a pull-down circuit, etc. Referring to the above embodiment, since the voltage domain of the conversion circuit 520 is different from that of the input circuit 510, under extreme conditions, the input signal generated by the input circuit 510 may not be able to turn on / off the corresponding transistor in the conversion circuit 520. Therefore, the conversion circuit 520 cannot output the first control signal Ctrl with the correct level, ultimately causing the output circuit 530 to fail to output the second level signal S2 normally. Exemplarily, the output circuit 530 may include one or more inverters.

[0085] The regulating circuit 540 can respond to the first input signal INB generated by the input circuit 510 and adjust the level of the first control signal Ctrl output by the conversion circuit 520, thereby enabling the output circuit 530 to output a second level signal S2, the level of which is greater than the level of the first level signal S1. The regulating circuit 540 may include components such as transistors with low threshold voltages (whose threshold voltage is lower than the power supply voltage coupled to the input circuit under extreme conditions), and capacitors. For example, under extreme conditions, if the input signal generated by the input circuit 510 cannot turn the corresponding transistor in the conversion circuit 520 on / off, the regulating circuit 540 can adjust the level of the first control signal Ctrl output by the conversion circuit 520 by charging or discharging the output node of the conversion circuit 520. That is, the level of the output node of the conversion circuit 520 can be normally flipped, and thus, the output circuit 530 can respond to the adjusted first control signal Ctrl and output the second level signal S2. It is understood that the voltage domains of the output circuit 530 and the conversion circuit 520 can be the same.

[0086] In some embodiments, the first level signal S1 can be generated by control logic circuitry in the peripheral circuitry of the memory. The first level signal S1 generated by the control logic circuitry can be converted into a second level signal S2 with a higher level value via level conversion circuitry 500. The page buffer in the peripheral circuitry can then perform various operations on the bit lines in response to the second level signal S2. It should be noted that the level conversion circuitry 500 can also be coupled between any two circuits / modules in different voltage domains.

[0087] In this embodiment, the voltage domain of the conversion circuit 520 is different from that of the input circuit 510. The adjustment circuit 540 is configured to adjust the first control signal Ctrl output by the conversion circuit 520 in response to the first input signal INB; the output circuit 530 is configured to output a second level signal S2 in response to the adjusted first control signal Ctrl. Thus, when there is a large voltage difference between the power supply voltage coupled to the conversion circuit 520 and the power supply voltage coupled to the input circuit 510, the adjustment circuit 540 can adjust the level of the first control signal Ctrl, thereby ensuring that the level of the first control signal Ctrl output by the conversion circuit 520 can be normally flipped, guaranteeing that the output circuit 530 can normally output the second level signal S2 with a higher level value, thereby improving the reliability of the level conversion circuit.

[0088] In some embodiments, such as Figure 7As shown, the input circuit 510 is specifically configured to: generate a first input signal INB that is inversely phase with the first level signal S1 in response to the first level signal S1; wherein, the first output terminal N3 of the input circuit 510 is used to output the first input signal INB; the conversion circuit 520 includes: a feedback circuit 521, which is coupled to the first power supply terminal and the first node N1 of the conversion circuit 520; wherein, the feedback circuit 521 is configured to: provide the power supply level of the first power supply terminal to the first node N1; the adjustment circuit 540 includes: a first branch 541, which is coupled to the first node N1 and the first output terminal N3 of the input circuit 510; wherein, the first branch 541 is configured to: discharge the first node N1 in response to the first input signal INB, thereby adjusting the first control signal Ctrl output by the conversion circuit 520.

[0089] In this embodiment of the disclosure, the input circuit 510 may include at least one inverter, and the first output terminal N3 of the input circuit 510 is used to output a first input signal INB that is inverted with the first level signal S1.

[0090] The conversion circuit 520 may include a feedback circuit 521 coupled between a first power supply terminal and a first node N1. Here, the power supply voltage of the first power supply terminal is different from the power supply voltage of the second power supply terminal coupled to the input circuit 510; that is, the voltage domain of the conversion circuit 520 is different from the voltage domain of the input circuit 510. For example, the power supply level VDDHV of the first power supply terminal is greater than the power supply level VDDLV of the second power supply terminal. The feedback circuit 521 can be used to provide the power supply level VDDHV of the first power supply terminal to the first node N1, or to disconnect the first node N1 from the first power supply terminal. The feedback circuit 521 may include a cross-coupled pair circuit. For example, when the signal level received by the input circuit 510 is VSS, the feedback circuit 521 can connect the first node N1 to the first power supply terminal, pulling the level of the first node N1 high to VDDHV. When the input circuit 510 receives the first level signal S1 (level VDDLV), the level of the first input signal INB generated by the input circuit 510 is VSS. The first branch 541 of the adjustment circuit 540 can respond to the first input signal INB with level VSS by discharging the first node N1, thereby causing the level of the first node N1 to drop from VDDLV to a suitable level value (e.g., changing the level value of the corresponding transistor's conduction state in the output circuit). In other words, the first branch 541 can respond to the first input signal INB by adjusting the level of the first control signal Ctrl output by the conversion circuit 520, so that the level of the first control signal Ctrl can be flipped normally, ensuring that the output circuit 530 can output the second level signal S2 with a higher level value, thereby improving the reliability of the level conversion circuit. The first branch 541 may include components such as transistors with low threshold voltages (whose threshold voltage is lower than the power supply voltage coupled to the input circuit under extreme conditions) and capacitors.

[0091] In some embodiments, such as Figure 7 As shown, the input circuit 510 is further configured to: generate a second input signal IN that is inversely phase to the first input signal INB in ​​response to the first input signal INB; wherein, the second output terminal N4 of the input circuit 510 is used to output the second input signal IN; the adjustment circuit 540 further includes: a second branch 542, the second branch 542 being coupled to the second node N2 of the conversion circuit 520 and the second output terminal N4 of the input circuit; wherein, the second branch 542 is configured to: adjust the level of the second node N2 in response to the second input signal IN, so that the feedback circuit 521 stops providing the power level to the first node N1; the feedback circuit 521 is coupled to the first power terminal and the second node N2 respectively.

[0092] In this embodiment of the disclosure, the input circuit 510 may include at least one inverter. The first output terminal N3 of the input circuit 510 is used to output a first input signal INB that is inverted with the first level signal S1, and the second output terminal N4 of the input circuit 510 is used to output a second input signal IN that is inverted with the first input signal INB.

[0093] Feedback circuit 521 can also be coupled to the first power supply terminal and the second node N2. Feedback circuit 521 can be used to provide the power supply level VDDHV of the first power supply terminal to the second node N2, or to disconnect the second node N2 from the first power supply terminal. Feedback circuit 521 may include a cross-coupled pair circuit. For example, when the level of the signal received by input circuit 510 is VSS, feedback circuit 521 can disconnect the second node N2 from the first power supply terminal, and the level of the second node N2 is pulled down to VSS. When input circuit 510 receives the first level signal S1 (level VDDLV), the level of the second input signal IN generated by input circuit 510 is VDDLV. The second branch 542 of adjustment circuit 540 can adjust the level of the second node N2 (e.g., increase the level of the second node N2) in response to the second input signal IN with level VDDLV. Then, feedback circuit 521 responds to the adjusted level of the second node N2 and disconnects the first node N1 from the first power supply terminal, promoting the discharge of the first node N1. In other words, the second branch 542 can respond to the second input signal IN, indirectly promoting the discharge of the first node N1, so that the level of the first control signal Ctrl can be normally flipped, ensuring that the output circuit 530 can normally output the second level signal S2 with a higher level value, thereby improving the reliability of the level conversion circuit. The second branch 542 may include components such as transistors with low threshold voltages (under extreme conditions, their threshold voltage is lower than the power supply voltage coupled to the input circuit), and capacitors.

[0094] In some embodiments, the second branch 542 is specifically configured to charge the second node N2 in response to the second input signal IN until the first node N1 and the first power supply are disconnected.

[0095] In this embodiment of the present disclosure, the second branch 542 of the adjustment circuit 540 can charge the second node N2 in response to the second input signal IN, causing the level of the second node N2 to rise from VSS to a level greater than the threshold voltage of the transistor in the feedback circuit 521. Then, in response to the increased level of the second node N2, the feedback circuit 521 disconnects the first node N1 from the first power supply terminal, further promoting the discharge of the first node N1, so that the level of the first control signal Ctrl can be flipped normally, ensuring that the output circuit 530 can output the second level signal S2 with a higher level value normally, thereby improving the reliability of the level conversion circuit.

[0096] In some embodiments, such as Figure 8 As shown, the feedback circuit 521 includes: a first transistor MP1, the first terminal of the first transistor MP1 is coupled to the first power supply terminal, the second terminal of the first transistor MP1 is coupled to the first node N1, and the control terminal of the first transistor MP1 is coupled to the second node N2; and a second transistor MP2, the first terminal of the second transistor MP2 is coupled to the first power supply terminal, the second terminal of the second transistor MP2 is coupled to the second node N2, and the control terminal of the second transistor MP2 is coupled to the first node N1.

[0097] In this embodiment, the feedback circuit 521 can be a cross-coupled pair circuit, and the feedback circuit 521 includes a positive feedback structure composed of a first transistor MP1 and a second transistor MP2. Specifically, the first terminal and the second terminal of the first transistor MP1 are respectively coupled to a first power supply terminal and a first node N1, and the control terminal of the first transistor MP1 is coupled to a second node N2; the first terminal and the second terminal of the second transistor MP2 are respectively coupled to the first power supply terminal and the second node N2, and the control terminal of the second transistor MP2 is coupled to the first node N1. Here, taking the example that both the first transistor MP1 and the second transistor MP2 are PMOS transistors, the positive feedback process of the feedback circuit 521 will be described. When the voltage level of the second node N2 is VSS, the first transistor MP1 is turned on, and the first node N1 is connected to the first power supply terminal. The voltage level of the first node N1 is pulled high to VDDHV, which in turn causes the second transistor MP2 to turn off, and the second node N2 remains at VSS. When the voltage level of the first node N1 is VSS, the second transistor MP2 is turned on, and the second node N2 is connected to the first power supply terminal. The voltage level of the second node N2 is pulled high to VDDHV, which in turn causes the first transistor MP1 to turn off, and the first node N1 remains at VSS. It can be understood that the first transistor and the second transistor can also be NMOS transistors. In this case, the first transistor can be coupled between the ground terminal and the first node, and the control terminal of the first transistor can be coupled to the second node; the second transistor can be coupled between the ground terminal and the second node, and the control terminal of the second transistor can be coupled to the first node.

[0098] In some embodiments, such as Figure 8As shown, the conversion circuit 520 further includes a pull-down circuit 522; the pull-down circuit 522 includes: a third transistor MN1, the first terminal of the third transistor MN1 being coupled to the first node N1, the second terminal of the third transistor MN1 being coupled to the ground terminal, and the control terminal of the third transistor MN1 being coupled to the second output terminal N4 of the input circuit 510; and a fourth transistor MN2, the first terminal of the fourth transistor MN2 being coupled to the second node N2, the second terminal of the fourth transistor MN2 being coupled to the ground terminal, and the control terminal of the fourth transistor MN2 being coupled to the first output terminal N3 of the input circuit 510.

[0099] In this embodiment of the disclosure, the conversion circuit 520 may further include a pull-down circuit 522, which includes a third transistor MN1 and a fourth transistor MN2. Specifically, the first and second terminals of the third transistor MN1 are respectively coupled to the first node N1 and the ground terminal, and the control terminal of the third transistor MN1 is coupled to the second output terminal N4 of the input circuit 510; the first and second terminals of the fourth transistor MN2 are respectively coupled to the second node N2 and the ground terminal, and the control terminal of the fourth transistor MN2 is coupled to the first output terminal N3 of the input circuit 510.

[0100] Thus, when the signal received by the input circuit 510 is low-level VSS, the level of the first output terminal N3 is VDDLV, the fourth transistor MN2 is turned on, causing the level of the second node N2 to be pulled low to VSS, the first transistor MP1 is turned on, and the level of the first node N1 is pulled high to VDDHV; the level of the second output terminal N4 is VSS, the third transistor MN1 is turned off, causing the first node N1 to be disconnected from the ground terminal. When the input circuit 510 receives the first level signal S1 (level value VDDLV), the first output terminal N3 outputs the first input signal INB with a level of VSS, the fourth transistor MN2 is turned off, and the second node N2 is disconnected from the ground terminal; the second output terminal N4 outputs the second input signal IN with a level of VDDLV, the third transistor MN1 is turned on, the level of the first node N1 discharges from the previous VDDHV until it becomes VSS, the second transistor MP2 is turned on, and the level of the second node N2 is pulled high to VDDHV, thereby causing the first transistor MP1 to be turned off, the first node N1 to be disconnected from the first power supply terminal, and the level of the first node N1 remains at VSS. Thus, the output circuit 530 can output a second-level signal S2 (level value VDDHV) with a higher level value, thereby improving the reliability of the level conversion circuit.

[0101] In some embodiments, the threshold voltage of the third transistor MN1 is greater than the level of the second input signal IN.

[0102] In this embodiment, if the level conversion circuit operates under extreme conditions (such as low temperature), the threshold voltage of the transistor in the conversion circuit 520 will further increase. For example, the threshold voltage of the third transistor MN1 will increase to a level greater than the level of the second input signal IN (i.e., greater than the power supply voltage VDDLV of the second power supply terminal). Thus, the second input signal IN, with a level of VDDLV, cannot turn on the third transistor MN1, and the first node N1 remains disconnected from the ground terminal. At this time, the first branch 541 can discharge the first node N1 in response to the first input signal INB, with a level of VSS, thereby causing the level of the first node N1 to drop from VDDHV to a suitable level (e.g., capable of changing the level of the corresponding transistor's conduction state in the output circuit), meaning the level of the first control signal Ctrl output by the conversion circuit 520 can be normally toggled. The second branch 542 can respond to the second input signal IN with a level of VDDLV to charge the second node N2, raising the level of the second node N2 from VSS to a level greater than the threshold voltage of the first transistor MP1. The first transistor MP1 is turned off, and the first node N1 is disconnected from the first power supply terminal, further promoting the discharge of the first node N1. This allows the level of the first control signal Ctrl to flip normally, ensuring that the output circuit 530 can output the second level signal S2 with a higher level value, thereby improving the reliability of the level conversion circuit.

[0103] In some embodiments, such as Figure 8 As shown, the first branch 541 includes a first capacitor C1; the second branch 542 includes a second capacitor C2.

[0104] In this embodiment, the first branch 541 may include a first capacitor C1 to discharge the first node N1 using a coupling effect; the second branch 542 may include a second capacitor C2 to charge the second node N2 using a coupling effect. Specifically, if the signal level initially received by the input circuit 510 is VSS, then the level of the first node N1 is VDDHV, and the level of the second node N2 is VSS. Then, under extreme conditions (such as low temperature), the input circuit 510 receives a first level signal S1 (level VDDLV), while the second input signal IN (level VDDLV) cannot turn on the third transistor MN1, and the first node N1 remains disconnected from the ground. At this time, refer to... Figure 9In the timing diagram shown, at time t1, the level of the first input signal INB flips from VDDLV to VSS, that is, the level of the first output terminal N3 changes from VDDLV to VSS. The first node N1 is coupled to the first output terminal N3 through the first capacitor C1. The level of the first node N1 discharges from VDDHV to VDDHV–CC1 / (CC1+Cload1)*VDDLV, thereby enabling the level of the first control signal Ctrl to flip normally. Here, Cload1 is the capacitance value at the first output terminal N3 in the input circuit 510, and CC1 is the capacitance value of the first capacitor C1. The capacitance value; the level of the second input signal IN is flipped from VSS to VDDLV, that is, the level of the second output terminal N4 changes from VSS to VDDLV. The second node N2 is coupled to the second output terminal N4 through the second capacitor C2. The level of the second node N2 is charged from VSS to CC2 / (CC2+Cload2)*VDDLV. The first transistor MP1 is turned off, and the first node N1 is disconnected from the first power supply terminal, which indirectly promotes the discharge of the first node N1. Here, Cload2 is the capacitance value at the second output terminal N4 in the input circuit 510, and CC2 is the capacitance value of the second capacitor C2.

[0105] In some embodiments, the level conversion circuit 500 is located in the peripheral circuit of the memory. In this case, the first capacitor C1 and the second capacitor C2 can be formed by means of metal-oxide-semiconductor field-effect transistor (MOSFET) technology, metal technology, etc., thereby improving compatibility with semiconductor technology and saving manufacturing costs.

[0106] In some embodiments, such as Figure 8 As shown, the third transistor MN1 and the fourth transistor MN2 are NMOS transistors; the input circuit 510 includes at least one NMOS transistor; wherein the threshold voltage of the third transistor MN1 and the threshold voltage of the fourth transistor MN2 are the same as the threshold voltage of the NMOS transistor in the input circuit 510.

[0107] In this embodiment, the input circuit 510 may include at least one NMOS transistor, such as the NMOS transistor in the first inverter INV1 and the second inverter INV2. It is understood that since the input circuit 510 is coupled to a second power supply terminal with a power supply voltage of VDDLV, and the conversion circuit 520 is coupled to a first power supply terminal with a power supply voltage of VDDHV, and VDDHV is greater than VDDLV, if the third transistor MN1 and the fourth transistor MN2 are formed using the manufacturing process of transistors in a high-voltage circuit, the threshold voltages of the third transistor MN1 and the fourth transistor MN2 will be relatively large. Under extreme conditions, the threshold voltages of the third transistor MN1 and the fourth transistor MN2 will further increase, thereby causing the input signals generated by the input circuit 510 (including but not limited to the first input signal INB and the second input signal IN) to fail to turn on the third transistor MN1 and / or the fourth transistor MN2, and the first control signal Ctrl output by the conversion circuit 520 cannot be flipped normally. Therefore, the threshold voltages of the third transistor MN1 and the fourth transistor MN2 can be the same as the threshold voltage of the NMOS transistor in the input circuit 510. That is, both the third transistor MN1 and the fourth transistor MN2 are transistors with low threshold voltages, thereby preventing the input signal generated by the input circuit 510 from failing to control the third transistor MN1 and / or the fourth transistor MN2. For example, the third transistor MN1 and the fourth transistor MN2 can be formed using the manufacturing process of transistors in low-voltage circuits, such as using the same process as the NMOS transistor in the input circuit 510. It should be noted that, based on ensuring that the first control signal Ctrl can be properly toggled using the first branch 541 and the second branch 542, the third transistor MN1 and the fourth transistor MN2 can be set to have the same threshold voltage as the NMOS transistor in the input circuit 510, thereby further increasing the reliability of the level conversion circuit.

[0108] In some embodiments, the input circuit includes at least one inverter.

[0109] In the embodiments disclosed herein, such as Figure 8 As shown, the input circuit 510 may include two inverters. The first output terminal N3 and the second output terminal N4 of the input circuit 510 can be the output terminals of the first inverter INV1 and the second inverter INV2, respectively. Figure 10As shown, the input circuit 510 may include an inverter. The first output terminal N3 and the second output terminal N4 of the input circuit 510 can be the output terminal and input terminal of the first inverter INV1, respectively. It is understood that the input circuit 510 may also include two or more inverters, as long as the level of the first input signal INB output from the first output terminal N3 is inverted with the level of the first level signal S1, and the level of the second input signal IN output from the second output terminal N4 is the same as the level of the first level signal S1. No further limitations are imposed here. Fewer inverters in the input circuit 510 are more beneficial for reducing the signal delay of the level conversion circuit; more inverters in the input circuit 510 are more beneficial for shaping the signal pulse and improving signal quality.

[0110] This disclosure provides a memory including a page buffer circuit, a control logic circuit, and a level shifting circuit, wherein the level shifting circuit is coupled between the control logic circuit and the page buffer circuit; the level shifting circuit includes: a first inverter and a second inverter connected in series; the first inverter is configured to generate a first input signal in response to a first level signal output by the control logic circuit; a first transistor, wherein a first terminal of the first transistor is coupled to a first power supply terminal, a second terminal of the first transistor is coupled to a first node, and a control terminal of the first transistor is coupled to a second node; the voltage of the second power supply terminal coupled to the first inverter is different from the voltage of the first power supply terminal; a second transistor, wherein the second transistor... A first terminal is coupled to the first power supply terminal; a second terminal of the second transistor is coupled to the second node; a control terminal of the second transistor is coupled to the first node; a first capacitor is coupled to the first node and the output terminal of the first inverter; the first capacitor is configured to: adjust a first control signal output through the first node in response to the first input signal; a second capacitor is coupled to the second node and the output terminal of the second inverter; a third inverter is coupled to the first node; the third inverter is configured to: output a second level signal in response to the adjusted first control signal; wherein the level value of the second level signal is greater than the level value of the first level signal.

[0111] In this embodiment of the disclosure, reference is made to Figure 3The memory 300 includes a memory cell array 310 and peripheral circuitry 320. The peripheral circuitry 320 includes a control logic circuit 325, a page buffer circuit 321, and a level shifting circuit 500 coupled between the control logic circuit 325 and the page buffer circuit 321. The page buffer circuit 321 can precharge bit lines in response to control signals generated by the control logic circuit 325, send data to and receive data from selected memory cells during programming and reading operations, or temporarily store sent data. The control logic circuit 325 and the page buffer circuit 321 have different voltage domains. For example, the power supply voltage provided to the control logic circuit 325 can be lower than the power supply voltage provided to the page buffer circuit 321, thereby enabling the control logic circuit 325 to have lower power consumption, while allowing the page buffer circuit 321 to apply a sufficiently large bias voltage to the corresponding bit lines to achieve operations such as disabling programming of the bit lines. The level conversion circuit 500 can convert the first level signal S1 output by the control logic circuit 325 into a second level signal S2 with a higher level value. The level of the second level signal S2 matches the voltage domain of the page buffer circuit 321. Therefore, the page buffer circuit 321 can apply a bias voltage to the corresponding bit line in response to the second level signal S2.

[0112] Specifically, refer to Figure 8 The level conversion circuit 500 includes an input circuit 510, a conversion circuit 520 and an output circuit 530 coupled in sequence, and an adjustment circuit 540 coupled between the input circuit 510 and the conversion circuit 520.

[0113] Input circuit 510 can receive a first level signal S1 and generate a first input signal INB in ​​response to the first level signal S1. The first level signal S1 can be generated by control logic circuitry. For example, input circuit 510 may include one or more inverters to generate one or more input signals. The first input signal INB can be the inverse of the first level signal S1. Input circuit 510 and control logic circuitry can be in the same voltage domain.

[0114] The conversion circuit 520 can respond to the input signal (including but not limited to the first input signal INB) generated by the input circuit 510 and output a first control signal Ctrl. Exemplarily, the conversion circuit 520 may include a cross-pair circuit, a pull-down circuit, etc. Referring to the above embodiment, since the voltage domain of the conversion circuit 520 is different from that of the input circuit 510, under extreme conditions, the input signal generated by the input circuit 510 may not be able to turn on / off the corresponding transistor in the conversion circuit 520. Therefore, the conversion circuit 520 cannot output the first control signal Ctrl with the correct level, ultimately causing the output circuit 530 to fail to output the second level signal S2 normally. Exemplarily, the output circuit 530 may include one or more inverters.

[0115] The regulating circuit 540 can respond to the first input signal INB generated by the input circuit 510 and adjust the level of the first control signal Ctrl output by the conversion circuit 520, thereby enabling the output circuit 530 to output a second level signal S2, the level of which is greater than the level of the first level signal S1. The regulating circuit 540 may include components such as transistors with low threshold voltages (whose threshold voltage is lower than the power supply voltage coupled to the input circuit under extreme conditions), and capacitors. For example, under extreme conditions, if the input signal generated by the input circuit 510 cannot turn the corresponding transistor in the conversion circuit 520 on / off, the regulating circuit 540 can adjust the level of the first control signal Ctrl output by the conversion circuit 520 by charging or discharging the output node of the conversion circuit 520. That is, the level of the output node of the conversion circuit 520 can be normally flipped, and thus, the output circuit 530 can respond to the adjusted first control signal Ctrl and output the second level signal S2. It is understood that the voltage domains of the output circuit 530 and the conversion circuit 520 can be the same.

[0116] Thus, when there is a large voltage difference between the power supply voltage coupled to the conversion circuit 520 and the power supply voltage coupled to the input circuit 510, the adjustment circuit 540 can adjust the level of the first control signal Ctrl, so that the level of the first control signal Ctrl output by the conversion circuit 520 can be flipped normally, ensuring that the output circuit 530 can output the second level signal S2 with a higher level value, thereby improving the reliability of the level conversion circuit.

[0117] More specifically, the input circuit 510 may include a first inverter INV1 and a second inverter INV2 connected in series. The first inverter INV1 can generate a first input signal INB in ​​response to a first level signal S1 output by the control logic circuit. The conversion circuit 520 may include a feedback circuit 521 and a pull-down circuit 522. The feedback circuit 521 includes a first transistor MP1 and a second transistor MP2. The first and second terminals of the first transistor MP1 are respectively coupled to a first power supply terminal and a first node N1, and the control terminal of the first transistor MP1 is coupled to a second node N2. The first and second terminals of the second transistor MP2 are respectively coupled to the first power supply terminal and the second node N2, and the control terminal of the second transistor MP2 is coupled to the first node N1. The voltage VDDLV of the second power supply terminal coupled to the first inverter INV1 is different from the voltage VDDHV of the first power supply terminal; for example, the voltage VDDHV of the first power supply terminal is greater than the voltage VDDLV of the second power supply terminal. The adjustment circuit 540 includes a first branch 541 and a second branch 542. The first branch 541 includes a first capacitor C1 coupled to the first node N1 and the first output terminal N3 of the first inverter INV1. The second branch 542 includes a second capacitor C2 coupled to the second node N2 and the second output terminal N4 of the second inverter INV2. The output circuit 530 includes a third inverter INV3. The input terminal of the third inverter INV3 is coupled to the first node N1. The third inverter INV3 can respond to the first control signal Ctrl and output a second level signal S2.

[0118] The first capacitor C1 can discharge the first node N1 using the coupling effect; the second capacitor C2 can charge the second node N2 using the coupling effect. Specifically, if the signal level initially received by the input circuit 510 is VSS, then the level of the first node N1 is VDDHV, and the level of the second node N2 is VSS. Then, under extreme conditions (such as low temperature), the input circuit 510 receives the first level signal S1 (level VDDLV), while the second input signal IN (level VDDLV) cannot turn on the third transistor MN1, and the first node N1 remains disconnected from the ground. At this time, reference... Figure 9In the timing diagram shown, at time t1, the level of the first input signal INB flips from VDDLV to VSS, that is, the level of the first output terminal N3 changes from VDDLV to VSS. The first node N1 is coupled to the first output terminal N3 through the first capacitor C1. The level of the first node N1 discharges from VDDHV to VDDHV–CC1 / (CC1+Cload1)*VDDLV, thereby enabling the level of the first control signal Ctrl to flip normally. Here, Cload1 is the capacitance value at the first output terminal N3 in the input circuit 510, and CC1 is the capacitance value of the first capacitor C1. The capacitance value; the level of the second input signal IN is flipped from VSS to VDDLV, that is, the level of the second output terminal N4 changes from VSS to VDDLV. The second node N2 is coupled to the second output terminal N4 through the second capacitor C2. The level of the second node N2 is charged from VSS to CC2 / (CC2+Cload2)*VDDLV. The first transistor MP1 is turned off, and the first node N1 is disconnected from the first power supply terminal, which indirectly promotes the discharge of the first node N1. Here, Cload2 is the capacitance value at the second output terminal N4 in the input circuit 510, and CC2 is the capacitance value of the second capacitor C2.

[0119] It is understandable that the first capacitor C1 and the second capacitor C2 enable the conversion circuit 520 to ensure that the level of the first control signal Ctrl can still be flipped normally when it receives a second input signal IN with a lower level (level VDDLV). In other words, the power supply voltage of the second power supply terminal coupled to the control logic circuit and the input circuit can be further reduced, i.e., VDDLV can be smaller, thereby reducing the energy consumption of the control logic circuit and the input circuit.

[0120] In some embodiments, the second inverter is configured to generate a second input signal in response to the first input signal; and the second capacitor is configured to adjust the level of the second node in response to the second input signal, thereby turning off the first transistor.

[0121] In some embodiments, the first capacitor is specifically configured to: discharge the first node in response to the first input signal, thereby adjusting the first control signal output by the first node; the second capacitor is configured to: charge the second node in response to the second input signal until the first transistor is turned off.

[0122] In some embodiments, the level shifting circuit further includes: a third transistor, a first terminal of which is coupled to the first node, a second terminal of which is coupled to a ground terminal, and a control terminal of which is coupled to the output terminal of the second inverter; and a fourth transistor, a first terminal of which is coupled to the second node, a second terminal of which is coupled to the ground terminal, and a control terminal of which is coupled to the output terminal of the first inverter.

[0123] In some embodiments, the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.

[0124] In some embodiments, the threshold voltage of the third transistor is greater than the level value of the second input signal.

[0125] In some embodiments, the third transistor and the fourth transistor are NMOS transistors; the threshold voltage of the third transistor, the threshold voltage of the fourth transistor, the threshold voltage of the NMOS transistor in the first inverter, and the threshold voltage of the NMOS transistor in the second inverter are all the same.

[0126] In some embodiments, such as Figure 11 As shown, the page buffer circuit 321 includes a bias circuit 329; the level conversion circuit 500 is coupled between the bias circuit 329 and the control logic circuit 325; the bias circuit 329 is configured to apply a bias voltage to the bit line in response to the second level signal S2.

[0127] In this embodiment, the voltage domains of the control logic circuit 325 and the page buffer circuit 321 are different. The maximum level of the signal in the control logic circuit 325 can be lower than the maximum level of the signal in the page buffer 321, meaning the power supply voltage provided by the memory to the control logic circuit 325 can be lower than the power supply voltage provided to the page buffer 321. Thus, the level conversion circuit 500 can convert the first level signal S1 output by the control logic circuit 325 into a second level signal S2 with a higher level value. The level of the second level signal S2 matches the voltage domain of the page buffer 321. Therefore, the bias circuit 329 in the page buffer 321 can apply a bias voltage to the corresponding bit line in response to the second level signal S2 to perform operations such as disabling programming on the bit line.

[0128] This disclosure provides a memory system, including: the memory described in any of the above embodiments; and a memory controller coupled to the memory.

[0129] In this embodiment of the disclosure, the memory system can be referred to accordingly. Figure 1The memory system 102 in the illustrated embodiment can be referenced accordingly. Figure 1 The memory 104 in the illustrated embodiment and Figure 3 The memory 300 in the illustrated embodiment can be referenced accordingly, and the memory controller can be referenced accordingly. Figure 1 The memory controller 106 in the illustrated embodiment is configured to control the memory. The specific functions, applications, and interactions between the memory and the memory controller will not be described in detail here.

[0130] This disclosure provides an electronic device, including: the memory system described in the above embodiments.

[0131] In this embodiment of the disclosure, the electronic device can be referred to accordingly. Figure 1 The electronic device 100 in the illustrated embodiments is for illustrative purposes only and will not be described in detail here. The electronic device may be implemented using the memory system described in the above embodiments, as well as one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components.

[0132] In the level conversion circuit, memory, memory system, and electronic device provided in this disclosure, the adjustment circuit can adjust the level of the first control signal, thereby enabling the level of the first control signal output by the conversion circuit to flip normally, ensuring that the output circuit can normally output a second level signal with a higher level value, thus improving the reliability of the level conversion circuit. More specifically, the adjustment circuit may include a first branch and a second branch. The first branch includes a first capacitor, and the second branch includes a second capacitor. The first capacitor can discharge the first node using the coupling effect, and the second capacitor can charge the second node using the coupling effect, thereby enabling the level of the first control signal to flip normally, ensuring that the output circuit can normally output a second level signal with a higher level value.

[0133] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0134] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A level conversion circuit, characterized in that, include: An input circuit, a conversion circuit, and an output circuit are coupled in sequence; wherein the input circuit is configured to generate a first input signal in response to a first level signal; An adjustment circuit is coupled to the input circuit and the conversion circuit respectively; wherein the adjustment circuit is configured to: adjust the first control signal output by the conversion circuit in response to the first input signal; wherein the voltage domain of the conversion circuit is different from the voltage domain of the input circuit. The output circuit is configured to output a second level signal in response to the adjusted first control signal; wherein the level value of the second level signal is greater than the level value of the first level signal.

2. The level conversion circuit according to claim 1, characterized in that, The input circuit is specifically configured to: generate a first input signal that is inversely phase to the first level signal in response to the first level signal; wherein, the first output terminal of the input circuit is used to output the first input signal; The conversion circuit includes a feedback circuit, which is coupled to a first power supply terminal and a first node of the conversion circuit; wherein the feedback circuit is configured to provide the power level of the first power supply terminal to the first node. The regulating circuit includes: a first branch coupled to the first node and a first output terminal of the input circuit; wherein the first branch is configured to: discharge the first node in response to the first input signal, thereby regulating the first control signal output by the conversion circuit.

3. The level conversion circuit according to claim 2, characterized in that, The input circuit is further configured to: generate a second input signal that is inversely phase to the first input signal in response to the first input signal; wherein the second output terminal of the input circuit is used to output the second input signal; The adjustment circuit further includes a second branch, which is coupled to a second node of the conversion circuit and a second output terminal of the input circuit; wherein the second branch is configured to: adjust the level of the second node in response to the second input signal, so that the feedback circuit stops providing the power level to the first node; the feedback circuit is coupled to the first power terminal and the second node respectively.

4. The level conversion circuit according to claim 3, characterized in that, The second branch is specifically configured to charge the second node in response to the second input signal until the first node and the first power supply are disconnected.

5. The level conversion circuit according to claim 3, characterized in that, The feedback circuit includes: A first transistor, wherein a first terminal of the first transistor is coupled to the first power supply terminal, a second terminal of the first transistor is coupled to the first node, and a control terminal of the first transistor is coupled to the second node; The second transistor has a first terminal coupled to the first power supply terminal, a second terminal coupled to the second node, and a control terminal coupled to the first node.

6. The level conversion circuit according to claim 3, characterized in that, The first branch includes a first capacitor; the second branch includes a second capacitor.

7. The level conversion circuit according to claim 3, characterized in that, The conversion circuit further includes a pull-down circuit; the pull-down circuit includes: The third transistor has a first terminal coupled to the first node, a second terminal coupled to ground, and a control terminal coupled to the second output terminal of the input circuit. A fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second node, a second terminal of the fourth transistor is coupled to the ground terminal, and a control terminal of the fourth transistor is coupled to the first output terminal of the input circuit.

8. The level conversion circuit according to claim 7, characterized in that, The threshold voltage of the third transistor is greater than the level of the second input signal.

9. The level conversion circuit according to claim 7, characterized in that, The third transistor and the fourth transistor are NMOS transistors; the input circuit includes at least one NMOS transistor; wherein the threshold voltage of the third transistor and the threshold voltage of the fourth transistor are the same as the threshold voltage of the NMOS transistor in the input circuit.

10. The level conversion circuit according to claim 1, characterized in that, The input circuit includes at least one inverter.

11. A memory, characterized in that, The memory includes a page buffer circuit, a control logic circuit, and a level conversion circuit, wherein the level conversion circuit is coupled between the control logic circuit and the page buffer circuit. The level conversion circuit includes: A first inverter and a second inverter connected in series; the first inverter is configured to generate a first input signal in response to a first level signal output by the control logic circuit. A first transistor, wherein a first terminal of the first transistor is coupled to a first power supply terminal, a second terminal of the first transistor is coupled to a first node, and a control terminal of the first transistor is coupled to a second node; the voltage of the second power supply terminal to which the first inverter is coupled is different from the voltage of the first power supply terminal. The second transistor has a first terminal coupled to the first power supply terminal, a second terminal coupled to the second node, and a control terminal coupled to the first node. A first capacitor is coupled to the first node and the output of the first inverter; the first capacitor is configured to: adjust a first control signal output through the first node in response to the first input signal. The second capacitor is coupled to the second node and the output of the second inverter; A third inverter, coupled to the first node, is configured to output a second level signal in response to the adjusted first control signal, wherein the level value of the second level signal is greater than the level value of the first level signal.

12. The memory according to claim 11, characterized in that, The second inverter is configured to generate a second input signal in response to the first input signal; The second capacitor is configured to: adjust the level of the second node in response to the second input signal, thereby turning off the first transistor.

13. The memory according to claim 12, characterized in that, The first capacitor is specifically configured to: discharge the first node in response to the first input signal, thereby adjusting the first control signal output by the first node; The second capacitor is configured to charge the second node in response to the second input signal until the first transistor is turned off.

14. The memory according to claim 12, characterized in that, The level conversion circuit also includes: The third transistor has a first terminal coupled to the first node, a second terminal coupled to ground, and a control terminal coupled to the output terminal of the second inverter. A fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second node, a second terminal of the fourth transistor is coupled to the ground terminal, and a control terminal of the fourth transistor is coupled to the output terminal of the first inverter.

15. The memory according to claim 14, characterized in that, The first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.

16. The memory according to claim 14, characterized in that, The threshold voltage of the third transistor is greater than the level of the second input signal.

17. The memory according to claim 14, characterized in that, The third transistor and the fourth transistor are NMOS transistors; the threshold voltage of the third transistor, the threshold voltage of the fourth transistor, the threshold voltage of the NMOS transistor in the first inverter, and the threshold voltage of the NMOS transistor in the second inverter are all the same.

18. The memory according to claim 11, characterized in that, The page buffer circuit includes a bias circuit; the level conversion circuit is coupled between the bias circuit and the control logic circuit. The bias circuit is configured to apply a bias voltage to the bit line in response to the second level signal.

19. A memory system, characterized in that, include: The memory as described in any one of claims 11 to 18; A memory controller, coupled to the memory.

20. An electronic device, characterized in that, include: The memory system as described in claim 19.

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