Silicon through hole interconnection structure and forming method thereof

Abstract

The invention provides a through silicon via interconnection structure and a forming method thereof, the through silicon via interconnection structure comprises a device wafer, a first surface of the device wafer is provided with an intermetallic dielectric layer, a first interconnection metal layer and a first etching stop layer, the first etching stop layer surrounds the side wall and the bottom of the first interconnection metal layer and is formed in the intermetallic dielectric layer; the bearing wafer is bonded with the first surface of the device wafer; the back protection layer is positioned on the second surface of the device wafer; the silicon through hole penetrates through the back protection layer, the device wafer and the first etching stop layer, and a part of the first interconnection metal layer is exposed out of the silicon through hole; the first insulating layer and the first barrier layer are sequentially stacked on the side wall of the silicon through hole; the second barrier layer is positioned on the surface of the first barrier layer and at the bottom of the silicon through hole; and the through hole interconnection metal layer is filled in the silicon through hole. The through silicon via interconnection structure and the forming method thereof can improve the reliability of a device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a through-silicon via (TSV) interconnect structure and a method for forming the same. Background Technology

[0002] With the development of 3D integrated circuits, chip integration density is gradually increasing, and the need for through-silicon via (TSV) interconnect technology is also growing. For back-side TSV interconnect technology, TSVlast is a commonly used process choice. TSVlast technology first thins the back side of the wafer, then etches the semiconductor substrate to form vias. Next, the dielectric layer under the semiconductor substrate is etched to expose the metal layer to be interconnected with the metal material in the TSV. The metal layer material is, for example, copper. When the dielectric layer is etched to expose the metal layer, the copper is sputtered, which then sputters into the insulating material layer, such as silicon oxide, on the sidewall of the via. Subsequently, the copper diffuses through the silicon oxide into the semiconductor substrate, causing reliability issues for semiconductor devices, such as active devices or interconnect structures formed in the semiconductor substrate.

[0003] Therefore, it is necessary to provide a more effective and reliable technical solution to prevent device reliability problems caused by sputtering of the metal material (e.g., copper) in the metal layer during the formation of TSV vias in existing technologies. Summary of the Invention

[0004] This application provides a through-silicon via (TSV) interconnect structure and a method for forming the same, avoiding device reliability issues caused by sputtering of metal material in the metal layer during the formation of TSV vias in existing technologies.

[0005] One aspect of this application provides a method for forming a through-silicon via (TSV) interconnect structure, comprising:

[0006] A device wafer is provided, the device wafer including a first side and a second side opposite to each other. An intermetallic dielectric layer, a first interconnect metal layer, and a first etch stop layer are formed on the first side of the device wafer, wherein the first etch stop layer surrounds the sidewalls and bottom of the first interconnect metal layer and is formed in the intermetallic dielectric layer. The second side of the device wafer is thinned after the first side of the device wafer is bonded to a carrier wafer. A back protection layer is formed on the second side of the device wafer, and the back protection layer and the device wafer are etched sequentially to form a through-silicon via (TSV), the TSV exposing the first etch stop layer. A first insulating layer and a first barrier layer are formed sequentially stacked on the sidewalls of the TSV, and the first etch stop layer at the bottom of the TSV is removed. A second barrier layer is formed on the surface of the first barrier layer and on the surface of the first interconnect metal layer at the bottom of the TSV, and the TSV is filled with the through-hole interconnect metal layer.

[0007] In some embodiments of this application, an intermetallic dielectric layer, a first interconnect metal layer, and a first etch stop layer are formed on a first surface of the device wafer. The first etch stop layer surrounds the sidewalls and bottom of the first interconnect metal layer and is formed within the intermetallic dielectric layer. This includes: sequentially forming the intermetallic dielectric layer on the first surface of the device wafer; etching the intermetallic dielectric layer to form a first opening and a second opening; depositing the first etch stop layer on the surface of the intermetallic dielectric layer and on the sidewalls and bottom of the first and second openings; removing the first etch stop layer from the sidewalls and bottom of the second opening; depositing an interconnect metal material layer on the surface of the remaining first etch stop layer, on the surface of the intermetallic dielectric layer, and within the first and second openings; and sequentially removing the interconnect metal material layer and the first etch stop layer from the surface of the intermetallic dielectric layer, wherein the interconnect metal material layer within the first opening is the first interconnect metal layer, and the interconnect metal layer within the second opening is the second interconnect metal layer.

[0008] In some embodiments of this application, forming a first insulating layer and a first barrier layer stacked sequentially on the sidewall of the through-silicon via (TSV), and removing the first etch stop layer at the bottom of the TSV includes: sequentially depositing a first insulating layer and a first barrier layer on the surface of the back protective layer and on the sidewall and bottom of the TSV; removing the first insulating layer and the first barrier layer on the surface of the back protective layer and the first insulating layer and the first barrier layer at the bottom of the TSV to expose the first etch stop layer; and removing the first etch stop layer exposed by the TSV.

[0009] In some embodiments of this application, forming a second barrier layer on the surface of the first barrier layer and the surface of the first interconnect metal layer at the bottom of the through-silicon via (TSV), and filling the TSV with the TSV interconnect metal layer includes: depositing the second barrier layer on the surface of the back protective layer, the surface of the first barrier layer, and the exposed surface of the first interconnect metal layer; filling the surface of the second barrier layer and the TSV with the TSV interconnect metal layer; and sequentially removing the TSV interconnect metal layer and the second barrier layer from the surface of the back protective layer.

[0010] In some embodiments of this application, thinning the second side of the device wafer after bonding the first side of the device wafer to the carrier wafer includes: sequentially forming a first interlayer metal layer and a bonding layer on the intermetallic dielectric layer, the first interconnect metal layer and the first etch stop layer of the first side of the device wafer; aligning and bonding the bonding layer to the carrier wafer; and thinning the second side of the device wafer.

[0011] In some embodiments of this application, the material of the first etch stop layer includes at least one of silicon nitride or NDC.

[0012] In some embodiments of this application, the thickness of the first etch stop layer is from 10 angstroms to 300 micrometers.

[0013] In some embodiments of this application, the material of the first barrier layer includes at least one of Ti, Ta, TiN, or TaN, and the material of the second barrier layer includes at least one of Ti, Ta, TiN, or TaN.

[0014] In some embodiments of this application, the thickness of the first barrier layer is 10 angstroms to 30 micrometers, and the thickness of the second barrier layer is 10 angstroms to 10 micrometers.

[0015] Another aspect of this application provides a through-silicon via (TSV) interconnect structure, comprising: a device wafer including a first side and a second side opposite to each other; the first side of the device wafer having an intermetallic dielectric layer, a first interconnect metal layer, and a first etch stop layer formed thereon, wherein the first etch stop layer surrounds the sidewalls and bottom of the first interconnect metal layer and is formed in the intermetallic dielectric layer; a carrier wafer bonded to the first side of the device wafer; a back protection layer located on the second side of the device wafer; a TSV penetrating the back protection layer, the device wafer, and the first etch stop layer, the TSV exposing a portion of the first interconnect metal layer; a first insulating layer and a first barrier layer sequentially stacked on the sidewalls of the TSV; a second barrier layer located on the surface of the first barrier layer and the bottom of the TSV; and a via interconnect metal layer filling the TSV.

[0016] This application provides a through-silicon via (TSV) interconnect structure and its formation method, solving the problem of metal back sputtering of the first interconnect metal layer caused during the TSV etching process in the formation of the TSV interconnect metal layer. In this application, a first etch stop layer is formed on the sidewall and bottom of the first interconnect metal layer in the front-end process. When the TSV penetrates the device wafer but the first etch stop layer is not opened, a stacked first insulating layer and a first barrier layer are sequentially formed on the sidewall of the TSV. After opening the first etch barrier layer at the TSV location to expose the first interconnect metal layer, a second barrier layer is formed. This reduces the device reliability risk caused by metal back sputtering and diffusion of the first interconnect metal layer during the TSV interconnect structure formation process on the back side of the device wafer. Furthermore, the method described in this application also reduces the process difficulty of window etching of the first interconnect metal layer and improves robustness. Attached Figure Description

[0017] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0018] in:

[0019] Figures 1 to 15 This is a schematic diagram of each step in the method for forming a through-silicon via interconnect structure according to an embodiment of this application. Detailed Implementation

[0020] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0021] This application provides a method for forming a through-silicon via (TSV) interconnect structure, including:

[0022] Step S1: Provide a device wafer, the device wafer including a first side and a second side opposite to each other, and form an intermetallic dielectric layer, a first interconnect metal layer and a first etch stop layer on the first side of the device wafer, wherein the first etch stop layer surrounds the sidewalls and bottom of the first interconnect metal layer and is formed in the intermetallic dielectric layer;

[0023] Step S2: After bonding the first side of the device wafer to the carrier wafer, the second side of the device wafer is thinned;

[0024] Step S3: A back protective layer is formed on the second side of the device wafer, and the back protective layer and the device wafer are etched sequentially to form a through-silicon via (TSV), wherein the TSV exposes the first etch stop layer;

[0025] Step S4: Form a first insulating layer and a first barrier layer stacked sequentially on the sidewall of the through silicon via, and remove the first etch stop layer at the bottom of the through silicon via;

[0026] Step S5: A second barrier layer is formed on the surface of the first barrier layer and on the surface of the first interconnect metal layer at the bottom of the through silicon via, and the through-hole interconnect metal layer is filled in the through silicon via.

[0027] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0028] Figures 1 to 15 This is a schematic diagram of each step in the method for forming a through-silicon via (TSV) interconnect structure according to an embodiment of this application. The method for forming a TSV interconnect structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0029] refer to Figure 1 As shown, a device wafer is provided, the device wafer including a first surface 10 and a second surface 20 opposite to each other, the device wafer including a semiconductor substrate 100, in which isolation structures and various active and passive devices, such as logic devices, memory devices or diodes, are formed. Figure 1 The diagram only schematically illustrates the STI structure located in the semiconductor substrate 100 and the gate structure 102 located on the surface of the semiconductor substrate. The device wafer also includes an interlayer dielectric layer 101 located on a first surface of the semiconductor substrate 100. Metal interconnects 103 are formed in the interlayer dielectric layer 101. The material of the metal interconnects 103 is, for example, copper or tungsten, and they are used to electrically connect active or passive devices formed in the semiconductor substrate. For example, the metal interconnects 103 are used to electrically connect the gate structure 102.

[0030] Reference Appendix Figure 2 To be continued Figure 6 As shown, in step S1, an intermetallic dielectric layer is formed on the interlayer dielectric layer 101 of the first surface 10 of the device wafer. The intermetallic dielectric layer may include a first intermetallic dielectric layer 104 and a second intermetallic dielectric layer 105, or it may only include the first intermetallic dielectric layer 104. The first surface 10 of the device wafer also has a first interconnect metal layer 1091 and a first etch stop layer 108 formed within the intermetallic dielectric layer. The first etch stop layer 108 surrounds the sidewalls and bottom of the first interconnect metal layer 1092. The first etch stop layer 108 and the first interconnect metal layer 1092 may or may not penetrate the intermetallic dielectric layer as a structural unit. That is, the first etch stop layer 108 and the first interconnect metal layer 1092 may or may not penetrate the second intermetallic dielectric layer 105 and the first intermetallic dielectric layer 104 as a structural unit, or they may only be formed in the second intermetallic dielectric layer 105. The following figures of the embodiments of this application describe the example of the first etch stop layer 108 and the first interconnect metal layer 1092 having a structural integral that runs through the second intermetallic dielectric layer 105 and the first intermetallic dielectric layer 104.

[0031] Reference Appendix Figure 2As shown, a first intermetallic dielectric layer 104 and a second intermetallic dielectric layer 105 are sequentially formed on the interlayer dielectric layer 101 on the first side of the device wafer. The first intermetallic dielectric layer 104 is made of silicon oxide, doped silicon nitride (NDC), silicon oxynitride, and any one or more of silicon nitride and low-dielectric-constant materials; it can be a single layer or a composite layer composed of multiple dielectric materials. The second intermetallic dielectric layer 105 is made of silicon oxide, doped silicon nitride (NDC), silicon oxynitride, and any one or more of silicon nitride and low-dielectric-constant materials; it can be a single layer or a composite layer composed of multiple dielectric materials. The process for forming the first intermetallic dielectric layer 104 and the second intermetallic dielectric layer 105 is, for example, chemical vapor deposition.

[0032] Continue to refer to the appendix Figure 2 The second intermetallic dielectric layer 105 and the first intermetallic dielectric layer 104 are etched to form a first opening 107 and a second opening 106. In this embodiment, the etching process can be wet etching or dry etching, etc. The first opening 107 is used to fill metal material to form a first interconnect metal layer, which is a metal interconnect formed through a back-side through-silicon via (TSV) in a subsequent process; the second opening is used to form a second interconnect metal layer filled with metal material. The second interconnect metal layer is used to electrically connect active devices and metal interconnects formed in the semiconductor substrate in the front-end process. The first opening 107 and the second opening 106 can be conventional through-holes or openings used to form a damascene structure.

[0033] Reference Appendix Figure 3 As shown, a first etch stop layer 108 is deposited on the surface of the second intermetallic dielectric layer 105 and on the sidewalls and bottom of the first opening 107 and the second opening 106. In this embodiment, the material of the first etch stop layer 108 includes at least one of silicon nitride or NDC. For example, the material of the first etch stop layer 108 is silicon nitride or NDC, or it can be a composite material layer composed of silicon nitride and NDC. The thickness of the first etch stop layer is 10 angstroms to 300 micrometers. The method for forming the first etch stop layer 108 is, for example, plasma chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The first etch stop layer 108 is used as an etch stop layer in the subsequent TSV process.

[0034] Reference Appendix Figure 4As shown, the first etch stop layer 108 on the sidewalls and bottom of the second opening 106 is removed, or, in this embodiment, the first etch stop layer 108 on the sidewalls and bottom of the first opening 107 is at least retained. In this embodiment, a photomask layer (not shown) can be formed on the surface of a portion of the first etch stop layer 108 and the surfaces of the first opening 107 and the second opening 106. The photomask layer at least covers the sidewalls and bottom of the first opening 107 to ensure that the first etch stop layer 108 on the sidewalls and bottom of the first opening 107 is not etched away in subsequent etching processes. Furthermore, it is necessary to ensure that the first etch stop layer 108 on the sidewalls and bottom of the second opening 106 is etched away in subsequent etching processes. Subsequently, a dry or wet etching process is used to remove the portion of the first etch stop layer 108 not covered by the photomask layer, for example, removing the first etch stop layer 108 on the sidewalls and bottom of the second opening 106. Then, the photomask layer is removed, for example, by an ashing process.

[0035] Reference Appendix Figure 5 As shown, an interconnect metal material layer 109 is deposited on the surface of the remaining first etch stop layer 108, the surface of the second intermetallic dielectric layer 105, and within the first opening 107 and the second opening 106. The interconnect metal material layer 109 is deposited using, for example, chemical vapor deposition or physical vapor deposition, or an electroplating process, and completely fills the first and second openings. The material of the interconnect metal material layer 109 is, for example, metallic copper.

[0036] Reference Appendix Figure 6As shown, the interconnect metal material layer 109 and the first etch stop layer 108 on the surface of the second intermetallic dielectric layer 105 are removed sequentially. The interconnect metal material layer 109 in the first opening 107 is the first interconnect metal layer 1091, and the interconnect metal material layer in the second opening 106 is the second interconnect metal layer 1092. In this embodiment, the method for removing the first etch stop layer 108 and the interconnect metal material layer 109 on the surface of the second intermetallic dielectric layer 105 can be a chemical mechanical polishing (CMP) process. First, the interconnect metal material layer 109 above the surface of the first etch stop layer 108 is polished, and then polishing continues until the first etch stop layer 108 above the top surface of the first opening 107 and the second opening 106 is completely removed, leaving only the interconnect metal material layer 109 located in the first opening 107 and the second opening 106. Since the interconnect metal material layers 109 in the first opening 107 and the second opening 106 are used to electrically connect different devices or wires, the interconnect metal material layer 109 in the first opening 107 is referred to as the first interconnect metal layer 1091 and the interconnect metal material layer in the second opening 106 is referred to as the second interconnect metal layer 1092 in this embodiment of the application.

[0037] Subsequently, step S2 is performed, whereby the first side of the device wafer is bonded to the carrier wafer, and then the second side of the device wafer is thinned.

[0038] In some embodiments of this application, reference is made to the appendix. Figure 7 To be continued Figure 9 Step S2, which involves bonding the first side of the device wafer to the carrier wafer and then thinning the second side of the device wafer, includes:

[0039] Step S21: Refer to Appendix Figure 7 As shown, a first interlayer metal layer 110 and a bonding layer 111 are sequentially formed on the first surface of the device wafer. Specifically, the first interlayer metal layer 110 and the bonding layer 111 are sequentially formed on the second intermetallic dielectric layer 105, the first interconnect metal layer 1091 (and the second interconnect metal layer 1092), and the first etch stop layer 108 on the first surface of the device wafer. The first interlayer metal layer 110 is made of, for example, copper, and is electrically connected to the first interconnect metal layer 1091 and the second interconnect metal layer 1092, respectively. The bonding layer 111 is made of at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, or hafnium oxide. The bonding layer 111 can be a single-layer or multi-layer stacked structure.

[0040] Step S22: Refer to Appendix Figure 8 As shown, the bonding layer 111 is aligned and bonded to the carrier wafer 200. The bonding process can be any process known to those skilled in the art.

[0041] Step S23: Refer to Appendix Figure 9 As shown, the second side 20 of the device wafer is thinned. Since the second side of the device wafer is a semiconductor substrate 100, thinning the second side of the device wafer involves thinning the second side of the semiconductor substrate 100 to a predetermined thickness. The thinning process is, for example, CMP, or it can be CMP combined with wet or dry etching processes.

[0042] Subsequently, refer to the appendix Figure 10 and attached Figure 11 As shown, step S3 is performed: a back protective layer 120 is formed on the second side of the device wafer (i.e., the second side of the semiconductor substrate 100), and the back protective layer 120 and the device wafer are sequentially etched to form a through-silicon via (TSV) 121. The TSV 121 exposes a portion of the first etch stop layer 108 at the bottom of the first interconnect metal layer 1091. The "bottom" refers to the relative position when the first side of the device wafer is facing upwards. In other words, the TSV 121 penetrates the back protective layer 120, the semiconductor substrate 100, and the interlayer dielectric layer 101.

[0043] In some embodiments of this application, the back protective layer 120 is made of any one or more of silicon oxide or silicon oxynitride. The back protective layer can be a single-layer structure or a multi-layer stacked structure, such as silicon oxide-silicon nitride, or silicon oxide-silicon nitride-silicon oxide, etc. The back protective layer 120 is used in subsequent process steps to protect the film layer on the second side of the device wafer, such as the second side of the semiconductor substrate.

[0044] In some embodiments of this application, the sequential etching of the back protective layer 120 and the device wafer to form a through-silicon via (TSV) 121 includes: forming a patterned photoresist mask on the surface of the back protective layer 120, the patterned photoresist mask including openings (not shown in the figure), the openings being used to define the position, shape, and size of the formed TSV. In this embodiment, the position of the opening corresponds to the position of the first interconnect metal layer 1091, so that the via interconnect metal layer filled in the subsequent TSV is in contact with the first interconnect metal layer 1091. Subsequently, using the patterned photoresist mask as a mask, the back protective layer 120, the semiconductor substrate 100 constituting the device wafer, and the interlayer dielectric layer 101 are sequentially etched to form the TSV 121, the TSV 121 exposing the first etch stop layer 108. The etching process of the back protective layer, the semiconductor substrate 100, and the interlayer dielectric layer 101 is, for example, wet etching or dry etching.

[0045] When the first etch stop layer 108 and the first interconnect metal layer 1092 do not penetrate the intermetallic dielectric layer, the back protective layer, the device wafer and part of the intermetallic dielectric layer can be etched sequentially to form the through-silicon via (TSV) until the TSV exposes the first etch stop layer 108.

[0046] Step S4: Refer to Appendix Figure 12 and attached Figure 13 A first insulating layer 122 and a first barrier layer 123 are formed sequentially stacked on the sidewall of the through silicon via 121, and the first etch stop layer 108 at the bottom of the through silicon via is removed.

[0047] Reference Appendix Figure 12 A first insulating layer 122 and a first barrier layer 123 are deposited on the surface of the back protective layer 120 and on the sidewalls and bottom of the through-silicon via 121. In some embodiments of this application, the first insulating layer 122 is made of silicon oxide and has a thickness of 10 angstroms to 10 micrometers. The first barrier layer is made of at least one of Ti, Ta, TiN, or TaN and has a thickness of 10 angstroms to 30 micrometers. The first barrier layer acts as a barrier layer for the metal material deposited in the subsequent through-silicon via 121, preventing the diffusion of sputtered metal material during the subsequent metal deposition process in the through-silicon via 121. In some embodiments of this application, the first barrier layer can be a single-layer or multi-layer stacked structure. For example, the first barrier layer can be a Ti single-layer or Ti / TiN stacked structure, or a Ta single-layer or Ta / TaN stacked structure.

[0048] Subsequently, refer to the appendix Figure 13 Remove the first insulating layer 122 and the first barrier layer 123 on the surface of the back protective layer 120 and the first insulating layer 122 and the first barrier layer 123 at the bottom of the through silicon via 121 to expose the first etch stop layer 108; continue etching along the through silicon via 121 to remove the first etch stop layer 108 exposed by the through silicon via until the surface of the first interconnect metal layer 1091 is exposed by the through silicon via 121.

[0049] Step S5: Refer to Appendix Figure 14 and attached Figure 15A second barrier layer 124 and a via interconnect metal layer 125 are filled into the through-silicon via 121. In some embodiments of this application, the material of the second barrier layer includes at least one of Ti, Ta, TiN, or TaN. The thickness of the second barrier layer is 10 angstroms to 10 micrometers, and the function of the second barrier layer is to prevent the diffusion of metal atoms or ions in the via interconnect metal layer 125. In some embodiments of this application, the second barrier layer can be a single-layer or multi-layer stacked structure. For example, the second barrier layer can be a Ti single-layer or Ti / TiN stacked structure, or a Ta single-layer or Ta / TaN stacked structure.

[0050] In some embodiments of this application, filling the through-silicon via 121 with a second barrier layer 124 and a via interconnect metal layer 125 includes:

[0051] Reference Appendix Figure 14 A second barrier layer 124 is deposited on the surface of the back protective layer 120, the surface of the first barrier layer 123, and the surface of the first interconnect metal layer 1091 exposed by the through silicon via 121. Then, the through-hole interconnect metal layer 125 is filled on the surface of the second barrier layer 124 and in the through silicon via 121. The second barrier layer 124 and the through-hole interconnect metal layer 125 on the surface of the back protective layer 120 are removed.

[0052] In some embodiments of this application, the material of the through-hole interconnect metal layer includes metals such as copper and tungsten.

[0053] In this embodiment of the application, the step of forming a second interlayer metal layer on the surface of the back protective layer 120 and the via interconnect metal layer may be further included, wherein the second interlayer metal layer is electrically connected to the via interconnect metal layer.

[0054] Another aspect of this application provides a through-silicon via (TSV) interconnect structure, as shown in the attached figure. Figures 1 to 15 As shown, it includes:

[0055] A device wafer, comprising a first side and a second side opposite to each other, the device wafer including a semiconductor substrate 100 and an interlayer dielectric layer 101 located on the first side of the semiconductor substrate, wherein an intermetallic dielectric layer (including a first intermetallic dielectric layer 104 and a second intermetallic dielectric layer 105), a first interconnect metal layer 1091, and a first etch stop layer 108 are formed on the first side of the device wafer, wherein the first etch stop layer 108 surrounds the sidewalls and bottom of the first interconnect metal layer 1091 and is formed in the intermetallic dielectric layer; carrier wafer 2 00, bonded to the first side of the device wafer; a back protective layer 120, located on the second side of the device wafer; a through-silicon via 121, penetrating the back protective layer 120, the device wafer, and the first etch stop layer 108, the through-silicon via 121 exposing a portion of the bottom of the first interconnect metal layer 1091; a first insulating layer 122 and a first barrier layer 123 sequentially stacked on the sidewalls of the through-silicon via; a second barrier layer 124 located on the surface of the first barrier layer 123 and the bottom of the through-silicon via; and a through-hole interconnect metal layer 125 filling the through-silicon via.

[0056] This application provides a through-silicon via (TSV) interconnect structure and its formation method, solving the problem of metal back sputtering of the first interconnect metal layer caused during the TSV etching process in the formation of the TSV interconnect metal layer. In this application, a first etch stop layer is formed on the sidewall and bottom of the first interconnect metal layer in the front-end process. When the TSV penetrates the device wafer but the first etch stop layer is not opened, a stacked first insulating layer and a first barrier layer are sequentially formed on the sidewall of the TSV. After opening the first etch barrier layer at the TSV location to expose the first interconnect metal layer, a second barrier layer is formed. This reduces the device reliability risk caused by metal back sputtering and diffusion of the first interconnect metal layer during the TSV interconnect structure formation process on the back side of the device wafer. Furthermore, the method described in this application also reduces the process difficulty of window etching of the first interconnect metal layer and improves robustness.

[0057] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0058] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0059] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0060] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0061] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a through-silicon via (TSV) interconnect structure, characterized in that, include: A device wafer is provided, the device wafer including a first side and a second side opposite to each other, an intermetallic dielectric layer, a first interconnect metal layer and a first etch stop layer are formed on the first side of the device wafer, wherein the first etch stop layer surrounds the sidewalls and bottom of the first interconnect metal layer and is formed in the intermetallic dielectric layer; After bonding the first side of the device wafer to the carrier wafer, the second side of the device wafer is thinned. A back protective layer is formed on the second side of the device wafer, and the back protective layer and the device wafer are etched sequentially to form a through-silicon via, the through-silicon via exposing the first etch stop layer; A first insulating layer and a first barrier layer are formed sequentially stacked on the sidewall of the through silicon via, and the first etch stop layer at the bottom of the through silicon via is removed; A second barrier layer is formed on the surface of the first barrier layer and on the surface of the first interconnect metal layer at the bottom of the through silicon via, and the through-hole interconnect metal layer is filled in the through silicon via.

2. The method for forming a through-silicon via (TSV) interconnect structure as described in claim 1, characterized in that, An intermetallic dielectric layer, a first interconnect metal layer, and a first etch stop layer are formed on a first surface of the device wafer, wherein the first etch stop layer surrounds the sidewalls and bottom of the first interconnect metal layer and is formed within the intermetallic dielectric layer, comprising: An intermetallic dielectric layer is sequentially formed on the first surface of the device wafer; The intermetallic dielectric layer is etched to form a first opening and a second opening; A first etch stop layer is deposited on the surface of the intermetallic dielectric layer and on the sidewalls and bottom of the first and second openings; Remove the first etch stop layer from the sidewalls and bottom of the second opening; Interconnect metal material layers are deposited on the surface of the remaining first etch stop layer, the surface of the intermetallic dielectric layer, and within the first and second openings; The interconnect metal material layer and the first etch stop layer on the surface of the intermetallic dielectric layer are removed sequentially. The interconnect metal material layer in the first opening is the first interconnect metal layer, and the interconnect metal layer in the second opening is the second interconnect metal layer.

3. The method for forming a through-silicon via (TSV) interconnect structure as described in claim 1, characterized in that, Forming a first insulating layer and a first barrier layer stacked sequentially on the sidewall of the through-silicon via (TSV), and removing the first etch stop layer at the bottom of the TSV includes: A first insulating layer and a first barrier layer are deposited sequentially on the surface of the back protective layer and on the sidewalls and bottom of the through-silicon via; Remove the first insulating layer and the first barrier layer on the surface of the back protective layer, as well as the first insulating layer and the first barrier layer at the bottom of the through silicon via, until the first etch stop layer is exposed; Remove the first etch stop layer exposed by the through silicon via.

4. The method for forming a through-silicon via (TSV) interconnect structure as described in claim 1, characterized in that, A second barrier layer is formed on the surface of the first barrier layer and on the surface of the first interconnect metal layer at the bottom of the through-silicon via (TSV), and the TSV interconnect metal layer is filled in the TSV, comprising: A second barrier layer is deposited on the surface of the back protective layer, the surface of the first barrier layer, and the surface of the exposed first interconnect metal layer; The surface of the second barrier layer and the silicon via are filled with a via interconnect metal layer; The through-hole interconnect metal layer and the second barrier layer on the surface of the back protective layer are removed sequentially.

5. The method for forming a through-silicon via (TSV) interconnect structure as described in claim 1, characterized in that, Thinning the second side of the device wafer after bonding the first side of the device wafer to the carrier wafer includes: A first interlayer metal layer and a bonding layer are sequentially formed on the intermetallic dielectric layer, the first interconnect metal layer, and the first etch stop layer on the first side of the device wafer; the bonding layer is aligned and bonded to the carrier wafer; and the second side of the device wafer is thinned.

6. The method for forming a through-silicon via (TSV) interconnect structure as described in claim 1, characterized in that, The material of the first etch stop layer includes at least one of silicon nitride or NDC.

7. The method for forming a through-silicon via (TSV) interconnect structure as described in claim 6, characterized in that, The thickness of the first etch stop layer is 10 angstroms to 300 micrometers.

8. The method for forming a through-silicon via (TSV) interconnect structure as described in claim 1, characterized in that, The material of the first barrier layer includes at least one of Ti, Ta, TiN, or TaN, and the material of the second barrier layer includes at least one of Ti, Ta, TiN, or TaN.

9. The method for forming a through-silicon via (TSV) interconnect structure as described in claim 8, characterized in that, The thickness of the first barrier layer is 10 angstroms to 30 micrometers, and the thickness of the second barrier layer is 10 angstroms to 10 micrometers.

10. A through-silicon via (TSV) interconnect structure, characterized in that, include: A device wafer, the device wafer including a first side and a second side opposite to each other, the first side of the device wafer having an intermetallic dielectric layer, a first interconnect metal layer and a first etch stop layer formed thereon, wherein the first etch stop layer surrounds the sidewalls and bottom of the first interconnect metal layer and is formed in the intermetallic dielectric layer; The carrier wafer is bonded to the first side of the device wafer; A back protective layer is located on the second side of the device wafer; A through-silicon via (TSV) penetrates the back protective layer, the device wafer, and the first etch stop layer, and exposes a portion of the first interconnect metal layer. A first insulating layer and a first barrier layer are stacked sequentially on the sidewall of the through silicon via; A second barrier layer located on the surface of the first barrier layer and at the bottom of the through-silicon via; A via interconnect metal layer that fills the silicon via.

11. The through-silicon via (TSV) interconnect structure as described in claim 10, characterized in that, The material of the first etch stop layer includes at least one of silicon nitride or NDC.

12. The through-silicon via (TSV) interconnect structure as described in claim 10, characterized in that, The thickness of the first etch stop layer is 10 angstroms to 300 micrometers.

13. The through-silicon via (TSV) interconnect structure as described in claim 10, characterized in that, The material of the first barrier layer includes at least one of Ti, Ta, TiN, or TaN, and the material of the second barrier layer includes at least one of Ti, Ta, TiN, or TaN.

14. The through-silicon via (TSV) interconnect structure as described in claim 10, characterized in that, The thickness of the first barrier layer is 10 angstroms to 30 micrometers, and the thickness of the second barrier layer is 10 angstroms to 10 micrometers.

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