Module for bonding fan-out wafer level packaging unit on electronic component through wire bonding

Abstract

The invention discloses a module for bonding a fan-out type wafer level packaging unit on an electronic component through wire bonding, which comprises the fan-out type wafer level packaging unit, the electronic component, at least one first bonding wire and at least two second bonding wires, the fan-out type wafer level packaging unit comprises a carrier plate, at least two bare chips, a first dielectric layer, a second dielectric layer, a plurality of conductive connection lines, an outer protection layer and a plurality of welding pads, wherein each conducting circuit is formed by metal paste filled in a plurality of first grooves of the first dielectric layer and a plurality of second grooves of the second dielectric layer, and at least one welding pad is positioned around the chip area of the second surface of each bare chip for external electrical connection. The invention aims to solve the problems that the fan-out type packaging technology in the existing module with the fan-out type wafer level packaging unit is easy to generate higher manufacturing cost and is not beneficial to environmental protection when each conducting circuit is manufactured.

Description

Technical Field

[0001] This invention relates to a module, and more particularly to a module in which a fan-out wafer-level packaging unit is wire-bonded to an electronic component. Background Technology

[0002] Packaging technologies that are thin, light, compact, efficient, and highly reliable are the development trend of the semiconductor industry. Among them, fan-out wafer level packaging (FOWLP) is an existing packaging technology.

[0003] In advanced FOWLP packaging, the redistribution layer (RDL) is the most critical component. The interconnects within the RDL enable XY-planar electrical extension and interconnection of multiple pads on the die, allowing for the formation of more dispersed solder pads around each die. This effectively improves the design space and reliability of the interconnects. However, the fabrication of the RDL interconnects is crucial in maintaining or achieving a certain degree of thinness and compactness while achieving XY-planar electrical extension and interconnection. Currently, the RDL interconnects in FOWLP packaging technologies are formed using chemical plating or electroplating techniques. This results in relatively high material and manufacturing costs, and the existing processes do not meet or are detrimental to environmental protection requirements. Moreover, when FOWLP aims to provide products with higher performance or more functions, it typically adopts a method of setting up at least two bare dies in FOWLP and integrating them with RDL to form a multi-chip fan-out wafer-level packaging unit. At this time, the design space requirement for each conductor in the RDL of FOWLP will increase relatively, and the manufacturing technology of each conductor in the RDL will also be relatively critical.

[0004] Furthermore, when FOWLP is used to produce modular products, it is generally integrated into RDL to form fan-out wafer-level packaging units. These fan-out wafer-level packaging units are then combined with electronic components to form modules. In this case, the material and manufacturing costs of the product will increase, and the manufacturing technology of each conductor in RDL will become more critical. Summary of the Invention

[0005] The main objective of this invention is to provide a module in which a fan-out wafer-level packaging unit is wire-bonded to an electronic component. The module includes a fan-out wafer-level packaging unit, an electronic component, at least one first bonding wire, and at least two second bonding wires. The fan-out wafer-level packaging unit includes a carrier board, at least two bare dies, a first dielectric layer, a second dielectric layer, multiple conductive lines, an outer sheath, and multiple solder pads. Each conductive line is formed by metal paste filled in multiple first grooves of the first dielectric layer and multiple second grooves of the second dielectric layer. At least one solder pad is located around the chip area on the second side of each bare die for external electrical connection. This effectively solves the problem that existing fan-out packaging technologies in modules tend to have high manufacturing costs and are environmentally unfriendly when fabricating the conductive lines.

[0006] To achieve the above objectives, the present invention provides a module for wire bonding of a fan-out wafer-level packaging unit to an electronic component. The module includes a carrier board, at least two dies, a first dielectric layer, a second dielectric layer, multiple conductive lines, an outer sheath, multiple solder pads, an electronic component, at least one first bonding wire, and at least two second bonding wires. The carrier board has a first surface and an opposing second surface. Each die is diced from the same wafer or different wafers, and each die is arranged parallel and spaced apart. On the second surface of the carrier substrate, each die has a first surface and an opposite second surface. The first surface of each die is fixedly disposed on the carrier substrate. The second surface of each die has multiple die pads, and the vertical chip region of the second surface defines a chip region. A first dielectric layer is disposed on the second surface of the carrier substrate and on the second surface of each die. The first dielectric layer has multiple horizontally extending first grooves. Each die pad of each die is exposed externally by the multiple first grooves. A second dielectric layer is disposed on... On the first dielectric layer, the second dielectric layer has a plurality of horizontally extending second grooves, which communicate with the plurality of first grooves; each conductive line is formed by filling the plurality of first grooves and the plurality of second grooves with a metal paste, and each conductive line is electrically connected to each of the die pads of each bare die; an outer sheath is disposed on the second dielectric layer, and the outer sheath has a plurality of openings, wherein at least two of the openings are located around the chip area on the second surface of each bare die, wherein each conductive line... The circuitry is exposed to the outside through multiple openings; each solder pad is a metal structure of a certain thickness formed within the multiple openings of the outer sheath, and is electrically connected to each conductive line; each bare die can be electrically connected to the outside via the die pad, the conductive line, and the solder pad surrounding the chip area on the second surface of the bare die, thereby forming a fan-out wafer-level package unit; the electronic component has a first surface on which the first surface of the carrier board is disposed; each first bonding wire is bonded via a wire bonding process. The bonding operation forms a first solder joint and a second solder joint on each pad in each of the bare dies, thereby electrically connecting each of the bare dies of the fan-out wafer-level packaging unit; wherein each second solder joint is formed by the wire bonding operation to form a third solder joint on each pad around the chip region and a fourth solder joint on the first surface of the electronic component, thereby electrically connecting each of the bare dies of the fan-out wafer-level packaging unit to the printed circuit board; wherein each first solder joint and each second solder joint are formed together simultaneously by the wire bonding operation; wherein the manufacturing method of the module includes the following steps: Step S1: providing a carrier board; wherein the carrier board has a first surface and an opposite second surface;Step S2: Multiple dies, cut from the same or different wafers, are arranged side-by-side in parallel and spaced intervals on the second surface of the carrier substrate. Each die has a first surface and an opposite second surface. The first surface of each die is disposed on the carrier substrate. The second surface of each die has multiple die pads, and the vertical chip area of ​​the second surface of each die defines a chip area. Step S3: A first dielectric layer is deposited on the carrier substrate and the second surface of each die. Step S4: Extend and form multiple first grooves horizontally on the first dielectric layer, so that each pad of each bare die can be exposed to the outside through the multiple first grooves; Step S5: Lay a second dielectric layer on the first dielectric layer; Step S6: Extend and form multiple second grooves horizontally on the second dielectric layer, so that the multiple second grooves can communicate with the multiple first grooves; Step S7: Fill the multiple first grooves and multiple second grooves with a metal paste, and make the thickness of the metal paste higher than the surface of the second dielectric layer; Step S8: Grind the metal paste above the surface of the second dielectric layer so that the surface of the metal paste is flush with the surface of the second dielectric layer to form multiple conductive lines; Step S9: Lay an outer sheath on the second dielectric layer; Step S10: Form multiple openings in the outer sheath, with at least one opening formed around the chip area on the second surface of each bare die, so that each conductive line can be exposed to the outside through each opening; Step S11: Form a solder pad in each opening of the outer sheath, wherein each The solder pad is a metal structure with a certain thickness, wherein each solder pad is electrically connected to each conductive line; Step S12: Perform a dicing operation to form a plurality of fan-out wafer-level packaging units; wherein each fan-out wafer-level packaging unit has at least two bare dies; Step S13: Provide an electronic component having a first surface, and place the first surface of the carrier of one fan-out wafer-level packaging unit on the first surface of the electronic component; Step S14: Perform a wire bonding operation. Bonding is used to form a first solder joint and a second solder joint on each pad of each die in each of the fan-out wafer-level packaging units by at least one first bonding wire, and a third solder joint on each pad around the chip region of the fan-out wafer-level packaging unit by at least two second bonding wires, and a fourth solder joint on the electronic component; wherein each die in the fan-out wafer-level packaging unit on the electronic component is electrically connected through each of the first bonding wires, and each die in the fan-out wafer-level packaging unit on the electronic component is electrically connected to the electronic component through each of the second bonding wires, thereby forming a module.

[0007] In a preferred embodiment of the present invention, the electronic component is a printed circuit board (PCB).

[0008] In a preferred embodiment of the present invention, the surface of each of the solder pads is flush with the surface of the outer sheath.

[0009] In a preferred embodiment of the present invention, each of the bare dies is formed by dicing from the same wafer or different wafers.

[0010] In a preferred embodiment of the invention, the horizontal height of each of the second surfaces of each bare die on the carrier is the same.

[0011] In a preferred embodiment of the present invention, the carrier is a silicon (Si) carrier, a glass carrier, or a ceramic carrier.

[0012] In a preferred embodiment of the present invention, the metal paste comprises silver paste, nano-silver paste, copper paste, or nano-copper paste.

[0013] In a preferred embodiment of the present invention, the first side of each bare die is further disposed on the carrier using a die attach film (DAF). Attached Figure Description

[0014] Figure 1 This is a side cross-sectional view of the module of the present invention.

[0015] Figure 2 This is a side cross-sectional view of the bare die of the present invention disposed on a carrier plate.

[0016] Figure 3 This is a side cross-sectional view of the first dielectric layer of the present invention disposed on the second surface of the carrier plate and the bare die.

[0017] Figure 4 This is a side cross-sectional view of the second dielectric layer disposed on the first dielectric layer according to the present invention.

[0018] Figure 5 This is a side cross-sectional view of the first and second grooves of the present invention filled with metal paste.

[0019] Figure 6 yes Figure 5 A side cross-sectional view of the metal paste on the surface of the middle layer above the second dielectric layer being polished.

[0020] Figure 7 This is a side cross-sectional view of the outer protective layer of the present invention with multiple openings.

[0021] Figure 8 This is a side cross-sectional view of the fan-out wafer-level packaging unit of the present invention.

[0022] Figure reference numerals: 1-Module; 1a-Fan-out wafer-level packaging unit; 10-Carrier board; 10a-Chip area; 11-First side; 12-Second side; 20-Bare die; 20a-First chip; 20b-Second chip; 21-First side; 22-Second side; 23-Die pad; 30-First dielectric layer; 31-First groove; 40-Second dielectric layer; 41-Second groove; 50-Conductive line; 50a-Metal paste; 60-Outer sheath; 61-Opening; 70-Solder pad; 80-Electronic component; 81-First side; 90-First bonding wire; 91-First solder joint; 92-Second solder joint; 100-Second bonding wire; 101-Third solder joint; 102-Fourth solder joint; 110-Chip bonding film. Detailed Implementation

[0023] The structure and technical features of the present invention are described in detail below with reference to the illustrations. The illustrations are only used to illustrate the structural relationships and related functions of the present invention. Therefore, the dimensions of the components in the illustrations are not drawn to actual scale and are not intended to limit the present invention.

[0024] refer to Figure 1 The present invention provides a module 1 for wire bonding a fan-out wafer-level packaging unit to an electronic component. The module 1 includes a fan-out wafer-level packaging unit 1a, an electronic component 80, at least one first bonding wire 90 and at least two second bonding wires 100.

[0025] refer to Figure 8 The fan-out wafer-level packaging unit 1a includes a carrier 10, at least two dies 20, a first dielectric layer 30, a second dielectric layer 40, multiple conductive lines 50, an outer sheath 60, and multiple solder pads 70.

[0026] The carrier plate 10 has a first surface 11 and an opposite second surface 12, such as Figure 2 As shown, the substrate 10 may be a silicon (Si) substrate, a glass substrate, or a ceramic substrate, but is not limited thereto, in order to facilitate diversified product development applications.

[0027] Each bare die 20 is cleaved from the same wafer or different wafers, and each bare die 20 is arranged parallel and spaced apart on the second surface 12 of the carrier plate 10, as shown below. Figure 2 As shown, each die 20 has a first surface 21 and an opposite second surface 22. The first surface 21 of each die 20 is fixedly disposed on the carrier 10. The second surface 22 of each die has a plurality of die pads 23, and the vertical chip region of the second surface 22 defines a chip region 10a. Figure 2 As shown. In Figure 2The example of each bare die 20 having a crystal pad 23 is given with two crystal pads 23, but it is not intended to limit the present invention.

[0028] Furthermore, in order to illustrate the structural relationships and related functions of the present invention, the present invention... Figures 1 to 8 In the embodiment shown, each bare die 20 on the carrier 10 further includes a first bare die 20a and a second bare die 20b, but this is not a limitation. That is, each bare die 20 is illustrated by example with two, but it is not intended to limit the present invention.

[0029] The first dielectric layer 30 is disposed on the second surface 12 of the carrier plate 10 and on the second surface 22 of each bare die 20 (the first bare die 20a and the second bare die 20b). The first dielectric layer 30 has multiple first grooves 31 formed extending horizontally, such as... Figure 3 As shown; in which each crystal pad 23 of each bare crystal 20 (the first bare crystal 20a and the second bare crystal 20b) is exposed to the outside by each first groove 31, as shown. Figure 3 As shown.

[0030] The second dielectric layer 40 is disposed on the first dielectric layer 40. The second dielectric layer 40 has multiple second grooves 41 extending horizontally, and each second groove 41 communicates with each first groove 31. Figure 4 As shown.

[0031] Each conductive line 50 is formed by a metal paste 50a filled in each first groove 31 and each second groove 41. Each conductive line 50 is electrically connected to each pad 23 of each bare die 20 (the first bare die 20a and the second bare die 20b). Figure 6 As shown; wherein the metal paste 50a may contain silver paste, nano-silver paste, copper paste, or nano-copper paste, but is not limited thereto. The nano-silver paste material has the characteristics of low cost, high conductivity, and low-temperature sintering capability, but since nano-silver paste material is a commonly used material, it will not be described in detail here.

[0032] The outer sheath 60 is disposed on the second dielectric layer 40. The outer sheath 60 has a plurality of openings 61, and at least two of the openings 61 are located around the chip region 10a on the second surface 22 of each bare die 20 (the first bare die 20a and the second bare die 20b), such as... Figure 7 As shown; each conductive line 50 is exposed to the outside through its respective opening 61, as... Figure 7 As shown. In Figure 7 The openings 61 of the outer protective layer 60 are described using four openings 61 as an example, but are not intended to limit the invention.

[0033] Each solder pad 70 is a metal structure of a certain thickness formed within each opening 61 of the outer sheath 60, and is electrically connected to each conductive line 50, such as... Figure 8 As shown; each bare die 20 (the first bare die 20a and the second bare die 20b) can be electrically connected to the external circuitry via each die pad 23, each conductive line 50, and each solder pad 70 located around the chip region 10a on the second surface 22 of each bare die 20 (the first bare die 20a and the second bare die 20b), thereby forming the fan-out wafer-level package unit 1a, as shown. Figure 8 As shown.

[0034] The electronic component 80 has a first surface 81 on which the first surface 11 of the carrier plate 10 of the fan-out wafer-level packaging unit 1a is disposed, such as Figure 1 As shown; wherein the electronic component 80 is a printed circuit board (PCB), but is not limited thereto.

[0035] Each first bonding wire 90 is formed by a wire bonding operation to create a first solder joint 91 and a second solder joint 92 on each pad 70 in each bare die 20 (the first bare die 20a and the second bare die 20b), thereby forming an electrical connection between each bare die 20 (the first bare die 20a and the second bare die 20b) of the fan-out wafer-level packaging unit 1a. Figure 1 As shown.

[0036] Furthermore, in order to illustrate the structural relationships and related functions of the present invention, the present invention... Figure 1 In the illustrated embodiment, the solder joint on the first bare die 20a is the first solder joint 91, but not limited thereto; the solder joint on the second bare die 20b is the second solder joint 92, but not limited thereto. That is, each first bonding wire 90 is illustrated as a single example, but is not intended to limit the invention. Furthermore, each first bonding wire 90 is further wire-bonded to two adjacent pads 70 in each bare die 20 (the first bare die 20a and the second bare die 20b), but not limited thereto, to complete the electrical connection between the pads within the shortest distance between the bare dies. This not only saves manufacturing costs but also avoids cross-line states in the package. The aforementioned cross-line state refers to any bonding wire that spans between any pad and its corresponding pad, which crosses the space above other pads, causing signal interference between the pads and bonding wires. This is a common drawback in existing packages and will not be elaborated upon here.

[0037] Each second bonding wire 100 is formed by the wire bonding operation to create a third solder joint 101 on each pad 70 around the chip region 10a and a fourth solder joint 102 on the first surface 81 of the electronic component 80, thereby forming an electrical connection between each die 20 (the first die 20a and the second die 20b) of the fan-out wafer-level packaging unit 1a and the printed circuit board 70. Figure 1 As shown.

[0038] Furthermore, in order to illustrate the structural relationships and related functions of the present invention, the present invention... Figure 1 In the illustrated embodiment, the solder joints on each pad 70 surrounding the chip region 10a of the first bare die 20a are the third solder joints 101, but not limited thereto; and the solder joints on each pad 70 surrounding the chip region 10a of the second bare die 20b are the third solder joints 101, but not limited thereto. The solder joints on the first surface 81 of the electronic component 80 adjacent to the chip region 10a of the first bare die 20a are the fourth solder joints 102, but not limited thereto; and the solder joints on the first surface 81 of the electronic component 80 adjacent to the chip region 10a of the second bare die 20b are the fourth solder joints 102, but not limited thereto. That is, each second bonding wire 100 is illustrated with two wires as an example, but is not intended to limit the invention.

[0039] refer to Figure 1 Each first bonding line 90 and each second bonding line 100 are formed simultaneously through the wire bonding operation to simplify the process.

[0040] The manufacturing method of module 1 includes the following steps:

[0041] Step S1: Provide a carrier board 10, such as Figure 2 As shown; wherein the carrier plate 10 has a first surface 11 and an opposite second surface 12, as... Figure 2 As shown.

[0042] Step S2: Multiple bare dies 20, cut from the same or different wafers, are arranged parallel and spaced apart on the second surface 12 of the carrier plate 10, such as... Figure 2 As shown; each die 20 has a first surface 21 and an opposite second surface 22. The first surface 21 of each die 20 is disposed on the carrier substrate 10, and the second surface 22 of each die 20 has a plurality of die pads 23. The vertical chip region of the second surface 22 of each die 20 is defined as a chip region 10a, as shown. Figure 2 As shown.

[0043] Step S3: A first dielectric layer 30 is deposited on the second surface 22 of the carrier 10 and each bare die 20, such as... Figure 3 As shown.

[0044] Step S4: Multiple first grooves 31 are formed horizontally on the first dielectric layer 30, allowing each pad 23 of each bare die 20 to be exposed through each first groove 31, such as... Figure 3 As shown.

[0045] Step S5: Deposit a second dielectric layer 40 on the first dielectric layer 30, such as... Figure 4 As shown.

[0046] Step S6: Multiple second grooves 41 are formed horizontally on the second dielectric layer 40, and each second groove 41 is made to communicate with each first groove 31, such as... Figure 4 As shown.

[0047] Step S7: Fill each first groove 31 and each second groove 41 with a metal paste 50a, such that the thickness of the metal paste 50a is higher than the surface of the second dielectric layer 40, for example... Figure 5 As shown.

[0048] Step S8: The metal paste 50a, which is higher than the surface of the second dielectric layer 40, is ground so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form multiple conductive lines 50, such as... Figure 6 As shown.

[0049] Step S9: Lay an outer sheath 60 on the second dielectric layer 40, such as... Figure 7 As shown.

[0050] Step S10: A plurality of openings 61 are formed in the outer sheath 60, and at least one of the openings 61 is formed around the chip region 10a on the second surface 22 of each bare die 20, so that each conductive line 50 can be exposed to the outside through each opening 61, such as... Figure 7 As shown.

[0051] Step S11: Form a solder pad 70 in each opening 61 of the outer sheath 60, such as... Figure 8 As shown; each solder pad 70 is a metal structure with a certain thickness, such as... Figure 8 As shown; each solder pad 70 is electrically connected to each conductive line 50, such as... Figure 8 As shown.

[0052] Step S12: Perform a dicing operation to form multiple fan-out wafer-level packaging units 1a, such as... Figure 8 As shown; each fan-out wafer-level packaging unit 1a has at least two bare dies 20, such as Figure 8 As shown.

[0053] Step S13: Provide an electronic component 80 having a first surface 81, and place the first surface 11 of the carrier plate 10 of the fan-out wafer-level packaging unit 1a on the first surface of the electronic component 80, such as... Figure 1 As shown.

[0054] Step S14: Perform a wire bonding operation to form a first solder joint 91 and a second solder joint 92 on each pad 70 in each bare die 20 of the fan-out wafer-level packaging unit 1a by at least one first bonding wire 90, and to form a third solder joint 101 on each pad 70 around the chip region 10a of the fan-out wafer-level packaging unit 1a by at least two second bonding wires 100, and to form a fourth solder joint 102 on the electronic component 80. Figure 1 As shown; wherein each bare die 20 within the fan-out wafer-level packaging unit 1a on the electronic component 80 is electrically connected via each first bonding wire 90, as... Figure 1 As shown; wherein each bare die 20 in the fan-out wafer-level packaging unit 1a on the electronic component 80 is electrically connected to the electronic component 80 through each second bonding wire 100, thereby forming a module 1, as shown. Figure 1 As shown.

[0055] Steps S3 to S10 in the manufacturing method of module 1 described above can be considered as key steps in fabricating the redistribution layer (RDL) of the fan-out wafer-level packaging unit 1a. Specifically, step S4 involves forming multiple first grooves 31 extending horizontally on the first dielectric layer 30; step S6 involves forming multiple second grooves 41 extending horizontally on the second dielectric layer 40; step S7 involves filling each first groove 31 and each second groove 41 with a metal paste 50a; and step S8 involves grinding the metal paste 50a above the surface of the second dielectric layer 40 so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40, thus forming multiple... Since steps S4 to S8 are easy to implement precisely, the process is relatively simple. This allows each conductor 50 in the redistribution layer to maintain or achieve a certain degree of thinness and compactness while generating XY plane electrical extension and interconnection. This also ensures that the completed fan-out wafer-level packaging unit 1a can still maintain or achieve a certain degree of thinness and compactness even when there are at least two bare dies 20 in the fan-out wafer-level packaging unit 1a.

[0056] refer to Figure 1The surface of each solder pad 70 is flush with the surface of the outer sheath 60, but not restricted, so that the wire bonding operation can be easily performed on the surface of each solder pad 70, thereby improving the reliability of the product. In addition, each solder pad 70 is subjected to the positive pressure generated during the wire bonding operation or the formation of solder joints, so that the internal circuitry is not damaged by the positive pressure, and the internal circuitry (such as each conductive line 50) can be allowed to pass through or be arranged under each solder pad 70.

[0057] refer to Figure 2 When each bare die 20 is formed by dividing from the same wafer, each bare die 20 is a bare die with the same specifications, performance or intended function, but is not limited thereto.

[0058] refer to Figure 2 When each bare die 20 is formed from different wafers, it is beneficial to increase the versatility of product applications. Each bare die 20 can be a bare die with different specifications, performance, or intended function, but there are no restrictions. Figure 2 The first bare crystal 20a is smaller than the second bare crystal 20b.

[0059] refer to Figure 2 The horizontal height of each second surface 22 of each bare die 20 on the carrier 10 is the same, but not limited, so that each first groove 31 of the first dielectric layer 30 and each second groove 41 of the second dielectric layer 40 formed by the RDL technology can be extended and formed flatly, which helps the structure subsequently stacked on each bare die 20 to maintain better structural flatness and increase product reliability.

[0060] refer to Figure 2 Each bare die 20's first surface 21 is further disposed on the carrier 10 using a die attach film (DAF) 110, but this is not a limitation.

[0061] Compared with existing module technologies with fan-out wafer-level packaging units, the module 1 of this invention has the following advantages:

[0062] (1) The fan-out wafer-level packaging unit 1a manufactured by steps S3 to S10 in the manufacturing method of module 1 of the present invention, compared with the relevant manufacturing technology of existing fan-out wafer-level packaging units in modules, the fan-out wafer-level packaging unit 1a of the present invention, through the fabrication of each conductive line in the RDL, enables each conductive line in the RDL to generate XY plane electrical extension and interconnection, while maintaining or achieving a certain degree of thinness and small size. These are all simplified and easy to implement precisely, which is especially beneficial to reduce the thickness of the packaging unit. Therefore, the process of the present invention is not only simpler and saves costs, but also effectively improves the efficiency and reliability of module 1.

[0063] (2) The method for forming each conductive line 50 of the fan-out wafer-level packaging unit 1a in module 1 of the present invention is to first fill the metal paste 50a into each first groove 31 and each second groove 41, and the thickness of the metal paste 50a is higher than the surface of the second dielectric layer 40, such as... Figure 5 As shown, the metal paste 50a, which is higher than the surface of the second dielectric layer 40, is then polished so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form each conductive line 50, as shown. Figure 6 As shown, this invention effectively solves the problems of high manufacturing costs and environmental impact associated with existing fan-out packaging technologies when fabricating various conductive lines. Therefore, the module 1 formed by integrating the fan-out wafer-level packaging unit 1a with the RDL of this invention onto the electronic component 80 will have relatively lower material and manufacturing costs.

[0064] (3) In the module 1 of the present invention, each bare die 20 of the fan-out wafer-level packaging unit 1a can be electrically connected to the outside via each die pad 23, each conductive line 50 (formed by RDL technology) and each solder pad 51 located around the chip region 1a on the second surface 22 of each bare die 20. That is, when each conductive line in the RDL generates XY plane electrical extension and interconnection, it can also enable the multi-chip type fan-out wafer-level packaging unit to maintain or achieve a certain degree of thin and small integration effect, so as to provide module products with higher performance (such as each bare die 20 is a bare die with the same specifications, performance or intended function) or more functions (such as each bare die 20 is a bare die with different specifications, performance or intended function), thereby increasing the market competitiveness of the module products.

[0065] The above are merely preferred embodiments of the present invention and are illustrative rather than restrictive. Those skilled in the art will understand that many changes, modifications, and even equivalent alterations can be made within the spirit and scope defined by the claims of the present invention, but all such changes will fall within the protection scope of the present invention.

Claims

1. A module in which a fan-out wafer-level packaging unit is wire-bonded to an electronic component, characterized in that, Include: A carrier plate having a first surface and an opposite second surface; At least two bare dies, each of which is cleaved from the same wafer or different wafers, each of which is arranged parallel and spaced apart on the second surface of the carrier, each of which has a first surface and an opposite second surface, the first surface of each of which is fixedly disposed on the carrier, and the second surface of each of which has a plurality of die pads, and the vertical chip area of ​​the second surface is defined as a chip area; A first dielectric layer is disposed on the second surface of the carrier and on the second surface of each bare die. The first dielectric layer has a plurality of first grooves formed in a horizontal direction. Each pad of each bare die is exposed to the outside by the plurality of first grooves. A second dielectric layer is disposed on the first dielectric layer, the second dielectric layer having a plurality of second grooves formed extending horizontally, the plurality of second grooves being connected to the plurality of first grooves; Multiple conductive lines, each of which is composed of a metal paste filled in multiple first grooves and multiple second grooves, and each conductive line is electrically connected to each of the crystal pads of each bare die; An outer sheath is disposed on the second dielectric layer, the outer sheath having a plurality of openings, wherein at least two of the openings are located around the chip region on the second surface of each bare die; Each of these conductive lines is exposed to the outside by each of these openings; Multiple solder pads, each solder pad being a metal structure of a certain thickness formed within multiple openings of the outer sheath, and electrically connected to each conductive line; wherein each bare die can be electrically connected to the outside via the die pad, the conductive line, and the solder pads surrounding the chip area on the second surface of the bare die in sequence, thereby forming a fan-out wafer-level packaging unit. An electronic component having a first surface on which the first surface of the carrier plate is disposed; At least one first bonding wire, each first bonding wire being formed by a wire bonding operation to create a first solder joint and a second solder joint on each pad in each of the bare dies, thereby creating an electrical connection between each of the bare dies of the fan-out wafer-level package unit; and At least two second bonding wires, each of which is formed by the wire bonding operation to form a third solder joint on each of the pads around the chip region and a fourth solder joint on the first surface of the electronic component, such that each die of the fan-out wafer-level packaging unit is electrically connected to the printed circuit board. Each of the first bonding wires and each of the second bonding wires are formed together simultaneously through the wire bonding operation; The manufacturing method of this module includes the following steps: Step S1: Provide a carrier plate; wherein the carrier plate has a first side and an opposite second side; Step S2: Multiple bare dies cut from the same or different wafers are arranged side by side in parallel and spaced intervals on the second surface of the carrier; wherein each bare die has a first surface and an opposite second surface, the first surface of each bare die is disposed on the carrier, the second surface of each bare die has multiple die pads, and the vertical chip area of ​​the second surface of each bare die is defined as a chip area; Step S3: Deposit a first dielectric layer on the second surface of the carrier and each bare die; Step S4: Extend and form multiple first grooves horizontally on the first dielectric layer, so that each of the pads of each bare die can be exposed to the outside through the multiple first grooves; Step S5: Lay a second dielectric layer on the first dielectric layer; Step S6: Extend and form multiple second grooves horizontally on the second dielectric layer, and make the multiple second grooves communicate with the multiple first grooves; Step S7: Fill a plurality of the first grooves and the plurality of the second grooves with a metal paste, and make the thickness of the metal paste higher than the surface of the second dielectric layer; Step S8: Grind the metal paste that is above the surface of the second dielectric layer so that the surface of the metal paste is flush with the surface of the second dielectric layer to form multiple conductive lines; Step S9: Lay an outer sheath on the second dielectric layer; Step S10: Form a plurality of openings in the outer sheath and form at least one of the openings around the chip area on the second surface of each bare die, so that each conductive line can be exposed to the outside through each opening; Step S11: Form a solder pad in each of the openings in the outer sheath; wherein each solder pad is a metal structure with a certain thickness; wherein each solder pad is electrically connected to each conductive line. Step S12: Perform a dicing operation to form a plurality of fan-out wafer-level packaging units; wherein each fan-out wafer-level packaging unit has at least two bare dies; Step S13: Provide an electronic component having a first surface, and place the first surface of the carrier of the fan-out wafer-level packaging unit on the first surface of the electronic component; and Step S14: Perform a wire bonding operation to form a first solder joint and a second solder joint on each pad of each die in each of the fan-out wafer-level packaging units by at least one first bonding wire, and a third solder joint on each pad around the chip region of the fan-out wafer-level packaging unit by at least two second bonding wires, and a fourth solder joint on the electronic component; wherein each die in the fan-out wafer-level packaging unit on the electronic component is electrically connected through each of the first bonding wires; wherein each die in the fan-out wafer-level packaging unit on the electronic component and the electronic component are electrically connected through each of the second bonding wires, thereby forming a module.

2. The module as described in claim 1, characterized in that, The electronic component is a printed circuit board.

3. The module as described in claim 1, characterized in that, The surface of each solder pad is flush with the surface of the outer sheath.

4. The module as described in claim 1, characterized in that, Each of these bare crystals is formed by dicing from the same wafer or different wafers.

5. The module as described in claim 1, characterized in that, The horizontal height of each of the second faces of each bare die on the carrier is the same.

6. The module as described in claim 1, characterized in that, The carrier can be a silicon carrier, a glass carrier, or a ceramic carrier.

7. The module as described in claim 1, characterized in that, The metal paste may contain silver paste, nano silver paste, copper paste, or nano copper paste.

8. The module as described in claim 1, characterized in that, The first side of each bare die is disposed on the carrier using a chip bonding film.

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