Test structure and method for local mismatch offset rate in SPICE model

Abstract

The invention discloses a test structure and method for a local mismatch offset rate in an SPICE model, the test structure comprises a first transistor and a second transistor, the first transistor and the second transistor respectively comprise four test ends, namely a first source end, a first drain end, a gate end and a substrate end, and the first transistor and the second transistor also respectively comprise two test ends, namely a second source end and a second drain end. According to the test structure and method for the local mismatch offset rate in the SPICE model provided by the invention, the two transistors in the test structure are respectively provided with six test ends, so that the test accuracy is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and particularly relates to a test structure and method of local mismatch offset rate in a SPICE model. BACKGROUND

[0002] In the field of current electronic technology, metal-oxide-semiconductor field-effect transistors (Mosfet, Metal-Oxide-Semiconductor Field-Effect Transistor) are widely used in various integrated circuits due to their excellent electrical performance. However, in the actual manufacturing and application of transistors, the problem of local mismatch (Mosfet local mismatch) gradually becomes a key factor restricting the performance of the circuit. Local mismatch refers to the phenomenon that, due to the non-ideality of the manufacturing process (such as lithography precision deviation, film thickness unevenness, doping concentration fluctuation, etc.), the threshold voltage, transconductance, drain-source current and other key electrical parameters of MOSFET devices prepared on the same chip (chip) or in the same batch are slightly different. This difference can cause many serious consequences, for example, in analog circuits (such as operational amplifiers, reference voltage sources, etc.), it can seriously affect the accuracy of the circuit, cause signal processing deviation, and thus reduce the performance of the entire system; in digital circuits (such as logic gates, memory cells, etc.), it can cause timing disorder of the circuit, increase the bit error rate of data transmission, and pose a serious threat to the stability and reliability of the system.

[0003] Currently, when testing the local mismatch effect of low-voltage transistors using a SPICE (Simulation Program with Integrated Circuit Emphasis) model, the commonly used is a four-terminal (4T:D / G / S / B) transistor mismatch structure. In this design, the key factor 1 / sqrt (W·L) (inverse of the square root of width-length product) can be as small as 0.1 range, where W is the channel width of the transistor and L is the channel length of the transistor, as shown in Figure 1 and Figure 2 .

[0004] In actual tests, as the channel area (W*L) of the transistor increases, the value of the key factor 1 / sqrt (W*L) of the mismatch standard deviation (mismatch sigma) gradually decreases, and when the key factor 1 / sqrt (W*L) is less than 0.1 and tends to 0, the curve slope of the value of the mismatch standard deviation changing with the key factor 1 / sqrt (W*L) can have two possibilities, one is that the slope is upturned, and the other is that the slope is gently approaching the origin. The change trend of the slope directly determines the size of the offset of the mismatch standard deviation, but the trend rule has not been clearly defined in the prior art, resulting in the inability to accurately quantify the offset of the mismatch standard deviation; and the offset of the mismatch standard deviation directly affects the accuracy of the mismatch model (mismatch model) in the SPICE model, ultimately leading to the existence of deviation in the MOSFET electrical parameter measurement results based on the mismatch model, which is difficult to meet the test requirements of high-precision circuit design.

[0005] Therefore, a test structure capable of improving test accuracy is needed to provide a measurement offset for a mismatch structure with a key factor 1 / sqrt (W*L) less than 0.1. SUMMARY

[0006] In view of the above problems, the present application provides a test structure and method for local mismatch offset rate in a SPICE model, which improves the accuracy of the test by providing six test terminals for each of the two transistors in the test structure.

[0007] According to a first aspect of the present application, a test structure for local mismatch offset rate in a SPICE model is provided, comprising: a first transistor and a second transistor, the first transistor and the second transistor each comprising four test terminals of a first source terminal, a first drain terminal, a gate terminal and a substrate terminal, wherein the first transistor and the second transistor each further comprise two test terminals of a second source terminal and a second drain terminal.

[0008] Optionally, in the first transistor or the second transistor, the first source terminal is a predetermined distance away from the second source terminal, and the first drain terminal is a predetermined distance away from the second drain terminal.

[0009] Optionally, the distance between the first source terminal and the gate terminal is greater than the distance between the second source terminal and the gate terminal, and the distance between the first drain terminal and the gate terminal is greater than the distance between the second drain terminal and the gate terminal.

[0010] Optionally, the gate of the first transistor and the second transistor comprises a plurality of interdigital fingers.

[0011] Optionally, the leading ends of the plurality of interdigital fingers are connected via a first metal layer; and / or the trailing ends of the plurality of interdigital fingers are connected via a first metal layer.

[0012] Optionally, the plurality of interdigital fingers have the same length and width.

[0013] Optionally, the plurality of interdigital fingers have the same length and width.

[0014] Optionally, the plurality of interdigital fingers have the same length and width.

[0015] Optionally, the first transistor and or the second transistor comprise: a substrate; an epitaxial layer on the substrate; a body region, a source region and a drain region in the epitaxial layer; a gate on the epitaxial layer, the source region and the drain region are located in the body region on both sides of the gate, the substrate end is electrically connected with the substrate, the gate end is electrically connected with the gate, the first drain end and the second drain end are electrically connected with the drain region, and the first source end and the second source end are electrically connected with the source region.

[0016] According to another aspect of the present application, a test method for local mismatch offset rate in a SPICE model is provided, comprising: testing the local mismatch offset rate by using the test structure for local mismatch offset rate in a SPICE model.

[0017] The unexpected technical effects of the present application are: The test structure and method for local mismatch offset rate in a SPICE model according to the embodiments of the present application, two transistors in one test structure are respectively provided with six test ends, including a gate end, a substrate end, a first source end, a second source end, a first drain end and a second drain end, compared with four test ends in a traditional test structure, the test structure provided by the present application separates the test signal application loop and the test result acquisition loop, reduces the mutual influence between them, and the terminals in the test result acquisition loop are closer to the substrate and the gate end of the transistor, which can reduce the influence of parasitic resistance in the circuit and improve the measurement accuracy.

[0018] Further, the test structure and method for local mismatch offset rate in a SPICE model according to the present application, for a large-area transistor mismatch structure, the transistor is set to an interdigital structure, so that a large-area transistor mismatch structure includes a plurality of interdigital fingers, thereby the simulation test of the transistor mismatch structure with uniform area and different length, the transistor mismatch structure with different area and different length, the transistor mismatch structure with the same length and different width, the transistor mismatch structure with the same width and different length, etc. can be realized, and the layout area can be maximally reduced and the mask cost can be saved. Meanwhile, for a small-area transistor mismatch structure, the local mismatch model simulation under different conditions can also be more accurately simulated. BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which: Figure 1 A measured data and a model fitting line of a standard deviation of local mismatch of a transistor device in the prior art versus the reciprocal of the square root of the device area are shown in a schematic diagram; Figure 2 A schematic diagram of a test structure of a local mismatch offset rate in a SPICE model in the prior art is shown; Figure 3 A schematic diagram of a standard deviation of local mismatch of a transistor device versus the reciprocal of the square root of the device area according to an embodiment of the present application is shown; Figure 4 A semiconductor top view schematic diagram of a test structure of a local mismatch offset rate in a SPICE model according to an embodiment of the present application is shown; Figure 5 A circuit structure schematic diagram of a test structure of a local mismatch offset rate in a SPICE model according to an embodiment of the present application is shown; Figure 6 A layout structure schematic diagram of a test structure of a local mismatch offset rate in a SPICE model according to an embodiment of the present application is shown; Figure 7 A flow chart of a test method of a local mismatch offset rate in a SPICE model according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0020] The present application will be described in more detail with reference to the drawings. Like elements in the drawings are denoted by like reference numerals throughout. Each part in the drawings is not drawn to scale for the sake of clarity. Also, some known elements can not be shown. The present application can be embodied in various forms, some of which will be described below.

[0021] The present application can be embodied in various forms, some of which will be described below.

[0022] Local mismatch of a transistor, taking a metal-oxide-semiconductor field effect transistor (MOSFET) as an example, refers to a phenomenon that actual electrical performance parameters of multiple transistors, which are originally designed to be consistent, are different on the same chip. Such difference is not caused by design intention, but by various non-ideal factors in the manufacturing process, such as manufacturing process deviation or uneven material properties.

[0023] SPICE (Simulation Program with Integrated Circuit Emphasis) is a powerful integrated circuit simulation program used for simulating and analyzing electronic circuits. Based on the physical characteristics of semiconductor devices and basic circuit theory, it establishes accurate mathematical models to simulate various electronic circuits, helping engineers predict the behavior and performance of circuits under different conditions.

[0024] Figure 3 A schematic diagram showing the change of the standard deviation of local mismatch of a transistor device according to an embodiment of the present application with the reciprocal of the square root of the device area is shown; Figure 4 A semiconductor top view schematic diagram of a test structure for the local mismatch offset rate in a SPICE model according to an embodiment of the present application is shown; Figure 5 A circuit structure schematic diagram of a test structure for the local mismatch offset rate in a SPICE model according to an embodiment of the present application is shown; Figure 6 A layout structure schematic diagram of a test structure for the local mismatch offset rate in a SPICE model according to an embodiment of the present application is shown.

[0025] In measuring the local mismatch offset rate of a transistor device using a SPICE model, transistors of the same size are usually placed two by two in a region in the test structure, and the difference between the performance of two adjacent devices is statistically analyzed.

[0026] Figure 3 The offset rate test graph shown, in which the abscissa 1 / Sqrt (W·L·nf) represents the key factor affecting the mismatch sigma, and the ordinate represents the mismatch sigma; and in the key factor 1 / Sqrt (W·L·nf) of the abscissa, W represents the channel width of the transistor, L represents the channel length of the transistor, and nf represents the number of interdigital (channels).

[0027] In addition, the curves L0 to L4 all refer to Figure 3 straight lines in the graph. Curve L0 represents the curve of the mismatch sigma in the existing model with the change of the key factor; curves L1 to L4 all represent the curve of the mismatch sigma in the new model of the present application with the change of the key factor, and the curve slopes of L1 to L4 are different because the number of interdigital nf in the key factor 1 / Sqrt (W·L·nf) is different. Among the curves L0 to L4, the slope of curve L0 is greater than the slope of curve L4, greater than the slope of curve L3, greater than the slope of curve L2, and greater than the slope of curve L1.

[0028] Specifically, in Figure 3In the present application, the finger number nf in the key factor 1 / Sqrt(W*L* nf) corresponding to the curve L4 to the curve L1 is increasing, for example. In one embodiment, the curve L4 corresponds to a transistor test structure with a finger number nf=2, the curve L3 corresponds to a transistor test structure with a finger number nf=3, and the curve L2 corresponds to a transistor test structure with a finger number nf>3. This is because when a finger structure is used, multiple fingers are equivalent to multiple small transistors in parallel, and when the key factor 1 / Sqrt(W*L* nf) is the same, the larger the finger number nf, the more finger transistors are in parallel in each transistor. Assuming that the process fluctuations experienced by each finger transistor are random and independent, as the finger number increases, these random process fluctuations will cancel each other out on the whole, making the electrical parameters of the entire finger transistor structure more uniform and stable.

[0029] Therefore, when the key factor 1 / Sqrt(W*L* nf) is M, it can be seen that the mismatch value corresponding to the curve L0 in the existing model is greater than the mismatch value corresponding to the curve L4 in the new model, greater than the mismatch value corresponding to the curve L3, greater than the mismatch value corresponding to the curve L2, and greater than the mismatch value corresponding to the curve L1. Therefore, the error of the test structure corresponding to the curve L1 is the smallest.

[0030] For the case where the key factor 1 / Sqrt(W*L* nf) approaches 0, it cannot be determined whether the mismatch standard deviation approaches zero or is upturned. However, in the existing model, the finger number nf increases and the mismatch standard deviation decreases, which can provide a test structure with a finger number nf of at least 2 for testing.

[0031] Therefore, the test structure provided in the present application can reduce the impact of mismatch to some extent by increasing the number of fingers nf, and provide the possibility for mismatch standard deviation measurement when the key factor 1 / Sqrt(W*L* nf) is less than 0.1.

[0032] Further, for the test structure, the accuracy of the measurement can also be improved by other means. The test structure provided in the present application will be described in detail below.

[0033] Reference Figure 4In the test structure for local mismatch offset rate in the SPICE model of the present application, the local mismatch offset rates of the first transistor MOS_A and the second transistor MOS_B are measured. The first transistor MOS_A and the second transistor MOS_B are adjacent and located on a substrate (not shown in the figure), and each transistor comprises: a substrate (not shown in the figure), an epitaxial layer (not shown in the figure) located on the substrate; a body region 120, a source region and a drain region 130 located in the epitaxial layer; a gate 110 located on the epitaxial layer, and the source region and the drain region 130 are located in the body region 120 on both sides of the gate 110. The first transistor MOS_A and the second transistor MOS_B are oppositely arranged. In an embodiment, the first transistor MOS_A and the second transistor MOS_B are, for example, transistors produced in the same batch, or adjacent two transistors on the same substrate.

[0034] The gate 110 of the first transistor MOS_A and the second transistor MOS_B comprises a plurality of interdigital fingers, Figure 4 The structure diagram of each transistor is shown in FIG. 1, in which the gate of each transistor comprises 4 interdigital fingers. In this embodiment, the length L and the width W of the plurality of interdigital fingers in each transistor are, for example, the same. In other embodiments, the length L and the width W of the plurality of interdigital fingers in each transistor can also be different, i.e., the length L and the width W of the interdigital fingers are set correspondingly according to requirements; at least one of the length and the width of the interdigital fingers of the first transistor MOS_A is different from that of the second transistor MOS_B; the area (W·L·nf, nf represents the number of interdigital fingers) of the plurality of interdigital fingers in different transistors can be the same or different.

[0035] In the test structure for local mismatch offset rate in the SPICE model of the present application, the large-area gate is divided into a plurality of interdigital fingers, so that the structure can simultaneously cover the following cases: transistor mismatch structures with the same area and different length and width, transistor mismatch structures with different area and different length and width, transistor mismatch structures with the same length and different width, transistor mismatch structures with the same width and different length, etc.

[0036] Each transistor in the test structure comprises 6 lead-out ends as test ends, as shown in FIG. 2. Figure 5 The first transistor MOS_A and the second transistor MOS_B respectively comprise a gate end G, a substrate end B, a first source end S1, a second source end S2, a first drain end D1 and a second drain end D2. The first source end S1 and the second source end S2 are both located at the source end of the transistor, but the distance between the second source end S2 and the substrate end B is less than the distance between the first source end S1 and the substrate end B, i.e., the first source end S1 and the second source end S2 are apart by a predetermined distance. The first drain end D1 and the second drain end D2 are both located at the drain end of the transistor, but the distance between the second drain end D2 and the substrate end B is less than the distance between the first drain end D1 and the substrate end B, i.e., the first drain end D1 and the second drain end D2 are apart by a predetermined distance.

[0037] Further, as shown in Figure 5 The distance between the first source end S1 and the gate end G is greater than the distance between the second source end S2 and the gate end G, and the distance between the first drain end D1 and the gate end G is greater than the distance between the second drain end D2 and the gate end G. The distance can also be understood as the length of the current path. The longer the current path, the greater the equivalent resistance on the path, which will cause the test result to deviate and increase the measurement error. In addition, the longer current path may also be affected by parasitic capacitance, electromagnetic interference, etc., further increasing the test error.

[0038] In the present application, the six terminals in the test structure can realize Kelvin test, that is, the test signal application end and the test result end in the circuit are completely separated, and the current and voltage paths in the test structure are also separated, avoiding mutual interference, thereby improving the test precision. Specifically, the first source end S1 and the first drain end D1 in the present application are, for example, a first loop, and the first loop is used to apply a test signal; the second source end S2 and the second drain end D2 are, for example, a second loop, and are a test loop, and the second source end S2 and the second drain end D2 serve as test ends. In addition, since the distance between the second source end S2 and the second drain end D2 and the substrate end B and the gate end G of the transistor is smaller, the resistance can also be reduced, thereby improving the test precision.

[0039] In the SPICE model simulation, the first source end S1 and the second source end S2 are the source ends of the carriers, and in the first transistor MOS_A and the second transistor MOS_B, the source and the drain are symmetric in physical structure, but in actual application, they are usually distinguished according to the circuit connection and the working mode. The first drain end D1 and the second drain end D2 are the ends where the carriers flow out of the first transistor MOS_A and the second transistor MOS_B. When the transistor is in the on state, according to different working modes (such as enhancement mode or depletion mode, N channel or P channel), the carriers will flow from the source to the drain. The substrate end B is usually connected to a fixed potential, and for an N channel transistor, the substrate end B is generally connected to the lowest potential (such as ground GND), while for a P channel transistor, the substrate end B is usually connected to the highest potential. The gate end G plays a key role in controlling the conduction or cutoff of the transistor, and by applying a voltage (VGS) at the gate end G, the formation of the channel and the flow of the carriers can be controlled.

[0040] In the test structure of the local mismatch offset rate in the SPICE model of the present application, by providing different test signals to the first transistor MOS_A and the second transistor MOS_B, such as voltage-to-current or current-to-voltage, etc., by respectively acquiring the data on the test ends such as the second source end S2 and the second drain end D2, a more accurate test result can be obtained, and the detection of the mismatch offset of the large-area transistor is also more accurate.

[0041] Further, Figure 6 The layout design shown is a top view of the layout design of either the first transistor MOS_A or the second transistor MOS_B. In the layout design, the head and tail ends of the gate 110 of the transistor are connected to the first metal layer 160 via the via 140, i.e. the head ends of the plurality of interdigital fingers are connected to the same first metal layer 160 and / or the tail ends are connected to the same first metal layer 160; the source region and the drain region 130 are located in the body region 120, and the source region and the drain region 130 are connected to the second metal layer 150 via the via 140, i.e. the second metal layer 150 serves as the lead-out layer of the source region and the drain region 130, and the second metal layer 150 forms lead-out ends on the two sides of the source region and the drain region 130, respectively, for distinguishing the source region and the drain region, as shown in the figure. Figure 6 In addition, via different positions of the second metal layer 150, the first drain end D1, the second drain end D2, the first source end S1 and the second source end S2 in the test structure can be formed.

[0042] Figure 6 In the layout design of the test structure, it can be understood that the first metal layer 160 and the second metal layer 150 are separated by an insulating layer (not shown in the figure) and are located in different horizontal planes of the insulating layer, i.e. in the same horizontal plane, the first metal layer 160 and the second metal layer 150 will not be connected.

[0043] Further, the application also provides a test method for local mismatch offset rate in a SPICE model, comprising: using the test structure for local mismatch offset rate in the SPICE model to test the local mismatch offset rate. Specifically, Figure 7 A flowchart of a test method for local mismatch offset rate in a SPICE model according to an embodiment of the application is shown, which is, for example, a test method for measuring current with voltage, comprising the following steps.

[0044] S10: applying a test voltage to the gate end and the first source end of the first transistor and / or the second transistor.

[0045] In this step, a suitable test voltage signal is applied to the gate and the first source end of the first transistor MOS_A and the second transistor MOS_B for setting the working point of the transistor. The working point of the transistor includes amplification, cutoff, saturation, etc.

[0046] If the test method adopts a method for measuring current with voltage, a suitable test current signal is applied to the gate and the first source end of the first transistor MOS_A and the second transistor MOS_B.

[0047] S20: acquiring current data via the second source end and / or the second drain end of the first transistor and / or the second transistor.

[0048] In this step, current data is acquired via the second source terminal and / or the second drain terminal of the first transistor MOS_A and the second transistor MOS_B, which for example includes drain current.

[0049] If the test method is to measure voltage by current, voltage data is acquired, which includes voltage between gate and source, voltage between drain and source, etc.

[0050] S30: multiple times change the test voltage and acquire multiple corresponding current data.

[0051] In this step, the test voltage is changed to change the working point of the first transistor MOS_A and the second transistor MOS_B, and then the corresponding current data at the working point is acquired; the test voltage is changed again and the corresponding current data is acquired; the step of changing the test voltage and acquiring the corresponding current data is repeated multiple times.

[0052] If the test method is to measure voltage by current, the step of changing the test current and acquiring the corresponding voltage data is repeated multiple times.

[0053] S40: according to the acquired current data, the key electrical parameters of the first transistor and the second transistor are calculated and compared.

[0054] In this step, the key electrical parameters of the first transistor MOS_A and the second transistor MOS_B include threshold voltage (Vth), transconductance (gm), etc. For the first transistor MOS_A and the second transistor MOS_B of the same design but possibly having local mismatch, the difference values of their electrical parameters are acquired by comparison, which can directly reflect the degree of local mismatch of the transistors.

[0055] According to the test structure and method of local mismatch offset rate in the SPICE model of the embodiment of the present application, six test terminals are arranged in two transistors in a test structure, including gate terminal, substrate terminal, first source terminal, second source terminal, first drain terminal and second drain terminal. Compared with four test terminals in the traditional test structure, the test structure with six test terminals provided by the present application can reduce the influence of parasitic resistance in the circuit and improve the measurement accuracy.

[0056] Further, the test structure and method of local mismatch offset rate in the SPICE model of the present application, for a large-area transistor mismatch structure, the transistor is set to a finger structure, so that a large-area transistor mismatch structure includes multiple fingers, so that the simulation test of the transistor mismatch structure with different lengths in the same area, the transistor mismatch structure with different lengths in different areas, the transistor mismatch structure with different widths in the same length, the transistor mismatch structure with different lengths in the same width, etc. can be realized, and the layout area can be maximally reduced to save mask cost. At the same time, for small-area transistor mismatch structures, the local mismatch model simulation under different conditions can also be more accurately simulated.

[0057] In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details, nor limit the present application to the specific embodiments described. Obviously, many modifications and variations can be made in light of the above description. The present description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A test structure for local mismatch offset rate in a SPICE model, comprising: The first transistor and the second transistor each include four test terminals: a first source terminal, a first drain terminal, a gate terminal, and a substrate terminal. The first transistor and the second transistor each include two test terminals: a second source terminal and a second drain terminal.

2. The test structure according to claim 1, wherein, In either the first transistor or the second transistor, the first source terminal and the second source terminal are separated by a predetermined distance, and the first drain terminal and the second drain terminal are separated by a predetermined distance.

3. The test structure according to claim 2, wherein, The distance between the first source terminal and the gate terminal is greater than the distance between the second source terminal and the gate terminal, and the distance between the first drain terminal and the gate terminal is greater than the distance between the second drain terminal and the gate terminal.

4. The test structure according to claim 1, wherein, The gates of the first transistor and the second transistor include a plurality of interdigitated fingers.

5. The test structure according to claim 4, wherein, The tips of the plurality of interdigitated fingers are connected via a first metal layer; and / or The tail ends of the plurality of interdigitated fingers are connected via a first metal layer.

6. The test structure according to claim 5, wherein, The length and width of the multiple interdigitated fingers are all the same.

7. The test structure according to claim 5, wherein, In the first transistor and the second transistor, the sum of the areas of the plurality of interdigitated fingers may be the same or different.

8. The test structure according to claim 7, wherein, At least one of the length and width of the interdigitated fingers of the first transistor is different from the interdigitated fingers of the second transistor.

9. The test structure according to claim 1, wherein, The first transistor and / or the second transistor include: Substrate; Epitaxial layer located on the substrate; The body region, source region, and drain region located in the epitaxial layer; The gate is located on the epitaxial layer, and the source and drain regions are located in the body regions on both sides of the gate. The substrate terminal is electrically connected to the substrate, the gate terminal is electrically connected to the gate, the first drain terminal and the second drain terminal are electrically connected to the drain region, and the first source terminal and the second source terminal are electrically connected to the source region.

10. A method for testing the local mismatch offset rate in a SPICE model, wherein, include: The local mismatch offset rate is tested using the test structure of the SPICE model as described in any one of claims 1-9.

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